JP2009135718A - Switching amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute negative feedback without using an LPF in a negative feedback path in a pulse width modulation circuit. <P>SOLUTION: By a current based on an audio signal eS and a signal generated by amplitude-attenuating and inverting a pulse signal output from a switching circuit, a voltage of a first integrator circuit C1 is changed in a first period T1 of a clock signal MCLK while the voltage of the first integrator circuit C1 is reversely changed in a second period T2 on the basis of a fixed bias current, and also, a voltage of a second integrator circuit C2 is changed while the voltage of the second integrator circuit C2 is reversely changed in a period T3 on the basis of the bias current. Time duration from the start of the second period T2 until the time when the voltage of the first integrator circuit C1 reaches a reference voltage Vth is detected. Time duration from the start of the third period T3 until the time when the voltage of the second integrator circuit C2 reaches the reference voltage Vth is detected. A pulse signal is generated on the basis of the time duration until the voltages of the integrator circuits C1, C2 reach the reference voltage Vth so as to have a pulse width of the time duration. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a switching amplifier using a pulse width modulation circuit.

  FIG. 13 is a block diagram showing a pulse width modulation circuit disclosed by the present applicant in the following prior application 1. The pulse width modulation circuit 41 charges the first integration circuit C1 in the first period T1 of the clock signal MCLK based on the current Ic + Δi based on the audio signal eS, and in the second period T2 based on the constant bias current Id. The voltage of the first integration circuit C1 is discharged, the second integration circuit C2 is charged, and the voltage of the second integration circuit C2 is discharged in the third period T3 based on the bias current Id.

  Then, the time from when the second period T2 is started until the voltage of the first integration circuit C1 reaches the reference voltage Vref is detected, and after the third period T3 is started, the voltage of the second integration circuit C2 is The time until the reference voltage Vref is reached is detected. The voltage of the first integrating circuit C1 is maintained until the third period T3 starts after the voltage of the first integrating circuit C1 reaches the reference voltage Vref, and the voltage of the second integrating circuit C2 reaches the reference voltage Vref. Then, the voltage of the second integrating circuit C2 is maintained until the fourth period T4 is started. Based on the time until the voltage of the first and second integration circuits C1 and C2 reaches the reference voltage Vref, a pulse signal having a pulse width of the time is generated.

  Here, although the pulse width modulation circuit 41 is applied to an audio switching amplifier, it is conceivable to provide a negative feedback circuit in order to remove a noise component included in the output of the switching amplifier. As a method for negative feedback of the switching amplifier, a method is used in which a high-frequency component (carrier component) is removed from the output signal of the switching amplifier by an LPF or a notch filter, and a signal converted into an analog signal is negatively fed back to the input signal. However, according to this method, since the frequency characteristic is provided by the filter in the negative feedback path, the influence of the frequency characteristic occurs on the negative feedback signal, and as a result, a waveform different from the intended waveform is generated. There is a problem of being output from the switching amplifier.

[Patent Application 1] Japanese Patent Application No. 2007-111251

  The present invention has been made to solve the above-described problems, and an object thereof is to realize negative feedback without using a filter in a negative feedback path in a switching amplifier using the pulse width modulation circuit having the above-described configuration. It is to provide a switching amplifier that can.

  A switching amplifier according to a preferred embodiment of the present invention includes a pulse width modulation circuit, and a switching circuit that switches a predetermined power supply voltage supplied from a voltage source based on a modulation signal output from the pulse width modulation circuit. .

  The pulse width modulation circuit changes a voltage in the first integration circuit in a first period which is a half cycle of a predetermined clock signal based on a current based on an input signal and a signal from an inversion circuit described later, and a constant bias current. The voltage in the first integration circuit is changed in the opposite direction to the increase / decrease direction in the first period in a second period following the first period that is shifted from the first period by a half cycle from the first period, and the input signal A voltage in a second integration circuit different from the first integration circuit is changed based on a current based on a signal from an inversion circuit described later, and the second period shifted from the second period by a half cycle based on the bias current. A voltage control circuit that changes the voltage in the second integration circuit in the third period following the period in a direction opposite to the increase / decrease direction in the second period, and the second period starts. A first detection circuit for detecting a time until the voltage in the first integration circuit reaches a predetermined reference voltage, and a voltage in the second integration circuit after the start of the third period is a predetermined reference voltage Based on the second detection circuit for detecting the time until the signal reaches the first time, and the time repeatedly output from the first detection circuit and the second detection circuit every half cycle of the clock signal. A pulse signal generation circuit that generates a pulse signal having an amplitude, an amplitude attenuation circuit that attenuates the amplitude of the pulse signal output from the switching circuit, and an inversion circuit that inverts the pulse signal whose amplitude is attenuated by the amplitude attenuation circuit Is provided.

  By changing the voltages of the first integration circuit and the second integration circuit according to the current based on the input signal and the current based on the signal obtained by amplitude-attenuating and inverting the pulse signal from the switching circuit, a negative feedback path is provided. Negative feedback can be realized without providing a filter. That is, it is one of the features of the present invention that the pulse signal that is the output signal of the switching circuit 2 is fed back instead of the analog signal that is the output of the filter of the switching amplifier.

  In a preferred embodiment, the voltage control circuit converts a voltage based on the input signal into a current, converts a voltage based on the signal from the inverting circuit into a current, and adds these currents. A first integration circuit is charged in the first period based on the current converted by the voltage-current conversion circuit, and in the second period based on the current converted by the voltage-current conversion circuit. The second integration circuit is charged.

  According to the present invention, the voltage of the first integration circuit and the second integration circuit is changed by the current based on the input signal and the current based on the signal obtained by amplitude-attenuating and inverting the pulse signal from the switching circuit, Negative feedback can be realized without providing a filter in the negative feedback path.

Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings. However, the present invention is not limited to these embodiments.
FIG. 1 is a block diagram showing a switching amplifier to which a pulse width modulation (PWM) circuit is applied. FIG. 2 is a block circuit diagram showing an embodiment of the pulse width modulation circuit shown in FIG. This switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, a first power supply 4 that supplies positive and negative power supply voltages + EB and -EB, and a second power supply. And a power source 5. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

  The pulse width modulation circuit 1 generates and outputs a pulse width modulation signal PWMout by performing pulse width modulation on the audio signal eS as an input signal output from the audio signal generation source AU. The pulse width modulation signal PWMout output from the pulse width modulation circuit 1 is input to the switching circuit 2.

  In the switching circuit 2, positive and negative power supply voltages + EB and -EB are supplied from the first power supply 4 and the second power supply 5, and the power supply voltages + EB and -EB are alternately switched based on the pulse width modulation signal PWMout. That is, the switching circuit 2 includes a switch element SW-A that operates on and off based on the pulse width modulation signal PWMout, an inverter 2a that inverts the phase of the pulse width modulation signal PWMout output from the pulse width modulation circuit 1, Based on the pulse width modulation signal PWMout ′ obtained by inverting the pulse width modulation signal PWMout by the inverter 2a, the switch element SW-B is turned on and off, and is connected to both ends of both switch elements SW-A and SW-B. Diodes DA and DB.

  Both switch elements SW-A and SW-B are alternately turned on and off by the pulse width modulation signal PWMout and the inverted pulse width modulation signal PWMout ′, and output signal eout (ie, switched positive and negative power supplies). Voltage + EB, -EB) is supplied to the low-pass filter circuit 3 and the load RL. Further, the output signal eout of the switching circuit 2 is negatively fed back to the pulse width modulation circuit via a negative feedback path, which will be described later, thereby removing the noise component contained in the output signal eout.

  The low-pass filter circuit 3 includes an LC circuit including a coil L0 and a capacitor C0. The low-pass filter circuit 3 is a circuit that removes a high-frequency component of the output signal output from the switching circuit 2 and supplies it to the load RL, and has a cutoff frequency of 60 kHz, for example. In the low-pass filter circuit 3, the high-frequency components of the switched positive and negative power supply voltages + EB and -EB are removed, and the output is supplied from the load RL as a sound by being supplied to the load RL.

  As shown in FIG. 2, the pulse width modulation circuit 1 includes a clock generation circuit 11, a dead time generation circuit 12, a falling edge detection circuit 42, a voltage-current conversion circuit 13, and first to fourth switches SW1 to SW1. SW4, first and second integration circuits C1 and C2, a discharge bias current source 14, a current bypass circuit 15, a signal output circuit 16, an amplitude attenuation circuit 18, and an inverting circuit 19 are provided.

  The clock generation circuit 11 is a circuit that generates a reference clock signal MCLK. The reference clock signal MCLK is a clock signal having a duty ratio of approximately 50%, and serves as a reference signal for the first and second switching signals φ1 and φ2 for switching the first and second switches SW1 and SW2. The clock generation circuit 11 outputs the reference clock signal MCLK to the dead time generation circuit 12. Note that the clock generation circuit 11 may be provided outside the pulse width modulation circuit 1 and configured to supply the reference clock signal MCLK to the pulse width modulation circuit 1 as an external clock signal.

  Based on the reference clock signal MCLK from the clock generation circuit 11, the dead time generation circuit 12 generates a first switching signal φ1 and a second switching signal φ2 having an antiphase relationship with the first switching signal φ1. This is a circuit to be generated. More specifically, the dead time generation circuit 12 performs a predetermined time when the levels of the first and second switching signals φ1 and φ2 are inverted so that the output levels of the first and second switching signals φ1 and φ2 do not coincide at the same time. Each circuit is a delay circuit.

  That is, as shown in FIGS. 3A and 3B, the first switching signal φ1 is delayed from the low level to the high level by a predetermined period Δt when the reference clock signal MCLK is inverted from the low level to the high level. Invert. The first switching signal φ1 is inverted from the high level to the low level simultaneously when the reference clock signal MCLK is inverted from the high level to the low level. On the other hand, as shown in FIGS. 3A and 3C, the second switching signal φ2 is delayed from the low level to the high level by a predetermined period Δt when the reference clock signal MCLK is inverted from the high level to the low level. Invert. Note that the second switching signal φ2 is simultaneously inverted from the high level to the low level when the reference clock signal MCLK is inverted from the low level to the high level.

  In this way, when the first and second switches SW1 and SW2 are turned on by the first and second switching signals φ1 and φ2, respectively, the first and second integration circuits C1 are prevented from being turned on at the same time. , C2 can perform charging operations simultaneously, thereby preventing an error from occurring in the output of the pulse width modulation signal PWMout. The first and second switching signals φ1 and φ2 are output to the first and second switches SW1 and SW2, respectively.

  In the following description, for the sake of convenience, as shown in FIG. 3A, the period in which the reference clock signal MCLK first becomes high level is the first period T1, and the subsequent low level period is the second period T2. The subsequent high level period is defined as a third period T3, and the subsequent low level period is defined as a fourth period T4.

  Returning to FIG. 2, the falling edge detection circuit 42 is a circuit that outputs first and second set signals set <b> 1 and set <b> 2 that are output to first and second RS flip-flop circuits 43 and 44 described later. That is, the falling edge detection circuit 42 detects the falling edge when the first and second switching signals φ1 and φ2 from the dead time generation circuit 12 are inverted from the high level to the low level, and the detected timing is detected. This circuit outputs the first and second set signals set 1 and set 2 to the first and second RS flip-flop circuits 43 and 44.

  The voltage / current conversion circuit 13 performs voltage / current conversion on the audio signal eS supplied from the audio signal generation source AU to the pulse width modulation circuit 1, converts the PWM signal −enfb supplied from the inverting circuit 19 into voltage / current, and converts them. Add current. The voltage-current conversion circuit 13 has a charging bias current source (for example, constituted by a power supply Vo and a resistor R2). The voltage-current conversion circuit 13 charges the first and second integration circuits C1, C2 in the negative direction with respect to the reference voltage (for example, ground potential) by the added current. As will be described later, the voltage-current conversion circuit 13 is connected to the first and second integration circuits C1 and C2 via the first and second switches SW1 and SW2, respectively. The first and second integration circuits C1 and C2 are charged in the minus direction by drawing the electric charge accumulated in C2.

  Here, when the conversion conductance in the voltage-current conversion circuit 13 is Gm, the current Δi converted from the audio signal eS by the voltage-current conversion circuit 13 can be expressed by Δi = Gm · eS. The current Δinfb obtained by converting the PWM signal −enfb from the inverting circuit 19 by the voltage / current conversion circuit 13 can be expressed as Gm · −enfb. Assuming that the charging bias current in the charging bias current source is Ic, the current drawn from the first and second integrating circuits C1 and C2 can be expressed as Ic + Gm · eS + Gm · −enfb = Ic + Δi + Δinfb.

  The discharge bias current source 14 is a circuit that supplies a discharge bias current Id. As will be described later, the discharge bias current source 14 is connected to the first and second integration circuits C1 and C2 via the third and fourth switches SW3 and SW4, respectively. By supplying the second integration circuits C1 and C2, the first and second integration circuits C1 and C2 are discharged in the plus direction.

  The current bypass circuit 15 includes a diode D 1 and a voltage source 17. The current bypass circuit 15 is configured to discharge the bias current source when the first and second integrating circuits C1 and C2 are not charged in the negative direction by the voltage-current conversion circuit 13 and are not discharged in the positive direction by the discharge bias current source 14. 14 is a circuit through which a discharging current Id from 14 flows.

  The first and second switches SW1 and SW2 are turned on and off to charge the voltage accumulated in the first and second integrating circuits C1 and C2 in the negative direction. The first and second switches SW1, SW2 are turned on and off based on the first and second switching signals φ1, φ2 output from the dead time generation circuit 12. That is, as shown in FIG. 3B, the first switch SW1 is turned on when the first switching signal φ1 is at a high level, and is turned off when the first switching signal φ1 is at a low level. As shown in FIG. 3C, the second switch SW2 is turned on when the second switching signal φ2 is at a high level, and is turned off when the second switching signal φ2 is at a low level.

  The third and fourth switches SW3 and SW4 are turned on and off in order to cause the first and second integration circuits C1 and C2 to discharge the discharge bias current Id supplied by the discharge bias current source 14 in the positive direction. Circuit. The third and fourth switches SW3 and SW4 are turned on and off based on the control signals φ3 and φ4 from the signal output circuit 16. That is, the third switch SW3 is turned on when the control signal φ3 is at a high level, and is turned off when the control signal φ3 is at a low level. The fourth switch SW4 is turned on when the control signal φ4 is at a high level and turned off when the control signal φ4 is at a low level. The control signals φ3 and φ4 are output from second and fourth NAND circuits NA2 and NA4, which will be described later, of the signal output circuit 16.

  Each of the first and second integrating circuits C1 and C2 is configured by a charging capacitor, and is a circuit that charges by storing a predetermined charge and discharges by discharging the charge.

  Specifically, in the first integration circuit C1, the first switch SW1 is turned on (the third switch SW3 is turned off at this time) in the first period T1 (excluding the predetermined time Δt that is strictly a dead time). ), The charge accumulated in the first integration circuit C1 flows to the voltage-current conversion circuit 13, and is thereby charged in the minus direction. In addition, the first integrating circuit C1 is configured to turn on the third switch SW3 during the next second period T2 (at this time, the first switch SW1 is turned off). It is discharged in the positive direction by the current Id.

  On the other hand, in the second integration circuit C2, the second switch SW2 is turned on in the second period T2 during which the first integration circuit C1 is discharged in the positive direction (excluding the predetermined time Δt that is strictly a dead time) When the fourth switch SW4 is turned off, the charge accumulated in the second integration circuit C2 flows into the voltage-current conversion circuit 13 and is thereby charged in the negative direction. In addition, the second integration circuit C2 is configured to turn on the fourth switch SW4 during the next third period T3 (in this case, the second switch SW2 is turned off). It is discharged in the positive direction by the current Id.

  As described above, in the first and second integrating circuits C1 and C2, the unit period (for example, the first period T1 or the second period T2) in which the levels of the first and second switching signals φ1 and φ2 are maintained alternately. Charging and discharging are performed.

  Here, the circuit connection configuration relating to charging / discharging of the first and second integrating circuits C1 and C2 will be described. The voltage-current conversion circuit 13 is connected to one end of each of the first and second switches SW1 and SW2, and the first The other end of the switch SW1 is connected to one end of the first integrating circuit C1 (see point A in FIG. 2), thereby forming a charging path in the minus direction of the first integrating circuit C1. The other end of the first integrating circuit C1 is connected to the ground potential. One end of the first integrating circuit C1 is also connected to one end of the third switch SW3, and the other end of the third switch SW3 is connected to the discharging bias current source 14, and thereby the first integrating circuit C1 A discharge path in the positive direction is formed.

  On the other hand, the other end of the second switch SW2 is connected to one end of the second integrating circuit C2 (see point B in FIG. 2), thereby forming a charging path in the negative direction of the second integrating circuit C2. The The other end of the second integration circuit C2 is connected to the ground potential. One end of the second integrating circuit C2 is also connected to one end of the fourth switch SW4, and the other end of the fourth switch SW4 is connected to the discharging bias current source 14, thereby allowing the second integrating circuit C2 to A discharge path in the positive direction is formed.

  The signal output circuit 16 includes first and second comparison circuits 23 and 24, first and second RS flip-flop circuits 43 and 44, and a fifth NAND circuit NA5, and includes first and second integration circuits C1 and C2. Based on the voltage, a pulse width modulation signal PWMout and third and fourth switching signals φ3 and φ4 are output.

  The first comparison circuit 23 has a negative (−) side input terminal connected to one end of the first integration circuit C1, and a positive (+) side input terminal connected to the source of the reference voltage Vref. The second comparison circuit 24 has a negative (−) side input terminal connected to one end of the second integration circuit C2, and a positive (+) side input terminal connected to the source of the reference voltage Vref. The output of the first comparison circuit 23 is input to the first RS flip-flop circuit 43 as the first reset signal res1. The output of the second comparison circuit 24 is input to the second RS flip-flop circuit 44 as the second reset signal res2.

  The first and second RS flip-flop circuits 43 and 44 are circuits for holding the outputs of the first and second comparison circuits 23 and 24, respectively, for a predetermined period. The first RS flip-flop circuit 43 is configured by combining the first and second NAND circuits NA1 and NA2. Within the first RS flip-flop circuit 43, each output terminal of the first and second NAND circuits NA1 and NA2 is one of the other. Connected to the input terminal.

  The other input terminal of the first NAND circuit NA1 is connected to the output terminal of the first comparison circuit 23 and is a terminal to which a first reset signal res1 as an RS flip-flop is input, and the other input terminal of the second NAND circuit NA2. Is a terminal that is connected to the falling edge detection circuit 42 and receives the first set signal set1 as an RS flip-flop. The output terminal of the second NAND circuit NA2 is connected to the third switch SW3. The opening / closing of the third switch SW3 is controlled by a control signal φ3 output from the output terminal of the second NAND circuit NA2.

  On the other hand, the second RS flip-flop circuit 44 is configured by combining the third and fourth NAND circuits NA3 and NA4. In the second RS flip-flop circuit 44, the output terminals of the third and fourth NAND circuits NA3 and NA4 are mutually connected. Is connected to one input terminal.

  The other input terminal of the third NAND circuit NA3 is connected to the output terminal of the second comparison circuit 24 and is a terminal to which a second reset signal res2 as an RS flip-flop is input. The other input terminal of the fourth NAND circuit NA4 Is a terminal that is connected to the falling edge detection circuit 42 and receives the second set signal set2 as an RS flip-flop. The output terminal of the fourth NAND circuit NA4 is connected to the fourth switch SW4. The opening / closing of the fourth switch SW4 is controlled by a control signal φ4 output from the output terminal of the second NAND circuit NA2.

  The input terminal of the fifth NAND circuit NA5 is connected to the output terminal of the first NAND circuit NA1 of the first RS flip-flop circuit 43 and the output terminal of the third NAND circuit NA3 of the second RS flip-flop circuit 44. The output signal rsout1 is output from the output terminal of the first NAND circuit NA1, and the output signal rsout2 is output from the output terminal of the third NAND circuit NA3. The pulse width modulation signal PWMout is output from the output terminal of the fifth NAND circuit NA5.

  The amplitude attenuation circuit 18 is a circuit that attenuates the amplitude value of the output signal eout output from the switching circuit 2 and supplies the attenuated pulse width modulation signal enfb to the inverting circuit 19. That is, the amplitude attenuating circuit 18 adjusts the output signal eout switched and amplified by the switching circuit 2 to an amplitude value that can be negatively fed back and added to the audio signal eS. For example, when the high level of the output signal eout of the switching circuit 2 is + 50V and the low level is −50V, the amplitude attenuation circuit 18 generates the pulse width modulation signal enfb whose high level is + 5V and low level is −5V. .

  The amplitude attenuating circuit 18 includes, for example, resistors R1 and R2 for voltage division. One end of the resistor R1 is connected to the output end (point X in FIG. 1), and the other end is one end of the resistor R2. And the input of the inverting circuit 19. One end of the resistor R2 is connected to the other end of the resistor R1 and the input of the inverting circuit 19, and the other end is connected to the ground potential. Therefore, the amplitude attenuation circuit 18 multiplies the amplitude of the output signal eout from the switching circuit 2 by R2 / (R1 + R2).

  The inverting circuit 19 converts the pulse width modulation signal enfb from the amplitude attenuating circuit 18 from the current Ic + Δi based on the audio signal charging the first and second integrating circuits C1 and C2 into a voltage / current converted current by the voltage / current converting circuit 13. In order to subtract Δinfb, the pulse width modulation signal enfb from the amplitude attenuation circuit 18 is inverted to generate a pulse width modulation signal -enfb.

  The pulse width modulation signal −enfb generated by the inverting circuit 19 is converted into a current Δinfb in the voltage / current conversion circuit 13 and added to the current Ic + Δi based on the audio signal for charging the first and second integration circuits C1 and C2. The

  The voltage-current conversion circuit 13 includes a transistor Q1, a diode D1, resistors R2 and R3, and a power supply Vo. The collector of the transistor Q1 is connected to the output terminal (that is, the first and second switches SW1, SW2) of the voltage-current conversion circuit 13, the base thereof is connected to the ground potential via the diode D1, and the emitter thereof is connected to the resistor R2 and It is connected to each end of R3. The other end of the resistor R2 is connected to the audio signal generation source AU via the power supply voltage Vo. The other end of the resistor R3 is connected to the output terminal of the inverting circuit 19.

  With such a configuration, the voltage-current conversion circuit 13 causes the current Ic + Δi based on the audio signal to flow from the first and second integration circuits C1 and C2 to the resistor R2 and the power supply Vo via the collector-emitter of the transistor Q1, The current Δinfb based on the signal from the inverting circuit 19 flows on the R3 side, and as a result, the first integration circuit C1 and the second integration circuit C2 are charged in the negative direction by the current Ic + Δi + Δinfb obtained by adding these currents.

  Here, voltage waveforms of the first and second integration circuits C1 and C2 will be described. First, for simplicity, the case of no feedback (assuming that there is no signal from the inverting circuit 19) will be described with reference to FIG. FIG. 4 is a diagram showing the relationship between the level change of the first switching signal φ1 and the voltage waveform at one end of the first integrating circuit C1 (see point A in FIG. 2) when there is no feedback.

  The first integration circuit C1 is charged in the minus direction because the first switch SW1 is turned on when the first switching signal φ1 becomes a high level. The slope of the voltage waveform during charging (the voltage at point A in FIG. 2) depends on the magnitude of the current (Ic + Δi), that is, the positive and negative directions and the magnitude of the amplitude of the audio signal eS.

  4 shows a waveform when the audio signal eS is no signal, and a voltage waveform of the reference sign S1 shows a waveform when the audio signal eS is positive and the amplitude is relatively large. The voltage waveform of S2 shows a waveform when the audio signal eS is negative and the amplitude is relatively large.

  According to the figure, the voltage waveform S1 when the audio signal eS is positive and its amplitude is relatively large has a larger slope than the voltage waveform S0 when the audio signal eS is no signal. The voltage waveform S2 when the audio signal eS is negative and the amplitude thereof is relatively large is smaller than the voltage waveform S0 when the audio signal eS is no signal.

  That is, due to charging in the negative direction in the first integration circuit C1, the voltage Vth at the start of charging is minimized when the level of the first switching signal φ1 is inverted. For example, when the audio signal eS is no signal, the minimum charging voltage is V0 as shown in FIG. When the audio signal eS is positive and the amplitude thereof is relatively large, the minimum charging voltage is V1 (<V0). When the audio signal eS is negative and the amplitude thereof is relatively large, the minimum charging voltage is V2 (> V0).

  Charging in the minus direction in the first integrating circuit C1 is continued until the level of the first switching signal φ1 is inverted, and when the first switching signal φ1 is inverted to become a low level, the first switch SW1 is turned off. At that time, since the control signal φ3 is inverted from the low level to the high level and is output to the third switch SW3, the third switch SW3 is turned on.

  Since the point A of the first integrating circuit C1 is connected to the discharging bias current source 14, the first integrating circuit C1 is discharged in the plus direction by the ON operation of the third switch SW3. The voltage waveform during the discharge in the positive direction of the first integration circuit C1 during the second period T2 is that the discharge bias current Id flowing through the first integration circuit C1 is always constant, so the positive and negative directions of the audio signal eS. The slope is constant regardless of the magnitude of the amplitude. That is, as shown in FIG. 4, the slope of the voltage waveform when the first integrating circuit C1 is discharged in the positive direction is the voltage waveform when the first integrating circuit C1 is charged in the negative direction (first period T1). It is constant regardless of the inclination of.

  That is, in the first period T1, the first integration circuit C1 is charged in the minus direction, but the charge amount in this charging depends on the positive and negative directions and the amplitude of the audio signal eS. In the second period T2, the first integrating circuit C1 is discharged in the plus direction. In this case, since the discharge amount is constant, the first integrating circuit C1 starts discharging in the plus direction. The time until the terminal voltage of the first integrating circuit C1 reaches the threshold voltage Vth (after the transition to the second period T2) depends on the positive and negative directions and the amplitude of the audio signal eS.

  For example, when the audio signal eS is positive and the amplitude is relatively large, the terminal voltage of the first integration circuit C1 when the discharge in the positive direction is started becomes the minimum charging voltage V1. In this case, the time until the terminal voltage of the first integration circuit C1 reaches the threshold voltage Vth (see t1 in FIG. 4) is longer than that in the case where the audio signal eS is no signal (see t0 in FIG. 4). . On the other hand, when the audio signal eS is negative and the amplitude is relatively large, the terminal voltage in the first integration circuit C1 when the discharge in the positive direction is started becomes the minimum charging voltage V2. In this case, the time until the terminal voltage of the first integration circuit C1 reaches the threshold voltage Vth (see t2 in FIG. 4) is shorter than that in the case where the audio signal eS is no signal (see t0 in FIG. 4). .

  Therefore, the time t from when the first integrator circuit C1 starts discharging in the positive direction until the terminal voltage of the first integrator circuit C1 reaches the threshold voltage Vth is in the positive and negative direction and the amplitude of the audio signal eS. The time t from when the second integrator circuit C2 starts to discharge in the positive direction until the terminal voltage of the second integrator circuit C2 reaches the threshold voltage Vth is also the same as the terminal voltage of the first integrator circuit C1. , Depending on the positive and negative directions and the amplitude of the audio signal eS, the first integration circuit C1 and the second integration circuit C1 in the clock generation circuit 11 to the current bypass circuit 15 each cycle of the clock signal MCLK. The discharge time t is generated alternately, and the signal output circuit 16 combines the discharge time t as an off period to generate the pulse width modulation signal PWMout.

  Here, the capacities of the first and second integrating circuits C1 and C2 are the same (= C), and the period that is the charging time of the first and second integrating circuits C1 and C2 is T (for example, corresponding to the first period T1). Then, the minimum charging voltage (potential difference from the start of charging in the minus direction to the end) Vc is represented by Vc = [(Ic + Δi) · T] / C.

  The time t from when the first integrator circuit C1 (or second integrator circuit C2) starts discharging in the positive direction until the voltage of the first integrator circuit C1 (or second integrator circuit C2) reaches the threshold voltage Vth is Since t = [C · Vc / Ib, t = [(Ic + Δi) · T] / Id. Substituting Δi = Gm · eS into this equation yields t = (Gm · T / Id) · eS + Ic · T / Id. That is, the time t changes in proportion to the audio signal eS.

  Further, since the modulation degree m in the pulse width modulation circuit 1 is m = t / T− (T−t) / T, if it is modified and t = [(Ic + Δi) · T] / Id is considered, m = 2Δi / Id + 2Ic / Id−1. Here, when the discharge bias current Id is set to twice the charge bias current Ic (Id = 2Ic), the modulation degree m is m = Δi / Ic = (Gm / Ic) · eS. That is, the modulation degree m depends on the audio signal eS. Note that setting the discharge bias current Id to be twice the charge bias current Ic suppresses the occurrence of offset because the proportional relationship between the modulation degree m and the audio signal eS becomes clear as shown in the above equation. Because it can.

  In the second period T2, the discharge of the first integration circuit C1 is continued with a constant voltage waveform slope, and when the voltage at the point A of the first integration circuit C1 reaches the threshold voltage Vth, the control signal φ3 is At this time, the third switch SW3 is turned off. Thereby, the discharge in the plus direction in the first integration circuit C1 is completed.

  When the third switch SW3 is turned OFF, the charging voltage-current conversion circuit 13 and the discharging discharge bias current source 14 are not connected to one end of the first integrating circuit C1, and the first integrating circuit C1 is connected to the first integrating circuit C1. Until the next charging operation is performed, the terminal voltage in the first integration circuit C1 is maintained at the threshold voltage Vth. That is, as shown in FIG. 4, when the audio signal eS is no signal, the terminal voltage of the first integrating circuit C1 is a threshold value for a time t0k until the next charging is started after the discharge in the plus direction is finished. The voltage Vth is maintained. When the audio signal eS is positive and the amplitude is relatively large, the threshold voltage Vth is maintained for a time t1k (<t0k). Further, when the audio signal eS is negative and the amplitude is relatively large, the threshold voltage Vth is maintained for a time t2k (> t0k).

  As described above, in the present embodiment, voltage information based on the audio signal eS is converted into time information, and this time information is made to correspond to the pulse OFF period, thereby appropriately generating the pulse width of the pulse width modulation signal PWMout. be able to. Therefore, for example, even when this pulse width modulation circuit 1 is applied to a multi-channel switching amplifier, the pulse width modulation circuit 1 can perform pulse width modulation synchronized with the first and second switching signals φ1 and φ2. it can. Since the same first and second switching signals φ1 and φ2 can be inputted to each channel, for example, even when the audio signal eS is inputted, the carrier frequency f is slightly different between the channels. This prevents the beat component between the modulated signals (carriers) from being mixed in the audio frequency.

  Next, the negative feedback of the output signal of the switching circuit 2 (when there is a signal from the inverting circuit 19) will be described with reference to FIG. 5A. 5A shows (a) level change of the first switching signal φ1, (b) voltage waveform at one end of the first integrating circuit C1 (see point A in FIG. 2), and (c) to (c) in negative feedback. e) It is a figure which shows the relationship with the output signal eout of the switching circuit 2. FIG.

  At the time of negative feedback, the magnitude of the current charging the first integrating circuit C1 is a magnitude obtained by subtracting the current based on the output signal eout of the switching circuit 2. Accordingly, when the output signal eout of the switching circuit 2 is at a high level, the magnitude of the current for charging the first integrating circuit C1 is small, and when the output signal eout of the switching circuit 2 is at a low level, the first The magnitude of the current charging the integrating circuit C1 increases. As a result, the voltage waveform of the first integrating circuit C1 has a two-step gradient, and the charging voltage of the first integrating circuit C1 when the first switching signal φ1 is inverted to the low level changes with respect to the time of no feedback. To do.

  When the audio signal eS is positive, the output signal eout of the switching circuit 2 is longer in the high level period than in the low level period as shown in FIG. 5A (c). Accordingly, as shown in S1 ′ of FIG. 5A (b), the period in which the voltage gradient of the first integrating circuit C1 is small is longer than the period in which the voltage gradient is large, as compared with the non-feedback state, and the charging is completed. The voltage V1 ′ at the time becomes higher than the voltage V1 at the end of charging without feedback. As a result, when discharging with a constant amount of current, the time t1 ′ until the threshold voltage Vth is reached is shorter than when there is no feedback, and the high-level period of the pulse width modulation signal PWMout is shorter than when there is no feedback. .

  When the audio signal eS is negative, the low level period of the output signal eout of the switching circuit 2 is longer than the high level period as shown in FIG. 5A (d). Therefore, as in S2 ′ of FIG. 5A (b), the period in which the voltage gradient of the first integrating circuit C1 is larger is longer than the period in which the voltage gradient is smaller as compared with the non-feedback state, and charging is completed. The voltage V2 ′ at the time becomes lower than the voltage V2 at the end of charging without feedback. As a result, when discharging with a constant amount of current, the time t2 ′ until the threshold voltage Vth is reached is longer than when there is no feedback, and the high level period of the pulse width modulation signal PWMout is longer than when there is no feedback. .

  When the audio signal eS is 0, as shown in FIG. 5A (e), the output signal eout of the switching circuit 2 is equal in the low level period and the high level period. Therefore, as shown by S0 ′ in FIG. 5A (b), the period during which the voltage gradient of the first integrating circuit C1 is large is equal to the period during which the voltage gradient is small, and the voltage V0 ′ at the end of charging is not fed back. Is equal to the voltage V0 at the end of charging. As a result, when discharging with a constant amount of current, the time t0 ′ until the threshold voltage Vth is reached is the same as in no feedback, and the high level period of the pulse width modulation signal PWMout is the same as in no feedback. .

  FIG. 5B shows a simulation result of the current for charging the first and second integration circuits C1 and C2 by the voltage-current conversion circuit 13. That is, the output signal eout of the switching circuit 2 is attenuated in amplitude, and the current obtained by converting the inverted signal is added to obtain a current waveform in which a pulse component is superimposed with the current Ic + Δi as a reference.

  As described above, when the audio signal eS is positive, the pulse width modulation signal PWMout acts so that the high level period is short and the low level period is long, and when the audio signal eS is negative, the pulse width. Since the high level period of the modulation signal PWMout is long and the low level period is short, the amplitude value of the output signal of the switching amplifier is small. Accordingly, as described above, it can be seen that by providing the amplitude attenuation circuit 18 and the inverting circuit 19 in the pulse width modulation circuit 1, it acts as a negative feedback.

Hereinafter, the operation of the pulse width modulation circuit 1 will be described using the entire time chart.
[basic action]
First, basic operations will be described with reference to FIGS. 6 to 8 on the assumption that there is no PWM signal −enfb from the inverting circuit 19. 6 to 8 are timing charts of signals in the pulse width modulation circuit 1. 6 shows a case where the audio signal eS is no signal (Gm · eS = 0), FIG. 7 shows a case where the audio signal eS is a positive value, and FIG. 8 shows that the audio signal eS is The negative case is shown.

  In the first period T1 in FIG. 6, since the first switching signal φ1 from the dead time generation circuit 12 is at a high level (see FIG. 6B), the first switch SW1 is turned on. Therefore, the first integration circuit C1 is charged in the minus direction by the current (Ic + Δi) from the voltage-current conversion circuit 13 (see FIG. 6 (h)).

  When the first switching signal φ1 is inverted from the high level to the low level, the process proceeds to the second period T2, and the falling edge detection circuit 42 detects the falling edge when the first switching signal φ1 is inverted, and the first RS The first set signal set1 is output to the flip-flop circuit 43 (see FIG. 6D).

  In the first RS flip-flop circuit 43, when a signal that instantaneously changes to low level is input as the first set signal set1, the second NAND circuit NA2 inverts its output from low level to high level. Since the output of the second NAND circuit NA2 is input to the third switch SW3 as the control signal φ3 (see FIG. 6F), the third switch SW3 is turned on. As a result, the first integrating circuit C1 is discharged in the plus direction with a constant discharge amount by the discharging bias current source 14 (see FIG. 6H).

  In the first RS flip-flop circuit 43, when a signal that instantaneously changes to the low level is input as the first set signal set1, the first NAND circuit NA1 inverts the output from the high level to the low level. The output of the first NAND circuit NA1 is input to the fifth NAND circuit NA5 as the output signal rsout1 (see FIG. 6L).

  In the first comparison circuit 23, the terminal voltage of the first integration circuit C1 is discharged in the positive direction until it reaches the reference voltage Vref input to the positive (+) side input terminal, and when the terminal voltage reaches the reference voltage Vref, The 1 comparison circuit 23 changes its output from the high level to the low level (see FIG. 6J). The output of the first comparison circuit 23 is input to the first RS flip-flop circuit 43 as the first reset signal res1.

  In the first RS flip-flop circuit 43, when the first reset signal res1 changes from high level to low level, the output signal rsout1 changes from low level to high level and is input to the fifth NAND circuit NA5 (FIG. 6 (l )reference). In the fifth NAND circuit NA5, since the other input terminal (rsout2) is at the high level, the output signal rsout1 is inverted and output to the switching circuit 2 as the pulse width modulation signal PWMout (see FIG. 6 (n)). Further, when the first reset signal res1 changes from the high level to the low level, the control signal φ3 also changes from the high level to the low level. As a result, the third switch SW3 is turned off, and the discharge of the first integrating circuit C1 is stopped. The first integration circuit C1 holds a voltage equivalent to Vref until the start of the third period T3.

  On the other hand, in the second period T2, since the second switching signal φ2 from the dead time generation circuit 12 is at a high level (see FIG. 6C), the second switch SW2 is turned on. Therefore, the second integration circuit C2 is charged in the minus direction by the current (Ic + Δi) from the voltage-current conversion circuit 13 (see FIG. 6 (i)).

  When the second switching signal φ2 is inverted from the high level to the low level, the process proceeds to the third period T3, and the falling edge detection circuit 42 detects the falling edge when the second switching signal φ2 is inverted, and the second RS The second set signal set2 is output to the flip-flop circuit 44 (see FIG. 6E).

  In the second RS flip-flop circuit 44, when a signal that instantaneously changes to the low level is input as the second set signal set2, the fourth NAND circuit NA4 inverts the output from the low level to the high level. Since the output of the fourth NAND circuit NA4 is input to the fourth switch SW4 as the control signal φ4 (see FIG. 6G), the fourth switch SW4 is turned on. As a result, the second integrating circuit C2 is discharged in the plus direction with a constant discharge amount by the discharging bias current source 14 (see FIG. 6 (i)).

  In the second RS flip-flop circuit 44, when a signal that instantaneously changes to the low level is input as the second set signal set2, the third NAND circuit NA3 inverts the output from the high level to the low level. The output of the third NAND circuit NA3 is input to the fifth NAND circuit NA5 as the output signal rsout2 (see FIG. 6 (m)).

  In the second comparison circuit 24, the terminal voltage of the second integration circuit C2 is discharged in the positive direction until reaching the reference voltage Vref input to the positive (+) side input terminal, and when the terminal voltage reaches the reference voltage Vref, the output is performed. Is changed from high level to low level. The output of the second comparison circuit 24 is input to the second RS flip-flop circuit 44 as the second reset signal res2 (see FIG. 6 (k)).

  In the second RS flip-flop circuit 44, when the second reset signal res2 changes from the high level to the low level, the output signal rsout2 changes from the low level to the high level and is input to the fifth NAND circuit NA5 (FIG. 6 (m )reference). In the fifth NAND circuit NA5, since the other input terminal (rsout1) is at the high level, the output signal rsout2 is inverted and output to the switching circuit 2 as the pulse width modulation signal PWMout (see FIG. 6 (n)). When the second reset signal res2 changes from the high level to the low level, the control signal φ4 also changes from the high level to the low level. As a result, the fourth switch SW4 is turned off, and the discharge of the second integration circuit C2 is stopped. The second integration circuit C2 holds a voltage equivalent to Vref until the start of the fourth period T4.

  As shown in FIG. 7, when the audio signal eS is positive, the magnitude of the current (Ic + Δi) is large, and the slope of the voltage waveform at one end of the first or second integrating circuit C1, C2 is also the audio signal eS. Larger than in the case of no signal. Therefore, the terminal voltage of the first or second integration circuit C1, C2 at the time when the level of the first or second switching signal φ1, φ2 is inverted from the high level to the low level is the same as when the audio signal eS is no signal. In comparison, when these are discharged in the plus direction, the time t until the reference voltage Vref is reached after the discharge is started is longer than when the audio signal eS is no signal. Therefore, as shown in FIG. 7 (n), the pulse width modulation signal PWMout having a long high level time is output compared to the case where the audio signal eS shown in FIG. 6 is no signal. Thus, the pulse width modulation signal PWMout corresponding to the amplitude of the audio signal eS is output.

  As shown in FIG. 8, when the audio signal eS is negative, the current (Ic + Δi) is small, and the slope of the voltage waveform at one end of the first or second integrating circuit C1, C2 is small. Become. Therefore, the terminal voltage of the first or second integration circuit C1, C2 at the time when the level of the first or second switching signal φ1, φ2 is inverted from the high level to the low level is the same as when the audio signal eS is no signal. In comparison, when these are discharged in the positive direction, the time t until the reference voltage Vref is reached after the discharge is started is shorter than in the case where the audio signal eS is no signal. Therefore, as shown in FIG. 8 (n), the pulse width modulation signal PWMout having a short high level time is output compared to the case where the audio signal eS shown in FIG. 6 is no signal.

[Negative feedback operation]
The operation when the output signal eout of the switching circuit 2 is negatively fed back to the voltage-current conversion circuit 13 by the amplitude attenuation circuit 18 and the inverting circuit 19 will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagram showing a case where the audio signal eS is positive, and FIG. 10 is a diagram showing a case where the audio signal eS is negative.

  With reference to FIG. 9, the case where the audio signal eS similar to FIG. 7 is positive will be described. During the period T1 during which the first integration circuit C1 is charged and the pulse width modulation signal PWMout (that is, the output signal eout of the switching circuit 2) is at the high level, the output signal eout of the switching circuit 2 is at the high level. (For example, + 50V) is attenuated by the amplitude attenuating circuit 18, inverted by the inverting circuit 19 (for example, becomes a voltage of -5V), converted into a current by the voltage / current converting circuit 13, and charged to charge the first integrating circuit C1. Therefore, the magnitude of the charging current is smaller than that when there is no feedback. As a result, as shown in FIG. 9 (h), the slope of the voltage waveform at one end of the first integrating circuit C1 becomes smaller than when there is no feedback.

  During the period T1 during which the first integration circuit C1 is charged and the pulse width modulation signal PWMout (that is, the output signal eout of the switching circuit 2) is at the low level, the output signal eout of the switching circuit 2 is at the low level. (For example, −50V) is attenuated in amplitude by the amplitude attenuating circuit 18, inverted by the inverting circuit 19 (for example, becomes a voltage of + 5V), converted into a current by the voltage / current converting circuit 13, and charging the first integrating circuit C1. Therefore, the magnitude of the current to be charged is larger than that when there is no feedback. As a result, as shown in FIG. 9 (h), the slope of the voltage waveform at one end of the first integrating circuit C1 becomes larger than when there is no feedback.

  When the audio signal eS is positive, as shown in FIG. 9 (n), the high level period of the output signal eout of the switching circuit 2 is longer than the low level period, so the level of the first switching signal φ1 The terminal voltage of the first integration circuit C1 at the time when is inverted from the high level to the low level is higher than that in the case of no feedback, and when these are discharged in the positive direction, compared to the case of no feedback, The time t until the reference voltage Vref is reached after the discharge is started is shortened. Note that the periods T2a and T2b in which the second integration circuit C2 is charged are the same as the periods T1a and T1b in which the first integration circuit C1 is charged. Therefore, as shown in FIG. 9 (n), compared to the non-feedback case shown in FIG. 7, the pulse width modulation signal PWMout having a short high level period and a long low level period is output.

  Next, the case where the audio signal eS similar to that in FIG. 8 is negative will be described with reference to FIG. During the period T1 during which the first integration circuit C1 is charged and the pulse width modulation signal PWMout (that is, the output signal eout of the switching circuit 2) is at the high level, the output signal eout of the switching circuit 2 is at the high level. (For example, + 50V) is attenuated by the amplitude attenuating circuit 18, inverted by the inverting circuit 19 (for example, becomes a voltage of -5V), converted into a current by the voltage / current converting circuit 13, and charged to charge the first integrating circuit C1. Therefore, the magnitude of the current to be charged is smaller than that when there is no feedback. As a result, as shown in FIG. 10 (h), the slope of the voltage waveform at one end of the first integrating circuit C1 becomes smaller than when there is no feedback.

  During the period T1 during which the first integration circuit C1 is charged and the pulse width modulation signal PWMout is at the low level (that is, the output signal eout of the switching circuit 2), the output signal eout of the switching circuit 2 is at the low level. (For example, −50V) is attenuated in amplitude by the amplitude attenuating circuit 18, inverted by the inverting circuit 19 (for example, becomes a voltage of + 5V), converted into a current by the voltage / current converting circuit 13, and charging the first integrating circuit C1. Therefore, the magnitude of the current to be charged is larger than that when there is no feedback. As a result, as shown in FIG. 10 (h), the slope of the voltage waveform at one end of the first integrating circuit C1 becomes larger than when there is no feedback.

  When the audio signal eS is negative, the high level period of the pulse width modulation signal PWMout (that is, the output signal eout of the switching circuit 2) is shorter than the low level period as shown in FIG. When the level of the first switching signal φ1 is inverted from the high level to the low level, the terminal voltage of the first integrating circuit C1 is lower than that in the case of no feedback, and when these are discharged in the plus direction, Compared with the non-feedback case, the time t until the reference voltage Vref is reached after the discharge is started becomes longer. Note that the periods T2a and T2b in which the second integration circuit C2 is charged are the same as the periods T1a and T1b in which the first integration circuit C1 is charged. Therefore, as shown in FIG. 10 (n), compared to the non-feedback case shown in FIG. 8, the pulse width modulation signal PWMout having a long high level period and a short low level period is output.

  As described above, when the audio signal eS is positive, the high level period of the pulse width modulation signal PWMout is short and the low level period is long. When the audio signal eS is negative, the pulse width modulation signal PWMout is Since the high-level period is long and the low-level period is short, the amplitude value of the output signal of the switching amplifier is small, so that it functions as negative feedback and noise can be removed.

  FIG. 11 is a circuit diagram showing a pulse width modulation circuit 51 according to another preferred embodiment of the present invention. The pulse width modulation circuit 51 is different from the pulse width modulation circuit 1 of FIG. 2 in that the configuration of the signal output circuit 16 is different and the falling edge detection circuit 42 is not provided.

  The signal output circuit 16 includes first to third NOR circuits N1, N2, and N3. The first NOR circuit N1 has one input terminal connected to the output terminal of the first switching signal φ1 of the dead time generation circuit 12, and the other input terminal connected to one end of the first integration circuit C1. On the other hand, one input terminal of the second NOR circuit N2 is connected to the output terminal of the second switching signal φ2 of the dead time generation circuit 12, and the other input terminal is connected to one end of the second integration circuit C2.

  The output terminal of the first NOR circuit N1 is connected to one input terminal of the third NOR circuit N3 and to the third switch SW3. The output terminal of the second NOR circuit N2 is connected to the other input terminal of the third NOR circuit N3 and to the fourth switch SW4. The output terminal of the third NOR circuit N3 is connected to the subsequent switching circuit 2 as the pulse width modulation signal PWMout.

  The first NOR circuit N1 calculates the negative OR of the first switching signal φ1 and the terminal voltage of the first integrating circuit C1, that is, the first switching signal φ1 is at a low level and the first integrating circuit When the terminal voltage of C1 is less than the predetermined voltage Vth, a high level is output. The second NOR circuit N2 calculates the negative logical sum of the second switching signal φ2 and the terminal voltage of the second integrating circuit C2, that is, the second switching signal φ2 is at a low level and the second integrating circuit When the terminal voltage of C2 is less than the predetermined voltage Vth, a high level is output.

  The third NOR circuit N3 calculates a negative logical sum of the outputs of the first and second NOR circuits N1 and N2, and sets the outputs of the first and second NOR circuits N1 and N2 as one pulse width modulation signal PWMout. 2 is output. Since other configurations and operations are the same as those in the previous embodiment, the description is incorporated.

  FIG. 12 is a circuit diagram showing a pulse width modulation circuit 61 according to another preferred embodiment of the present invention. The pulse width modulation circuit 61 does not include the first and second comparison circuits 23 and 24, and the pulse of FIG. 2 is different in that the charging and discharging directions of the first and second integration circuits C1 and C2 are reversed. Unlike the width modulation circuit 1, the other is the same. That is, the first integration circuit C1 is charged in the positive direction in the first period T1, discharged in the negative direction in the second period T2, and then maintained at the reference voltage Vref. Further, the second integration circuit C2 performs the same charging / discharging operation as the first integration circuit C1 with a half cycle shift. The comparison with the threshold voltage by the first and second comparison circuits is performed by the first and third NAND circuits NA1 and NA3.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment. Also, in the voltage waveforms shown in FIGS. 4 to 10, the audio signal eS may be reversed in sign. For example, in the voltage waveform of FIG. 4, the waveform of the sign S1 may be a waveform when the audio signal eS is negative, and the waveform of the sign S2 may be a waveform when the audio signal eS is positive. Further, in the pulse width modulation circuits of FIGS. 2 and 11, the directions of the charging and discharging currents may be reversed as shown in FIG.

  The present invention can be suitably applied to a pulse width modulation circuit of an audio switching amplifier.

It is a block diagram which shows the structure of the switching amplifier by preferable embodiment of this invention. It is a block diagram which shows the structure of the pulse width modulation circuit 1 by preferable embodiment of this invention. It is a figure which shows the reference clock signal MCLK, 1st switching signal (phi) 1, and 2nd switching signal (phi) 2. It is a figure explaining the voltage change of the 1st integration circuit C1 at the time of no feedback. It is a figure explaining the voltage change of the 1st integration circuit C1 at the time of negative feedback. It is a figure which shows the waveform of the charging current at the time of performing negative feedback. 6 is a time chart showing the operation of the pulse width modulation circuit 1 when there is no signal when there is no feedback. 6 is a time chart showing the operation of the pulse width modulation circuit 1 when the audio signal is positive when there is no feedback. It is a time chart which shows the operation | movement of the pulse width modulation circuit 1 when an audio signal is negative at the time of no feedback. It is a time chart which shows operation | movement of the pulse width modulation circuit 1 at the time of a negative feedback, when an audio signal is positive. It is a time chart which shows operation | movement of the pulse width modulation circuit 1 at the time of a negative feedback, when an audio signal is negative. It is a circuit diagram which shows the structure of the pulse width modulation circuit 51 by another preferable embodiment of this invention. It is a circuit diagram which shows the structure of the pulse width modulation circuit 61 by another preferable embodiment of this invention. FIG. 6 is a circuit diagram showing a configuration of a conventional pulse width modulation circuit 41.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pulse width modulation circuit 2 Switching circuit 3 Low pass filter circuit 4 1st power supply 5 2nd power supply 11 Clock generation circuit 12 Dead time generation circuit 13 Voltage current conversion circuit 14 Bias current source 15 Current bypass circuit 16 Signal output circuit 18 Amplitude Attenuation circuit 19 Inversion circuit 23 First comparison circuit 24 Second comparison circuit 42 Falling edge detection circuit 43 First RS flip-flop circuit 44 Second RS flip-flop circuit AU Audio generation source C1 First integration circuit C2 Second integration circuit eS Audio signal Ic charge bias current Id discharge bias current SW1 first switch SW2 second switch SW3 third switch SW4 fourth switch T1 first period T2 second period T3 third period T4 third period Vref reference voltage Vth threshold voltage φ1 first switching Signal φ2 Second switching signal 3 control signal φ4 control signal

Claims (2)

A pulse width modulation circuit;
A switching circuit for switching a predetermined power supply voltage supplied from a voltage source based on a modulation signal output from the pulse width modulation circuit;
The pulse width modulation circuit comprises:
Based on a current based on an input signal and a signal from an inverting circuit described later, a voltage in the first integration circuit is changed in a first period which is a half cycle of a predetermined clock signal, and the first period is determined based on a constant bias current. In the second period following the first period shifted by a half cycle, the voltage in the first integration circuit is changed in the opposite direction to the increase / decrease direction in the first period, and the input signal and the signal from the inversion circuit described later are In the third period following the second period shifted by a half cycle from the second period based on the bias current, the voltage in the second integration circuit different from the first integration circuit is changed based on the current based on A voltage control circuit for changing the voltage in the second integration circuit in the direction opposite to the increase / decrease direction in the second period;
A first detection circuit for detecting a time from when the second period starts until the voltage in the first integration circuit reaches a predetermined reference voltage;
A second detection circuit that detects a time from when the third period starts until the voltage in the second integration circuit reaches a predetermined reference voltage;
A pulse signal generation circuit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection circuit and the second detection circuit every half cycle of the clock signal;
An amplitude attenuation circuit for attenuating the amplitude of the pulse signal from the switching circuit;
A switching amplifier comprising: an inverting circuit that inverts a pulse signal whose amplitude is attenuated by the amplitude attenuating circuit. The voltage control circuit includes:
A voltage-current conversion circuit that converts a voltage based on the input signal into a current, converts a voltage based on the signal from the inverting circuit into a current, and adds these currents;
The first integration circuit is charged in the first period based on the current converted by the voltage-current conversion circuit, and the second integration is performed in the second period based on the current converted by the voltage-current conversion circuit. The switching amplifier according to claim 1, wherein the circuit is charged.