JP4582351B2 - Pulse width modulation circuit - Google Patents

Description

  The present invention relates to a pulse width modulation circuit applied to, for example, a switching amplifier.

  FIG. 14 is a block diagram showing a pulse width modulation circuit disclosed by the present applicant in the following prior application 1. The pulse width modulation circuit 901 charges the first integration circuit C1 in the first period T1 of the clock signal MCLK based on the current Ic + Δi based on the audio signal eS, and in the second period T2 based on the constant bias current Id. The voltage of the first integration circuit C1 is discharged, the second integration circuit C2 is charged, and the voltage of the second integration circuit C2 is discharged in the third period T3 based on the bias current Id.

  Then, the time from when the second period T2 is started until the voltage of the first integrating circuit C1 reaches the reference voltage Vref is detected, and after the third period T3 is started, the voltage of the second integrating circuit C2 is The time until the reference voltage Vref is reached is detected. The voltage of the first integrating circuit C1 is maintained until the third period T3 starts after the voltage of the first integrating circuit C1 reaches the reference voltage Vref, and the voltage of the second integrating circuit C2 reaches the reference voltage Vref. Then, the voltage of the second integrating circuit C2 is maintained until the fourth period T4 is started. Based on the time until the voltage of the first and second integration circuits C1 and C2 reaches the reference voltage Vref, a pulse signal having a pulse width of the time is generated.

  Here, the pulse width modulation circuit 901 is applied to an audio switching amplifier, but the switching amplifier amplifies the power of the pulse waveform, and in principle, an unnecessary radiation problem is likely to occur. An example is radio reception interference. One possible countermeasure is to switch the carrier frequency. In the pulse width modulation circuit 901 described above, the modulation carrier frequency is twice the frequency of the input clock signal, so that the problem of unnecessary radiation can be solved by switching the frequency of the input clock signal.

  However, when the frequency of the clock signal is changed, as shown in FIG. 15, the maximum charging voltage (voltage value at the end of charging) of the first and second integrating circuits C1 and C2 that perform charging and discharging changes. Since the maximum value of the chargeable voltage is the power supply voltage VCC, the maximum charge voltage Va when the audio signal eS is no signal (that is, no modulation) is half the chargeable voltage (that is, (VCC + Vref)). If it is greater than / 2), the charging voltage is limited and clipping occurs, resulting in a problem that a normal PWM waveform is not output.

  Hereinafter, this problem will be described in detail. FIG. 15 is a diagram illustrating a charging voltage waveform of the first integration circuit C1 when the frequency of the clock signal MCLK is changed. FIG. 15A illustrates a case where the clock signal MCLK is a first frequency that is a normal frequency. (B) shows a case where the clock signal MCLK is a second frequency which is lower than the first frequency, and (c) shows a case where the clock signal MCLK is a third frequency which is higher than the first frequency. Show. In FIG. 15, a waveform (1) shows a case where the audio signal eS is no signal, and a waveform (2) shows a case where the amplitude value of the audio signal eS is a positive and maximum value. The signal φ1 is synchronized with the clock signal. When the signal φ1 is high level, the switch SW1 is turned on to charge the first integrating circuit C1, and when it is low level, the switch SW1 is turned off to turn the first integrating circuit C1. Is a signal that does not charge.

  As shown in FIG. 15A, when the frequency of the clock signal MCLK is the first frequency (reference frequency), the maximum charging voltage Va of the first integration circuit C1 when the audio signal eS is no signal is the first As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply. The voltage VCC is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 15B, when the frequency of the clock signal MCLK is the second frequency, the charging time for the first integrating circuit C1 becomes long, so that the first case where the audio signal eS is no signal is used. The maximum charging voltage Va of the 1 integrating circuit C1 is a voltage larger than ½ of the chargeable voltage of the first integrating circuit C1, and as a result, the amplitude value of the audio signal eS is positive and maximum. In addition, the maximum charging voltage of the first integrating circuit C1 exceeds the power supply voltage VCC (see broken line). Therefore, in this case, the charging voltage of the first integration circuit C1 is limited, and it becomes impossible to output a normal PWM waveform by clipping.

  Next, as shown in FIG. 15C, when the frequency of the clock signal MCLK is the third frequency, the maximum charging voltage Va of the first integration circuit C1 when the audio signal eS is no signal is the first integration voltage. As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply voltage. VCC is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

[Patent Application 1] Japanese Patent Application No. 2007-111251

  The present invention has been made to solve the above-described problems, and an object of the present invention is to output a normal PWM waveform even when the frequency of the clock signal is changed in the pulse width modulation circuit. It is to provide a pulse width modulation circuit that can.

  The pulse width modulation circuit according to a preferred embodiment of the present invention changes the voltage in the first integration circuit in a first period which is a half cycle of a predetermined clock signal based on a current based on an input signal, and based on a constant bias current. In the second period following the first period shifted by a half cycle from the first period, the voltage in the first integration circuit is changed in the opposite direction to the increase / decrease direction in the first period, and the current based on the input signal Based on the second integration circuit, the voltage in the second integration circuit different from the first integration circuit is changed, and the second period in the third period following the second period shifted from the second period by a half cycle based on the bias current. A voltage control circuit that changes the voltage in the integration circuit in the opposite direction to the increase / decrease direction in the second period; and the first integration circuit after the second period is started. A first detection circuit that detects a time until the voltage reaches a predetermined reference voltage, and a time from when the third period starts until the voltage in the second integration circuit reaches the predetermined reference voltage. A second detection circuit for detecting, and a first voltage for maintaining the voltage in the first integration circuit at the reference voltage until the third period starts after the voltage in the first integration circuit reaches the reference voltage A sustain circuit and a second integration circuit in the second integration circuit until a fourth period starting from the third period shifted from the third period after the voltage in the second integration circuit reaches the reference voltage is started. A second voltage maintaining circuit that maintains a voltage at the reference voltage, and a pulse of the time based on a time that is alternately output from the first detection circuit and the second detection circuit every half cycle of the clock signal. A pulse signal generation circuit that generates a pulse signal having frequency control means for switching a frequency of the clock signal to at least a first frequency and a second frequency that is lower than the first frequency; When the frequency is the second frequency, the chargeable voltage of the first integration circuit and the second integration circuit is switched to a value larger than the chargeable voltage when the frequency of the clock signal is the first frequency. Possible voltage switching means.

  When the frequency of the clock signal is low, the charging time for the first integrating circuit and the second integrating circuit becomes long, but by increasing the chargeable voltage of the first integrating circuit and the second integrating circuit, the input signal It is possible to prevent the voltage waveform from being clipped because the maximum charging voltage of the first integrating circuit and the second integrating circuit exceeds the chargeable voltage even when the amplitude of the first integrating circuit is maximum. Therefore, a normal PWM waveform can be output even when the frequency of the clock signal is low.

  In a preferred embodiment, the chargeable voltage is a difference between a power supply voltage and the reference voltage in the first detection circuit and the second detection circuit, and the chargeable voltage switching unit is configured to change the frequency of the clock signal. A reference voltage switching circuit that switches the reference voltage to a value smaller than the reference voltage when the frequency of the clock signal is the first frequency.

  When the frequency of the clock signal is low, the chargeable voltage can be increased by switching the reference voltage to a small value.

  In a preferred embodiment, the chargeable voltage is a difference between a power supply voltage and the reference voltage in the first detection circuit and the second detection circuit, and the chargeable voltage switching unit is configured to change the frequency of the clock signal. A power supply voltage switching circuit that switches the power supply voltage to a value greater than the power supply voltage when the frequency of the clock signal is the first frequency.

  When the frequency of the clock signal is low, the chargeable voltage can be increased by switching the power supply voltage to a large value.

  According to another preferred embodiment of the present invention, a pulse width modulation circuit changes a voltage in a first integration circuit in a first period which is a half cycle of a predetermined clock signal based on a current based on an input signal, and a constant bias current. Based on the first period, the voltage in the first integration circuit is changed in the direction opposite to the increase / decrease direction in the first period in the second period following the first period shifted by a half cycle from the first period, and the input signal The voltage in the second integration circuit different from the first integration circuit is changed based on the current based on, and in the third period following the second period shifted from the second period by a half cycle based on the bias current. A voltage control circuit for changing the voltage in the second integration circuit in the direction opposite to the increase / decrease direction in the second period, and the first integration time after the second period is started. A first detection circuit that detects a time until the voltage at the second reference circuit reaches a predetermined reference voltage; and a time from when the third period starts until the voltage at the second integration circuit reaches the predetermined reference voltage. A second detection circuit for detecting, and a first voltage for maintaining the voltage in the first integration circuit at the reference voltage until the third period starts after the voltage in the first integration circuit reaches the reference voltage A sustain circuit and a second integration circuit in the second integration circuit until a fourth period starting from the third period shifted from the third period after the voltage in the second integration circuit reaches the reference voltage is started. A second voltage maintaining circuit that maintains a voltage at the reference voltage, and a time that is repeatedly output from the first detecting circuit and the second detecting circuit alternately every half cycle of the clock signal. A pulse signal generation circuit for generating a pulse signal having a pulse width; frequency control means for switching a frequency of the clock signal to at least a first frequency and a second frequency that is lower than the first frequency; and the clock When the frequency of the signal is the second frequency, the voltage change amount when the first integration circuit and the second integration circuit are charged and discharged, and the voltage change when the frequency of the clock signal is the first frequency Voltage change amount switching means for reducing the voltage change amount.

  When the frequency of the clock signal is low, the charging time for the first integrating circuit and the second integrating circuit becomes long, but the amount of voltage change during charging and discharging of the first integrating circuit and the second integrating circuit (that is, By reducing the voltage change amount per unit time and the slope of the voltage waveform, the maximum charging voltage of the first integrating circuit and the second integrating circuit can be charged even when the amplitude of the input signal is maximum. It is possible to prevent the voltage waveform from being clipped. Therefore, a normal PWM waveform can be output even when the frequency of the clock signal is low.

  In a preferred embodiment, the voltage change amount switching means is configured such that when the frequency of the clock signal is the second frequency, the capacitance of the first integration circuit and the second integration circuit is set to be the frequency of the clock signal. It has a capacity switching circuit for switching to a value larger than the capacity in the case of one frequency.

  When the frequency of the clock signal is low, the time constant for determining the charge / discharge time is increased by increasing the capacities of the first integration circuit and the second integration circuit. Therefore, the first integration circuit and the second integration circuit The amount of voltage change during circuit charging and discharging can be reduced.

  In a preferred embodiment, when the frequency of the clock signal is the second frequency, the voltage change amount switching means indicates the current based on the input signal and the bias current, and the frequency of the clock signal is the first frequency. A current switching circuit for switching to a value smaller than the current based on the input signal and the bias current in a certain case is provided.

  When the frequency of the clock signal is low, by reducing the current (charging current) and the bias current (discharging current) based on the input signal, the first integrating circuit and the second integrating circuit are charged and discharged. The amount of voltage change at the time can be reduced.

  According to still another preferred embodiment of the present invention, a pulse width modulation circuit changes a voltage in a first integration circuit in a first period which is a half cycle of a predetermined clock signal based on a current based on an input signal, and has a constant bias. Based on the current, the voltage in the first integration circuit is changed in the opposite direction to the increase / decrease direction in the first period in a second period following the first period shifted by a half cycle from the first period, and the input signal In the third period following the second period shifted by a half cycle from the second period based on the bias current, the voltage in the second integration circuit different from the first integration circuit is changed based on the current based on A voltage control circuit that changes a voltage in the second integration circuit in a direction opposite to the increase / decrease direction in the second period, and the first period after the second period is started. A first detection circuit for detecting a time until the voltage in the distribution circuit reaches a predetermined reference voltage; and a time from when the third period starts until the voltage in the second integration circuit reaches the predetermined reference voltage A second detection circuit for detecting time, and a second detection circuit for maintaining the voltage in the first integration circuit at the reference voltage until the third period starts after the voltage in the first integration circuit reaches the reference voltage. 1 voltage maintaining circuit and the second integration until the fourth period starting from the third period shifted from the third period after the voltage in the second integration circuit reaches the reference voltage is started. A second voltage maintaining circuit that maintains the voltage in the circuit at the reference voltage, and a time that is alternately and repeatedly output from the first detection circuit and the second detection circuit every half cycle of the clock signal. A pulse signal generation circuit for generating a pulse signal having a pulse width of: a frequency control means for switching a frequency of the clock signal to at least a first frequency and a second frequency that is lower than the first frequency; When the frequency of the clock signal is the second frequency, the maximum charging voltage of the first integration circuit and the second integration circuit when the input signal is no signal is expressed as the first integration circuit and the second integration circuit. Setting means for setting the voltage to ½ or less of the chargeable voltage.

  When the frequency of the clock signal is low, the charging time for the first integrating circuit and the second integrating circuit becomes long, but the maximum charging of the first integrating circuit and the second integrating circuit when the input signal is no signal is performed. By setting the voltage to ½ or less of the chargeable voltage of the first integration circuit and the second integration circuit, the maximum of the first integration circuit and the second integration circuit can be obtained even when the amplitude of the input signal is maximum. It can be prevented that the charging voltage exceeds the chargeable voltage and the voltage waveform is clipped. Therefore, a normal PWM waveform can be output even when the frequency of the clock signal is low.

  According to the present invention, even when the amplitude of the input signal is maximum, it is possible to prevent the maximum charging voltage of the first integration circuit and the second integration circuit from exceeding the chargeable voltage and clipping the voltage waveform. Therefore, a normal PWM waveform can be output even when the frequency of the clock signal is low.

Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings. However, the present invention is not limited to these embodiments.
[First Embodiment]
FIG. 1 is a configuration diagram showing a switching amplifier to which a pulse width modulation (PWM) circuit according to a first embodiment of the present invention is applied. FIG. 2 is a block circuit diagram showing an embodiment of the pulse width modulation circuit shown in FIG. This switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, a first power supply 4 that supplies positive and negative power supply voltages + EB and -EB, and a second power supply. And a power source 5. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

  The pulse width modulation circuit 1 generates and outputs a modulation signal PWMout by performing pulse width modulation on the audio signal eS as an input signal output from the audio signal generation source AU. The modulation signal PWMout output from the pulse width modulation circuit 1 is input to the switching circuit 2.

  In the switching circuit 2, positive and negative power supply voltages + EB and -EB are supplied from the first power supply 4 and the second power supply 5, and the power supply voltages + EB and -EB are alternately switched based on the modulated modulation signal PWMout. That is, the switching circuit 2 includes a switching element SW-A that is turned on and off based on the modulation signal PWMout, an inverter 2a that inverts the phase of the modulation signal PWMout output from the pulse width modulation circuit 1, and the inverter 2a. Based on the modulation signal PWMout ′ obtained by inverting the modulation signal PWMout, the switch element SW-B is turned on and off, and the diodes DA and D− connected to both ends of the switch elements SW-A and SW-B, respectively. B.

  Both switch elements SW-A and SW-B are alternately turned on and off by the modulation signal PWMout and the inverted modulation signal PWMout ′, and the positive and negative power supply voltages + EB and −EB are switched to the low-pass filter circuit 3. And supply to the load RL.

  The low-pass filter circuit 3 is configured by an LC circuit including a coil L0 and a capacitor C0. The low-pass filter circuit 3 is a circuit that removes a high-frequency component of the output signal output from the switching circuit 2 and supplies it to the load RL, and has a cutoff frequency of 60 kHz, for example. In the low-pass filter circuit 3, the high-frequency components of the switched positive and negative power supply voltages + EB and -EB are removed, and the output is supplied from the load RL as a sound by being supplied to the load RL.

  As shown in FIG. 2, the pulse width modulation circuit 1 includes a clock frequency control unit 9, a clock generation circuit 10, a dead time generation circuit 11, a falling edge detection circuit 12, a voltage / current conversion circuit 13, 1st to 4th switches SW1 to SW4, 1st and 2nd integrating circuits C1 and C2, a discharging bias current source 14, a current bypass circuit 15, a signal output circuit 16, and reference voltage switching circuits 18 and 19 It is constituted by.

  The clock generation circuit 10 is a circuit that generates a reference clock signal MCLK. The reference clock signal MCLK is a clock signal having a duty ratio of approximately 50%, and serves as a reference signal for the first and second switching signals φ1 and φ2 for switching the first and second switches SW1 and SW2. The clock generation circuit 10 outputs the reference clock signal MCLK to the dead time generation circuit 11. The clock generation circuit 10 may be provided outside the pulse width modulation circuit 1 and configured to supply the reference clock signal MCLK to the pulse width modulation circuit 1 as an external clock signal.

  Based on the reference clock signal MCLK from the clock generation circuit 10, the dead time generation circuit 11 generates a first switching signal φ1 and a second switching signal φ2 having an opposite phase relationship to the first switching signal φ1. This is a circuit to be generated. More specifically, the dead time generating circuit 11 performs the time inversion of the first and second switching signals φ1 and φ2 for a predetermined time so that the output levels of the first and second switching signals φ1 and φ2 do not coincide at the same time. Each circuit is a delay circuit.

  That is, as shown in FIGS. 3A and 3B, the first switching signal φ1 is delayed from the low level to the high level by a predetermined period Δt when the reference clock signal MCLK is inverted from the low level to the high level. Invert. The first switching signal φ1 is inverted from the high level to the low level simultaneously when the reference clock signal MCLK is inverted from the high level to the low level. On the other hand, as shown in FIGS. 3A and 3C, the second switching signal φ2 is delayed from the low level to the high level by a predetermined period Δt when the reference clock signal MCLK is inverted from the high level to the low level. Invert. Note that the second switching signal φ2 is simultaneously inverted from the high level to the low level when the reference clock signal MCLK is inverted from the low level to the high level.

  In this way, when the first and second switches SW1 and SW2 are turned on by the first and second switching signals φ1 and φ2, respectively, the first and second integration circuits C1 are prevented from being turned on at the same time. , C2 can perform charging operations simultaneously, thereby preventing an error from occurring in the output of the pulse width modulation signal PWMout. The first and second switching signals φ1 and φ2 are output to the first and second switches SW1 and SW2, respectively.

  In the following description, for the sake of convenience, as shown in FIG. 3A, the period in which the reference clock signal MCLK first becomes high level is the first period T1, and the subsequent low level period is the second period T2. The subsequent high level period is referred to as a third period T3, and the subsequent low level period is referred to as a fourth period T4.

  Returning to FIG. 2, the falling edge detection circuit 12 is a circuit that outputs first and second set signals set <b> 1 and set <b> 2 that are output to first and second RS flip-flop circuits 43 and 44 described later. That is, the falling edge detection circuit 12 detects the falling edge when the first and second switching signals φ1 and φ2 from the dead time generation circuit 11 are inverted from the high level to the low level, and the detected timing is detected. This circuit outputs the first and second set signals set 1 and set 2 to the first and second RS flip-flop circuits 43 and 44.

  The voltage-current conversion circuit 13 is a circuit that performs voltage-current conversion on the audio signal eS supplied to the pulse width modulation circuit 1 from the audio signal generation source AU (see FIG. 1). The voltage-current conversion circuit 13 has a charging bias current source (not shown), and is a circuit that charges the first and second integrating circuits C1 and C2 with respect to a reference voltage (for example, ground potential). .

  Here, when the conversion conductance in the voltage-current conversion circuit 13 is Gm, the current Δi converted from the audio signal eS by the voltage-current conversion circuit 13 can be expressed by Δi = Gm · eS. If the charging bias current in the charging bias current source is Ic, the current flowing through the first and second integrating circuits C1 and C2 can be expressed as Ic + Gm · eS = Ic + Δi.

  The discharge bias current source 14 is a circuit that converts the supplied negative power supply voltage −V into a discharge bias current Id. As will be described later, the discharge bias current source 14 is connected to the first and second integration circuits C1 and C2 via the third and fourth switches SW3 and SW4, respectively. By being supplied from the second integration circuits C1 and C2, the first and second integration circuits C1 and C2 are discharged in the minus direction.

  The current bypass circuit 15 includes a diode D 1 and a voltage source 17. The current bypass circuit 15 is configured to discharge the bias current source when the first and second integration circuits C1 and C2 are not charged in the positive direction by the voltage-current conversion circuit 13 and are not discharged in the negative direction by the discharge bias current source 14. 14 is a circuit through which a discharging current Id to 14 flows.

  The first and second switches SW1 and SW2 are turned on and off to charge the first and second integrating circuits C1 and C2 in the plus direction. The first and second switches SW1, SW2 are turned on and off based on the first and second switching signals φ1, φ2 output from the dead time generation circuit 11. That is, as shown in FIG. 3B, the first switch SW1 is turned on when the first switching signal φ1 is at a high level, and is turned off when the first switching signal φ1 is at a low level. As shown in FIG. 3C, the second switch SW2 is turned on when the second switching signal φ2 is at a high level, and is turned off when the second switching signal φ2 is at a low level.

  The third and fourth switches SW3 and SW4 are turned on and off to discharge the first and second integrating circuits C1 and C2 in the negative direction by the discharge bias current Id supplied by the discharge bias current source 14. Circuit. The third and fourth switches SW3 and SW4 are turned on and off based on the control signals φ3 and φ4 from the signal output circuit 16. That is, the third switch SW3 is turned on when the control signal φ3 is at a high level, and is turned off when the control signal φ3 is at a low level. The fourth switch SW4 is turned on when the control signal φ4 is at a high level and turned off when the control signal φ4 is at a low level. The control signals φ3 and φ4 are output from second and fourth NAND circuits NA2 and NA4, which will be described later, of the signal output circuit 16.

  Each of the first and second integrating circuits C1 and C2 is configured by a charging capacitor, and is a circuit that charges by storing a predetermined charge and discharges by discharging the charge.

  Specifically, in the first integration circuit C1, the first switch SW1 is turned on (the third switch SW3 is turned off at this time) in the first period T1 (excluding the predetermined time Δt that is strictly a dead time). ), A current flows from the voltage-current conversion circuit 13 to the first integration circuit C1, thereby charging in the positive direction. In addition, the first integrating circuit C1 is configured to turn on the third switch SW3 during the next second period T2 (at this time, the first switch SW1 is turned off). It is discharged in the negative direction by the current Id.

  On the other hand, in the second integration circuit C2, the second switch SW2 is turned on (at this time, in the second period T2 during which the first integration circuit C1 is discharged (excluding the predetermined time Δt that is strictly a dead time)). When the 4-switch SW4 is turned off), a current flows from the voltage-current conversion circuit 13 to the second integration circuit C2, and is thereby charged in the plus direction. In addition, the second integration circuit C2 is configured to turn on the fourth switch SW4 during the next third period T3 (in this case, the second switch SW2 is turned off). It is discharged in the negative direction by the current Id.

  As described above, in the first and second integrating circuits C1 and C2, the unit period (for example, the first period T1 or the second period T2) in which the levels of the first and second switching signals φ1 and φ2 are maintained alternately. Charging and discharging are performed.

  Here, the circuit connection configuration relating to charging / discharging of the first and second integrating circuits C1 and C2 will be described. The voltage-current conversion circuit 13 is connected to one end of each of the first and second switches SW1 and SW2, and the first The other end of the switch SW1 is connected to one end of the first integration circuit C1, thereby forming a charging path in the positive direction of the first integration circuit C1. The other end of the first integrating circuit C1 is connected to the ground potential. One end of the first integrating circuit C1 is also connected to one end of the third switch SW3, and the other end of the third switch SW3 is connected to the discharging bias current source 14, and thereby the first integrating circuit C1 A discharge path in the negative direction is formed.

  On the other hand, the other end of the second switch SW2 is connected to one end of the second integrating circuit C2, thereby forming a charging path in the positive direction of the second integrating circuit C2. The other end of the second integration circuit C2 is connected to the ground potential. One end of the second integrating circuit C2 is also connected to one end of the fourth switch SW4, and the other end of the fourth switch SW4 is connected to the discharging bias current source 14, thereby allowing the second integrating circuit C2 to A discharge path in the negative direction is formed.

  As shown in FIG. 2, the signal output circuit 16 includes a logic circuit in which a plurality of logic elements are combined. The signal output circuit 16 includes first and second comparison circuits 23 and 24, first and second RS flip-flop circuits 43 and 44, and And a fifth NAND circuit NA5.

  The first comparison circuit 23 has, for example, a reference voltage switching circuit 18 whose positive (+) input terminal is connected to one end of the first integration circuit C1, and whose negative (−) input terminal is a source of the reference voltage Vref. It is connected to the. The second comparison circuit 24 has a positive (+) side input terminal connected to one end of the second integration circuit C2, and a negative (−) side input terminal connected to the reference voltage switching circuit 19 which is a source of the reference voltage Vref. Has been. The output of the first comparison circuit 23 is input to the first RS flip-flop circuit 43 as the reset signal res1. The output of the second comparison circuit 24 is input to the second RS flip-flop circuit 44 as the reset signal res2.

  The first and second RS flip-flop circuits 43 and 44 are circuits for holding the outputs of the first and second comparison circuits 23 and 24, respectively, for a predetermined period. The first RS flip-flop circuit 43 is configured by combining the first and second NAND circuits NA1 and NA2. Within the first RS flip-flop circuit 43, each output terminal of the first and second NAND circuits NA1 and NA2 is one of the other. Connected to the input terminal.

  The other input terminal of the first NAND circuit NA1 is connected to the output of the first comparison circuit 23 and is a terminal to which a reset signal res1 as an RS flip-flop is input. The other input terminal of the second NAND circuit NA2 is This terminal is connected to the downstream edge detection circuit 12 and receives a set signal set1 as an RS flip-flop. The output terminal of the second NAND circuit NA2 is connected to the third switch SW3 as the control signal φ3.

  On the other hand, the second RS flip-flop circuit 44 is configured by combining the third and fourth NAND circuits NA3 and NA4. In the second RS flip-flop circuit 44, the output terminals of the third and fourth NAND circuits NA3 and NA4 are mutually connected. Is connected to one input terminal.

  The other input terminal of the third NAND circuit NA3 is connected to the output of the second comparison circuit 24, and is a terminal to which a reset signal res2 as an RS flip-flop is input. The other input terminal of the fourth NAND circuit NA4 is This terminal is connected to the falling edge detection circuit 12 and receives a set signal set2 as an RS flip-flop. The output terminal of the fourth NAND circuit NA4 is connected to the fourth switch SW4 as the control signal φ4.

  The output terminal of the first NAND circuit NA1 of the first RS flip-flop circuit 43 and the output terminal of the third NAND circuit NA3 of the second RS flip-flop circuit 44 are connected to the input terminals of the fifth NAND circuit NA5. The output signal rsout1 is output from the output terminal of the first NAND circuit NA1, and the output signal rsout2 is output from the output terminal of the third NAND circuit NA3. The pulse width modulation signal PWMout is output from the output terminal of the fifth NAND circuit NA5.

  The clock frequency control unit 9 is a circuit that controls the clock generation circuit 10 to change the frequency of the reference clock signal MCLK. For example, the clock frequency control unit 9 changes the frequency of the reference clock signal MCLK from the first frequency that is the reference frequency to the second frequency that is lower than the first frequency or higher than the first frequency. The clock generation circuit 10 is controlled to change to a certain third frequency. As a result, the clock generation circuit 10 outputs the reference clock signal MCLK whose frequency has been changed according to the control signal from the clock frequency control unit 9.

  Further, the clock frequency control unit 9 outputs a fifth switching signal φ5 to the reference voltage switching circuits 18 and 19. The fifth switching signal φ5 is normally a low level, and is a signal that is inverted to a high level only during a period in which the clock generation circuit 10 generates the reference clock signal MCLK having the second frequency. That is, the fifth switching signal is a signal for switching the reference voltage supplied to the negative side input terminals of the first and second comparison circuits 23 and 24.

  The reference voltage switching circuit 18 is a circuit that receives the fifth switching signal φ5 from the clock frequency control unit 9 and switches the reference voltage Vref supplied to the negative side input terminal of the first comparison circuit 23. When the frequency of the reference clock signal MCLK is the first or third frequency, the reference voltage switching circuit 18 receives the low-level fifth switching signal φ5 and receives the first reference voltage Vref1 that is a normal reference voltage. 1 is supplied to the negative input terminal of the comparison circuit 23. On the other hand, when the frequency of the reference clock signal MCLK is the second frequency (that is, the reference clock signal MCLK is a low frequency), the reference voltage switching circuit 18 receives the high-level fifth switching signal φ5, The second reference voltage Vref2 having a voltage value smaller than the one reference voltage Vref1 is supplied to the negative side input terminal of the first comparison circuit 23.

  The reference voltage switching circuit 18 includes resistors R1 to R3 and a fifth switch SW5. One end of the resistor R1 is connected to the power supply voltage VCC, and the other end is connected to one end of the resistor R2, one end of the fifth switch SW5, and the negative input terminal of the first comparison circuit 23. One end of the resistor R3 is connected to the other end of the fifth switch SW5, and the other end is connected to the ground potential. The other end of the resistor R2 is connected to the ground potential.

  The fifth switch SW5 is supplied with the fifth switching signal φ5 and is turned on when the fifth switching signal φ5 is at a high level, and is turned off when the fifth switching signal φ5 is at a low level. The reference voltage switching circuit 18 has a first reference voltage Vref1 (Vref1 = (VCC × R2) / (R1 + R2)) applied to the negative input terminal of the first comparison circuit 23 when the fifth switch SW5 is turned off. Supply. On the other hand, when the fifth switch SW5 is turned on, the reference voltage switching circuit 18 applies a second reference voltage Vref2 (Vref2 = (VCC × R2R3) / (R1R2 + R2R3 + R3R1) to the negative input terminal of the first comparison circuit 23. )).

  The reference voltage switching circuit 19 is a circuit that receives the fifth switching signal φ5 from the clock frequency control unit 9 and switches the reference voltage Vref supplied to the negative side input terminal of the second comparison circuit 24. When the frequency of the reference clock signal MCLK is the first or third frequency, the reference voltage switching circuit 19 receives the low-level fifth switching signal φ5 and receives the first reference voltage Vref1 that is a normal reference voltage. 2 is supplied to the negative input terminal of the comparison circuit 24. On the other hand, when the frequency of the reference clock signal MCLK is the second frequency (that is, the reference clock signal MCLK is a low frequency), the reference voltage switching circuit 19 receives the high-level fifth switching signal φ5, The second reference voltage Vref2 having a voltage value smaller than the one reference voltage Vref1 is supplied to the negative side input terminal of the second comparison circuit 24.

  The reference voltage switching circuit 19 includes resistors R4 to R6 and a sixth switch SW6. One end of the resistor R4 is connected to the power supply voltage VCC, and the other end is connected to one end of the resistor R5, one end of the sixth switch SW6, and the negative side input terminal of the second comparison circuit 24. One end of the resistor R6 is connected to the other end of the sixth switch SW6, and the other end is connected to the ground potential. The other end of the resistor R5 is connected to the ground potential.

  The sixth switch SW6 is supplied with the fifth switching signal φ5 and is turned on when the fifth switching signal φ5 is at a high level, and is turned off when the fifth switching signal φ5 is at a low level. The reference voltage switching circuit 19 has a first reference voltage Vref1 (Vref1 = (VCC × R5) / (R4 + R5)) applied to the negative input terminal of the second comparison circuit 24 when the sixth switch SW6 is turned off. Supply. On the other hand, when the sixth switch SW6 is turned on, the reference voltage switching circuit 19 has a second reference voltage Vref2 (Vref2 = (VCC × R5R6) / (R4R5 + R5R6 + R6R4) applied to the negative input terminal of the second comparison circuit 24. )).

  In order to make the reference voltages supplied to the first and second comparison circuits 23 and 24 the same, R1 = R4, R2 = R5, and R3 = R6.

  Here, the charge amount ΔQc charged in the first and second integrating circuits C1 and C2 during the charging period is expressed as ΔQc = I * T / 2 by the charging current I and the clock cycle T. When the audio signal eS is no signal, I = I1, and the voltage change ΔV during the charging period is ΔV = ΔQc / C = I1 * T / (using the capacitance C of the first and second integration circuits C1 and C2. 2 * C). That is, the voltage values of the first and second integration circuits C1 and C2 at the end of charging are determined by the balance of the capacitor capacity, the charging time (clock frequency), and the charging current amount. In this example, when the reference clock signal MCLK is at the second frequency, the chargeable voltage of the first and second integration circuits C1 and C2 is increased by switching the reference voltage Vref to a small value. Thus, the voltage upper limit VCC at the time of charging and the reference voltage Vref are set, and the condition of ΔV <= (VCC−Vref) / 2 when there is no signal (that is, the maximum charging voltage Va <= (VCC + Vref) / 2 when there is no signal) By satisfying (condition), the charging voltage can be prevented from being limited as will be described in detail later.

Hereinafter, operations and effects of the pulse width modulation circuit 1 will be described. First, the basic operation of the pulse width modulation circuit 1 will be described.
4 to 6 are timing charts showing respective signals in the pulse width modulation circuit 1. FIG. 4 shows a case where the audio signal eS is no signal (Gm · eS = 0), FIG. 5 shows a case where the audio signal eS is a positive value, and FIG. The negative case is shown.

  In the first period T1 in FIG. 4, since the first switching signal φ1 from the dead time generation circuit 11 is at a high level (see FIG. 4B), the first switch SW1 is turned on. Therefore, the first integration circuit C1 is charged in the plus direction by the current (Ic + Δi) from the voltage-current conversion circuit 13 (see FIG. 4 (h)).

  When the first switching signal φ1 is inverted from the high level to the low level, the process proceeds to the second period T2, and the falling edge detection circuit 12 detects the falling edge when the first switching signal φ1 is inverted, and the first RS The first set signal set1 is output to the flip-flop circuit 43 (see FIG. 4D).

  In the first RS flip-flop circuit 43, when a signal that instantaneously changes to low level is input as the first set signal set1, the second NAND circuit NA2 inverts its output from low level to high level. Since the output of the second NAND circuit NA2 is input to the third switch SW3 as the control signal φ3 (see FIG. 4F), the third switch SW3 is turned on. As a result, the first integrating circuit C1 is discharged in the negative direction by a constant discharge amount by the discharging bias current source 14 (see FIG. 4H).

  In the first RS flip-flop circuit 43, when a signal that instantaneously changes to the low level is input as the first set signal set1, the first NAND circuit NA1 inverts the output from the high level to the low level. The output of the first NAND circuit NA1 is input to the fifth NAND circuit NA5 as the output signal rsout1 (see FIG. 4L).

  In the first comparison circuit 23, the terminal voltage of the first integration circuit C1 is discharged in the negative direction until reaching the reference voltage Vref input to the negative side input terminal, and when the terminal voltage reaches the reference voltage Vref, the first comparison circuit 23 23 changes its output from a high level to a low level (see FIG. 4J). The output of the first comparison circuit 23 is input to the first RS flip-flop circuit 43 as the first reset signal res1.

  In the first RS flip-flop circuit 43, when the first reset signal res1 changes from the high level to the low level, the output signal rsout1 changes from the low level to the high level and is input to the fifth NAND circuit NA5 (FIG. 4 (l )reference). In the fifth NAND circuit NA5, since the other input terminal (rsout2) is at a high level, the output signal rsout1 is inverted and output to the switching circuit 2 as the pulse width modulation signal PWMout (see FIG. 4 (n)).

  On the other hand, in the second period T2, since the second switching signal φ2 from the dead time generation circuit 11 is at a high level (see FIG. 4C), the second switch SW2 is turned on. Therefore, the second integration circuit C2 is charged in the plus direction by the current (Ic + Δi) from the voltage-current conversion circuit 13 (see FIG. 4 (i)).

  When the second switching signal φ2 is inverted from the high level to the low level, the process proceeds to the third period T3, and the falling edge detection circuit 12 detects the falling edge when the second switching signal φ2 is inverted, and the second RS The signal is output to the flip-flop circuit 44 as the second set signal set2 (see FIG. 4E).

  In the second RS flip-flop circuit 44, when a signal that instantaneously changes to the low level is input as the second set signal set2, the fourth NAND circuit NA4 inverts the output from the low level to the high level. Since the output of the fourth NAND circuit NA4 is input to the fourth switch SW4 as the control signal φ4 (see FIG. 4G), the fourth switch SW4 is turned on. As a result, the second integrating circuit C2 is discharged in the negative direction by a constant discharge amount by the discharging bias current source 14 (see FIG. 4 (i)).

  In the second RS flip-flop circuit 44, when a signal that instantaneously changes to the low level is input as the second set signal set2, the third NAND circuit NA3 inverts the output from the high level to the low level. The output of the third NAND circuit NA3 is input to the fifth NAND circuit NA5 as the output signal rsout2 (see FIG. 4 (m)).

  In the second comparison circuit 24, the terminal voltage of the second integration circuit C2 is discharged in the negative direction until it reaches the reference voltage Vref input to the negative input terminal, and when the terminal voltage reaches the reference voltage Vref, the output is high level. From low to low. The output of the second comparison circuit 24 is input to the second RS flip-flop circuit 44 as the second reset signal res2 (see FIG. 4 (k)).

  In the second RS flip-flop circuit 44, when the second reset signal res2 changes from the high level to the low level, the output signal rsout2 changes from the low level to the high level and is input to the fifth NAND circuit NA5 (FIG. 4 (m )reference). In the fifth NAND circuit NA5, since the other input terminal (rsout1) is at the high level, the output signal rsout2 is inverted and output to the switching circuit 2 as the pulse width modulation signal PWMout (see FIG. 4 (n)).

  As shown in FIG. 5, when the audio signal eS is positive, the magnitude of the current (Ic + Δi) becomes large, and the slope of the voltage waveform at one end of the first or second integrating circuit C1, C2 is also the audio signal eS. Larger than in the case of no signal. Therefore, the terminal voltage of the first or second integrating circuit C1, C2 at the time when the level of the first or second switching signal φ1, φ2 is inverted becomes larger than that in the case where the audio signal eS is no signal. When these are discharged in the minus direction, the time t until the reference voltage Vref is reached after the discharge is started becomes longer than in the case where the audio signal eS is no signal. Therefore, as shown in FIG. 5 (n), compared to the case where the audio signal eS shown in FIG. 4 is no signal, the pulse width modulation signal PWMout having a long high level is output. Thus, the pulse width modulation signal PWMout corresponding to the amplitude of the audio signal eS is output.

  As shown in FIG. 6, when the audio signal eS is negative, the magnitude of the current (Ic + Δi) is small, and the slope of the voltage waveform at one end of the first or second integrating circuit C1, C2 is small. Become. Therefore, the terminal voltage of the first or second integrating circuit C1, C2 at the time when the level of the first or second switching signal φ1, φ2 is inverted becomes smaller than that when the audio signal eS is no signal. When these are discharged in the minus direction, the time t until the reference voltage Vref is reached after the discharge is started is shorter than when the audio signal eS is no signal. Therefore, as shown in FIG. 6 (n), the pulse width modulation signal PWMout having a short high level time is output compared to the case where the audio signal eS shown in FIG. 4 is no signal.

  Incidentally, the period of the first and second switching signals φ1 and φ2 increases during the period in which the clock frequency control unit 9 causes the clock generation circuit 10 to generate the reference clock signal MCLK having the second frequency. Therefore, when the audio signal eS is positive as shown in FIG. 5, the charging time of the first or second integrating circuit C1, C2 becomes very long. However, since the chargeable voltage of the first or second integration circuit C1, C2 is the power supply voltage VCC (upper limit) -reference voltage Vref (lower limit), the high-level period of the first and second switching signals φ1, φ2 Is completed, the charging voltage of the first or second integrating circuit C1, C2 reaches the power supply voltage VCC which is the upper limit of the chargeable voltage, and as a result, the charging of the first or second integrating circuit C1, C2 is performed. The voltage waveform is limited, and a normal PWM waveform is not output.

  Therefore, when the reference clock signal MCLK has the second frequency, the reference voltage Vref supplied by the reference voltage switching circuits 18 and 19 to the negative side input terminals of the first and second comparison circuits 23 and 24 is the second reference. By switching to the voltage Vref2, the chargeable voltage of the first or second integrating circuit C1, C2 is increased. This prevents the charging voltage of the first or second integrating circuit C1, C2 from reaching the power supply voltage VCC before the high-level period of the first and second switching signals φ1, φ2 ends, Enable to output PWM waveform.

  Here, the first reference voltage Vref1 and the second reference voltage Vref2 are such that the maximum charging voltage of the first and second integration circuits C1 and C2 when the amplitude value of the audio signal eS is a positive maximum value exceeds the power supply voltage VCC. In other words, the maximum charging voltage (voltage at the end of charging) Va of the first and second integrating circuits C1 and C2 when the audio signal eS is no signal is set to the first and second values. The voltage is set to be equal to or less than ½ of the chargeable voltage of the integration circuits C1 and C2 (that is, (VCC + Vref) / 2 or less).

  Hereinafter, the reference voltage switching circuit 18 will be described in detail as an example, but the same applies to the reference voltage switching circuit 19. FIG. 7 is a diagram illustrating a charging voltage waveform of the first integrating circuit C1 when the frequency of the reference clock signal MCLK is changed. FIG. 7A illustrates a case where the reference clock signal MCLK has the first frequency. Indicates a case where the reference clock signal MCLK is at the second frequency, and (c) indicates a case where the reference clock signal MCLK is at the third frequency. In FIG. 7, waveform (1) shows the case where the audio signal eS is no signal, and waveform (2) shows the case where the amplitude value of the audio signal eS is positive and the maximum value.

  As shown in FIG. 7A, when the frequency of the reference clock signal MCLK is the first frequency (reference frequency), the clock frequency control unit 9 maintains the fifth switching signal φ5 at the low level. In the switching circuit 18, the fifth switch SW5 is turned off. Thereby, the reference voltage Vref supplied to the negative side input terminal of the first comparison circuit 23 is maintained at the first reference voltage Vref1, which is a normal reference voltage. As a result, the chargeable voltage of the first integrating circuit C1 is maintained at VCC-Vref1, which is a normal voltage. However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is the reference frequency, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is less than half the chargeable voltage of the first integrating circuit C1. Does not reach the power supply voltage VCC. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 7B, when the frequency of the reference clock signal MCLK is the second frequency (a frequency lower than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the high level. In the reference voltage switching circuit 18, the fifth switch SW5 is turned on. As a result, the reference voltage Vref supplied to the negative input terminal of the first comparison circuit 23 is switched to the second reference voltage Vref2 having a voltage value smaller than the normal reference voltage Vref1. As a result, the chargeable voltage (VCC-Vref2) of the first integrating circuit C1 is increased, and the audio signal eS is not signaled although the charging time to the first integrating circuit C1 is longer than that in FIG. In this case, the maximum charging voltage Va of the first integration circuit C1 can be set to a voltage equal to or less than ½ of the chargeable voltage of the first integration circuit C1. As a result, even if the amplitude value of the audio signal eS is positive and maximum (in the case of the waveform (2)), the maximum charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC. Thus, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is lower than the reference frequency, the charging time increases and the maximum charging voltage to the first integrating circuit C1 increases, but the power supply voltage VCC And the reference voltage Vref2 are sufficiently large, the charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC even if the amplitude value of the audio signal eS is positive and maximum. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 7C, when the frequency of the reference clock signal MCLK is the third frequency (higher than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the low level. Thus, in the reference voltage switching circuit 18, the fifth switch SW5 is turned off. Thereby, the reference voltage Vref supplied to the negative side input terminal of the first comparison circuit 23 is maintained at the first reference voltage Vref1, which is a normal reference voltage. However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is high, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is less than half the chargeable voltage of the first integrating circuit C1. Does not reach the power supply voltage VCC. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  The reference voltage supplied to the second comparison circuit 24 is also switched by the reference voltage switching circuit 19 between the first reference voltage Vref1 and the second reference voltage Vref2 according to the frequency of the reference clock signal MCLK. Therefore, the charging voltage of the second integration circuit C2 is not clipped, and a normal PWM waveform can be output.

[Second Embodiment]
In the first embodiment, when the frequency of the reference clock signal is the second frequency, the first and second integrations are performed by switching the reference voltage Vref to the second reference voltage Vref2 that is lower than the first reference voltage Vref1. Although the chargeable voltage of the circuits C1 and C2 is increased, in this example, when the frequency of the reference clock signal is the second frequency, the power supply voltage VCC is changed to the second power supply voltage VCC2 that is higher than the first power supply voltage VCC1. By switching, the chargeable voltage (range) of the first and second integrating circuits C1 and C2 is increased. FIG. 8 is a block diagram showing the pulse width modulation circuit 201 of this example. In the pulse width modulation circuit 201, the reference voltage Vref is a fixed value, and power supply voltage switching circuits 20 and 21 are provided instead of the reference voltage switching circuits 18 and 19. About another structure, it is the same as that of 1st Embodiment.

  The power supply voltage switching circuit 20 is a circuit that receives the fifth switching signal φ5 from the clock frequency control unit 9 and switches the power supply voltage VCC supplied to the first comparison circuit 23. The power supply voltage switching circuit 20 includes a seventh switch SW7 for selectively supplying the first power supply voltage VCC1 and the second power supply voltage VCC2 having a voltage higher than the first power supply voltage VCC1 to the first comparison circuit 23. Including. The seventh switch SW7 is connected to the first power supply voltage VCC1 when the fifth switching signal φ5 is at a low level, and is connected to the second power supply voltage VCC2 when the fifth switching signal φ5 is at a high level.

  The power supply voltage switching circuit 21 is a circuit that receives the fifth switching signal φ5 from the clock frequency control unit 9 and switches the power supply voltage VCC supplied to the second comparison circuit 24. The power supply voltage switching circuit 21 includes an eighth switch SW8 for selectively supplying the first power supply voltage VCC1 and the second power supply voltage VCC2 having a voltage higher than the first power supply voltage VCC1 to the second comparison circuit 24. Including. The eighth switch SW8 is connected to the first power supply voltage VCC1 when the fifth switching signal φ5 is at a low level, and is connected to the second power supply voltage VCC2 when the fifth switching signal φ5 is at a high level.

  Here, as for the first power supply voltage VCC1 and the second power supply voltage VCC2, the maximum charging voltage of the first and second integrating circuits C1 and C2 when the amplitude value of the audio signal eS is the maximum positive value reaches the power supply voltage VCC. In other words, the maximum charging voltage Va of the first and second integrating circuits C1 and C2 when the audio signal eS is no signal is the charging of the first and second integrating circuits C1 and C2. It is set to be ½ or less of the possible voltage.

  Hereinafter, the operation of the power supply voltage switching circuit 20 will be described as an example. FIG. 9 is a diagram illustrating a charging voltage waveform of the first integration circuit C1 when the frequency of the reference clock signal MCLK is changed. FIG. 9A illustrates the case where the reference clock signal MCLK has the first frequency. Shows the case of the second frequency, and (c) shows the case of the third frequency. In FIG. 9, waveform (1) shows the case where the audio signal eS is no signal, and waveform (2) shows the case where the amplitude value of the audio signal eS is positive and the maximum value.

  As shown in FIG. 9A, when the frequency of the reference clock signal MCLK is the first frequency (reference frequency), the clock frequency control unit 9 maintains the fifth switching signal φ5 at the low level. In the switching circuit 20, the seventh switch SW7 selects the first power supply voltage VCC1. As a result, the power supply voltage VCC supplied to the first comparison circuit 23 is maintained at the first power supply voltage VCC1, which is a normal power supply voltage. As a result, the chargeable voltage of the first integrating circuit C1 is maintained at VCC1-Vref, which is a normal voltage. However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is the reference frequency, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply. The voltage VCC1 is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 9B, when the frequency of the reference clock signal MCLK is the second frequency (a frequency lower than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the high level. In the power supply voltage switching circuit 20, the seventh switch SW7 selects the second power supply voltage VCC2. As a result, the power supply voltage VCC supplied to the first comparison circuit 23 is switched to the second power supply voltage VCC2 having a voltage value higher than that of the normal power supply voltage VCC1. As a result, the chargeable voltage (VCC2-Vref) of the first integration circuit C1 is increased, and the audio signal eS is not signaled although the charging time to the first integration circuit C1 is longer than that in FIG. In this case, the maximum charging voltage Va of the first integrating circuit C1 can be set to ½ or less of the chargeable voltage of the first integrating circuit C1. As a result, even if the amplitude value of the audio signal eS is positive and maximum (in the case of the waveform (2)), the maximum charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC. Thus, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is lower than the reference frequency, the charging time increases and the charging voltage to the first integrating circuit C1 increases, but the second power supply voltage Since the difference between VCC2 and the reference voltage Vref is sufficiently large, even if the amplitude value of the audio signal eS is positive and maximum, the charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 9C, when the frequency of the reference clock signal MCLK is the third frequency (higher than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the low level. Thus, in the power supply voltage switching circuit 20, the seventh switch SW7 is turned off. As a result, the power supply voltage VCC supplied to the first comparison circuit 23 is maintained at the first power supply voltage VCC1, which is a normal power supply voltage. However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is high, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply. The voltage VCC is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  The power supply voltage supplied to the second comparison circuit 24 is also switched by the power supply voltage switching circuit 21 between the first power supply voltage VCC1 and the second power supply voltage VCC2 according to the frequency of the reference clock signal MCLK. Therefore, the charging voltage of the second integration circuit C2 is not clipped, and a normal PWM waveform can be output.

[Third Embodiment]
In the first and second embodiments, when the reference clock frequency MCLK is the second frequency, the chargeable voltage of the first and second integration circuits C1 and C2, which is the difference between the power supply voltage VCC and the reference voltage Vref, is increased. This prevents the charging voltages of the first and second integration circuits C1 and C2 from being clipped. In this example, when the reference clock signal MCLK has the second frequency, the first and second integration circuits The charging voltage of the first and second integrating circuits C1 and C2 is prevented from being clipped by reducing the charging voltage change width (change width per unit time, voltage gradient) during charging of C1 and C2. . Specifically, when the reference clock signal MCLK is at the second frequency, the charge waveform slope is reduced by increasing the capacitance (time constant) of the first and second integration circuits C1 and C2. FIG. 10 is a block diagram showing the pulse width modulation circuit 301 of this example. In the pulse width modulation circuit 301, capacity switching circuits 22 and 23 are provided instead of the reference voltage switching circuits 18 and 19. About another structure, it is the same as that of 1st Embodiment.

  The capacity switching circuit 22 is a circuit that receives the fifth switching signal φ5 from the clock frequency control unit 9 and switches the capacity of the first integrating circuit C1. The capacitance switching circuit 22 includes a capacitor C3 and a ninth switch SW9 connected in parallel to the first integrating circuit C1. The ninth switch SW9 is turned off when the fifth switching signal φ5 is at a low level, and maintains the capacitance of the first integrating circuit C1 at the first capacitance C1. On the other hand, the ninth switch SW9 is turned on when the fifth switching signal φ5 is at a high level, and switches the capacity of the first integrating circuit C1 to a second capacity (C1 + C3) larger than the first capacity.

  The capacity switching circuit 23 is a circuit that receives the fifth switching signal φ5 from the clock frequency control unit 9 and switches the capacity of the second integrating circuit C2. The capacitance switching circuit 23 includes a capacitor C4 and a tenth switch SW10 connected in parallel to the second integrating circuit C2. The tenth switch SW10 is turned off when the fifth switching signal φ5 is at a low level, and maintains the capacitance of the second integration circuit C2 at the first capacitance C1. On the other hand, the tenth switch SW10 is turned on when the fifth switching signal φ5 is at a high level, and switches the capacity of the second integrating circuit C2 to a second capacity (C2 + C4) larger than the first capacity.

  Here, the capacitances of the first and second integration circuits C1 and C2 and the capacitances of the capacitors C3 and C4 are the first and second integration circuits C1 (or when the amplitude value of the audio signal eS is a positive maximum value). C1 + C3), C2 (or C2 + C4) is set so that the maximum charging voltage does not reach the power supply voltage VCC, that is, the first and second integration circuits C1 (or C1 + C3) when the audio signal eS is no signal, The maximum charge voltage Va of C2 (or C2 + C4) is set to be ½ or less of the chargeable voltage of the first and second integration circuits C1 and C2.

  Hereinafter, the operation of the capacitance switching circuit 22 will be described as an example. FIG. 11 is a diagram illustrating a charging voltage waveform of the first integrating circuit C1 (C1 or C1 + C3) when the frequency of the reference clock signal MCLK is changed. FIG. 11A is a diagram illustrating the reference clock signal MCLK at the first frequency. In some cases, (b) shows the case of the second frequency, and (c) shows the case of the third frequency. In FIG. 9, waveform (1) shows the case where the audio signal eS is no signal, and waveform (2) shows the case where the amplitude value of the audio signal eS is positive and the maximum value.

  As shown in FIG. 11A, when the frequency of the reference clock signal MCLK is the first frequency (reference frequency), the clock frequency control unit 9 maintains the fifth switching signal φ5 at the low level. In the circuit 22, the ninth switch SW9 is turned off. As a result, the capacity of the first integrating circuit C1 is maintained at the first capacity C1, which is a normal capacity. As a result, the voltage change value during charging of the first integration circuit C1 is maintained at a normal value (normal slope). However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is the reference frequency, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply. The voltage VCC1 is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 11B, when the frequency of the reference clock signal MCLK is the second frequency (a frequency lower than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the high level. In the capacitance switching circuit 20, the ninth switch SW9 is turned on. Thereby, the capacity | capacitance of the 1st integrating circuit C1 is switched to 2nd capacity | capacitance C1 + C3 larger than a normal capacity | capacitance. Thereby, since the time constant becomes large, the voltage change value at the time of charging of the first integrating circuit C1 becomes small (the inclination becomes small), and the charging time to the first integrating circuit C1 is longer than that in FIG. Nevertheless, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal can be made ½ or less of the chargeable voltage of the first integrating circuit C1. As a result, even if the amplitude value of the audio signal eS is positive and maximum (in the case of the waveform (2)), the maximum charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC. Thus, the charging time increases because the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is lower than the reference frequency, but the voltage change amount is small, so the amplitude value of the audio signal eS. Even if is a positive and maximum value, the charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 11C, when the frequency of the reference clock signal MCLK is the third frequency (higher than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the low level. Therefore, in the capacitance switching circuit 22, the ninth switch SW9 is turned off. As a result, the capacity of the first integrating circuit C1 is maintained at the first capacity C1, which is a normal capacity. However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is high, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply. The voltage VCC is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Note that the capacitance of the second integration circuit C2 is also switched by the capacitance switching circuit 23 between the first capacitance C2 and the second capacitance C2 + C4 according to the frequency of the reference clock signal MCLK. Therefore, the charging voltage of the second integration circuit C2 is not clipped, and a normal PWM waveform can be output.

[Fourth Embodiment]
In the third embodiment, when the reference clock signal has the second frequency, the capacities of the first and second integration circuits C1 and C2 are increased, thereby charging and discharging the first and second integration circuits C1 and C2. Although the amount of change in the charging voltage is reduced to prevent the charging voltage of the first and second integrating circuits C1 and C2 from clipping, in this example, when the reference clock signal is at the second frequency, By reducing the current amount itself supplied to the first and second integration circuits C1 and C2, the amount of change in the charging voltage during charging of the first and second integration circuits C1 and C2 is reduced, so that the first and second The charging voltage of the integrating circuits C1 and C2 is prevented from clipping. FIG. 12 is a block diagram showing the pulse width modulation circuit 401 of this example. In the pulse width modulation circuit 401, a current switching circuit 24 is provided instead of the capacitance switching circuits 22 and 23 of FIG. About another structure, it is the same as that of 3rd Embodiment.

  The current switching circuit 24 receives the fifth switching signal φ5 from the clock frequency control unit 9 and supplies the current amount of current supplied to charge the first and second integrating circuits C1 and C2, and the first and first currents. 2 is a circuit for switching the amount of current supplied to discharge the integrating circuits C1 and C2. The current switching circuit 24 includes a first current source 25, a second current source 26, an eleventh switch SW11, and a twelfth switch SW12. The first current source 25 adds the current Id1 to the current output from the voltage / current conversion circuit 13, and one end is connected to the input end of the voltage / current conversion circuit 13 and the other end is connected to the eleventh switch SW11. Yes. The eleventh switch SW11 switches whether to add the current Id1 of the first current source 25 to the current Ic + Δi of the voltage-current conversion circuit 13. The second current source 26 adds the current Id3 to the discharging current Id2 supplied from the discharging bias current source 14, and has one end connected to the ground potential and the other end connected to the twelfth switch SW12. The twelfth switch SW12 switches whether or not the current Id3 is added to the discharging current Id2 supplied from the discharging bias current source 14.

  The eleventh switch SW11 is connected to the output terminal of the voltage / current conversion circuit 13 when the fifth switching signal φ5 is at the low level, and adds the current Id1 of the first current source 25 to the charging current, and the charging current is set to the normal current. The first current Ic + Δi + Id1, which is the current amount, is set. On the other hand, the eleventh switch SW11 is connected to the ground potential when the fifth switching signal φ5 is at the high level, and does not add the current Id1 of the first current source 25 to the charging current, and the charging current is more than the normal current amount. Is set to the second current Ic + Δi having a small current amount.

  The twelfth switch SW12 is connected to the discharge bias current source 14 when the fifth switching signal φ5 is at a low level, adds the current Id3 of the second current source 26 to the discharge current, and uses the discharge current as a normal current. The amount of the third current Id2 + Id3 is set. On the other hand, the twelfth switch SW11 is connected to the input terminal of the voltage-current conversion circuit 13 when the fifth switching signal φ5 is at the high level, and does not add the current Id3 of the second current source 26 to the discharge current. Is a fourth current Id2 having a smaller current amount than the normal current amount.

  Here, the first to fourth currents are such that the maximum charging voltage of the first and second integrating circuits C1 and C2 when the amplitude value of the audio signal eS is a positive maximum value does not reach the power supply voltage VCC. That is, the maximum charging voltage Va of the first and second integrating circuits C1 and C2 when the audio signal eS is no signal is the chargeable voltage of the first and second integrating circuits C1 and C2. It is set to be 1/2 or less. Further, in order to output a normal PWM waveform, the first to fourth currents have the ratio of the charging current to the discharging current when the audio signal eS is no signal, and the eleventh switch SW11 and the twelfth switch. It is set so as not to change by switching of SW12.

  Hereinafter, the operation of the pulse width modulation circuit 401 will be described with reference to FIG. As shown in FIG. 11A, when the frequency of the reference clock signal MCLK is the first frequency (reference frequency), the clock frequency control unit 9 maintains the fifth switching signal φ5 at the low level. In the circuit 24, the eleventh switch SW11 selects the output terminal of the voltage-current converter circuit 13. As a result, the charging current becomes a first current having a normal current amount Ic + Δi + Id1. As a result, the amount of voltage change during charging of the first integration circuit C1 is maintained at a normal value (normal inclination). Similarly, the twelfth switch SW12 selects the discharge bias current source 14 side. As a result, the discharging current becomes a third current having a normal current amount Id2 + Id3. As a result, the voltage change amount at the time of discharging of the first integration circuit C1 is maintained at a normal value (normal inclination). However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is the reference frequency, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply. The voltage VCC1 is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 11B, when the frequency of the reference clock signal MCLK is the second frequency (a frequency lower than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the high level. In the current switching circuit 24, the eleventh switch SW11 selects the ground potential. As a result, the charging current is switched to the second current having a smaller current amount (Ic + Δi) than the first current. Similarly, since the second switch SW12 selects the input terminal of the voltage-current conversion circuit 13, the discharge current is switched to a fourth current that is smaller (Id2) than the third current. As a result, the amount of voltage change during charging / discharging of the first integration circuit C1 is reduced (the inclination is reduced), and the audio is charged even though the charging time to the first integration circuit C1 is longer than that in FIG. The maximum charging voltage Va of the first integrating circuit C1 when the signal eS is no signal can be set to ½ or less of the chargeable voltage of the first integrating circuit C1. As a result, even if the amplitude value of the audio signal eS is positive and maximum (in the case of the waveform (2)), the maximum charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC. Thus, the charging time increases because the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is lower than the reference frequency, but the voltage change amount is small, so the amplitude value of the audio signal eS. Even if is a positive and maximum value, the charging voltage of the first integrating circuit C1 does not reach the power supply voltage VCC. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

  Next, as shown in FIG. 11C, when the frequency of the reference clock signal MCLK is the third frequency (higher than the reference frequency), the clock frequency control unit 9 sets the fifth switching signal φ5 to the low level. Therefore, in the current switching circuit 24, the eleventh switch SW11 selects the output terminal of the voltage-current conversion circuit 13. As a result, the charging current becomes a first current that is a normal current amount (Ic + Δi + Id1). Similarly, since the twelfth switch SW12 selects the discharge bias current source, the discharge current becomes a third current that is a normal current amount (Id2 + Id3). However, in this case, since the frequency of the reference clock signal MCLK (that is, the first switching signal φ1) is high, the maximum charging voltage Va of the first integrating circuit C1 when the audio signal eS is no signal is As a result, even if the amplitude value of the audio signal eS is positive and maximum, the maximum charging voltage of the first integrating circuit C1 is the power supply. The voltage VCC is not reached. Therefore, the charging voltage of the first integration circuit C1 is not clipped, and a normal PWM waveform can be output.

[Fifth Embodiment]
In the fourth embodiment, the charging current and the discharging current itself are changed by providing the first current source 25 and the second current source 26. In this example, the current control unit 27 is a voltage-current conversion circuit. 13 and the discharge bias current source 14 are controlled to switch the output charging current and discharging current. FIG. 13 is a circuit diagram showing the pulse width modulation circuit 501 of this example. The pulse width modulation circuit 501 is provided with a current control unit 27 instead of the current switching circuit 24 as compared with the circuit of FIG. Other configurations are the same as those of the circuit of FIG.

  The current control unit 27 is supplied with the fifth switching signal φ5 from the clock frequency control unit 9, and when the fifth switching signal φ5 is low level, the charging current is the first current and the discharging current is the third current. The voltage-current conversion circuit 13 and the discharge bias current source 14 are controlled so as to become current. On the other hand, when the fifth switching signal φ5 is at a high level, the current control unit 27 sets the voltage-current conversion circuit 13 and the discharging bias so that the charging current becomes the second current and the discharging current becomes the fourth current. The current source 14 is controlled. The voltage-current conversion circuit 13 and the discharge bias current source 14 are configured by variable current sources, and switch and output the charge current and the discharge current according to a control signal from the current control unit 27. The operation waveform is the same as that of the circuit of FIG.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment. For example, the frequency of the reference clock signal can be switched to three or more values, and the fifth switching signal φ5 may become a high level when the frequency becomes equal to or lower than a predetermined frequency. Further, the reference voltage may be switched to three or more reference voltages, power supply voltages, capacities, and current amounts according to the frequency of the reference clock signal. In the above description, the first integration circuit and the second integration circuit C1 and C2 are charged in the plus direction and discharged in the minus direction. However, they may be charged in the minus direction and discharged in the plus direction. . In the third to fifth embodiments, the threshold voltages inside the first NAND circuit NA1 and the third NAND circuit NA3 may be applied as the reference voltage Vref without providing the first comparison circuit 23 and the second comparison circuit 24. . Details of these circuit configurations are disclosed in detail in the prior application 1. Further, the positive input terminal and the negative input terminal of the first and second comparison circuits 23 and 24 may be reversed. That is, the reference voltage may be input to the positive input terminal and the voltage of the integration circuit may be input to the negative input terminal.

  The present invention can be suitably applied to a pulse width modulation circuit of an audio switching amplifier.

It is a block diagram which shows the structure of the switching amplifier by preferable embodiment of this invention. It is a block diagram which shows the structure of the pulse width modulation circuit 1 by preferable embodiment of this invention. It is a figure which shows the reference clock signal MCLK, 1st switching signal (phi) 1, and 2nd switching signal (phi) 2. 3 is a time chart showing the operation of the pulse width modulation circuit 1 when there is no signal. 6 is a time chart showing the operation of the pulse width modulation circuit 1 when the audio signal is positive. 6 is a time chart showing the operation of the pulse width modulation circuit 1 when the audio signal is negative. 6 is a diagram illustrating a voltage of the first integration circuit C1 when the frequency of the clock signal is changed in the pulse width modulation circuit 1. FIG. 2 is a block diagram showing a configuration of a pulse width modulation circuit 201 according to a preferred embodiment of the present invention. FIG. 6 is a diagram illustrating a voltage of the first integration circuit C1 when the frequency of the clock signal is changed in the pulse width modulation circuit 201. FIG. It is a block diagram which shows the structure of the pulse width modulation circuit 301 by preferable embodiment of this invention. FIG. 6 is a diagram illustrating a voltage of the first integration circuit C1 when the frequency of the clock signal is changed in the pulse width modulation circuit 301. It is a block diagram which shows the structure of the pulse width modulation circuit 401 by preferable embodiment of this invention. It is a block diagram which shows the structure of the pulse width modulation circuit 501 by preferable embodiment of this invention. FIG. 10 is a block diagram showing a configuration of a conventional pulse width modulation circuit 901. 6 is a diagram illustrating a voltage of the first integration circuit C1 when the frequency of the clock signal is changed in the pulse width modulation circuit 901. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pulse width modulation circuit 9 Clock frequency control part 10 Clock generation circuit 11 Dead time generation circuit 12 Falling edge detection circuit 13 Voltage current conversion circuit 14 Discharge bias current source 18 Reference voltage switching circuit 19 Reference voltage switching circuit 20 Power supply voltage switching Circuit 21 Power supply voltage switching circuit 22 Capacitance switching circuit 23 Capacitance switching circuit 24 Current switching circuit 27 Current control unit

Claims (7)

The voltage in the first integration circuit is changed in a first period which is a half cycle of a predetermined clock signal based on the current based on the input signal, and the first phase shifted from the first period by a half cycle based on a constant bias current. In the second period following one period, the voltage in the first integration circuit is changed in the direction opposite to the increase / decrease direction in the first period, and the second integration circuit is different from the first integration circuit based on the current based on the input signal. The voltage in the integration circuit is changed, and the voltage in the second integration circuit is increased or decreased in the second period in a third period following the second period that is shifted from the second period by a half cycle based on the bias current. A voltage control circuit to change in the reverse direction;
A first detection circuit for detecting a time from when the second period starts until the voltage in the first integration circuit reaches a predetermined reference voltage;
A second detection circuit that detects a time from when the third period starts until the voltage in the second integration circuit reaches a predetermined reference voltage;
A pulse signal generation circuit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection circuit and the second detection circuit every half cycle of the clock signal;
Frequency control means for switching the frequency of the clock signal to at least a first frequency and a second frequency that is lower than the first frequency;
When the frequency of the clock signal is the second frequency, the chargeable voltage of the first integration circuit and the second integration circuit is greater than the chargeable voltage when the frequency of the clock signal is the first frequency. Chargeable voltage switching means for switching to a value, a pulse width modulation circuit. The chargeable voltage is a difference between a power supply voltage and the reference voltage in the first detection circuit and the second detection circuit,
When the frequency of the clock signal is the second frequency, the chargeable voltage switching means switches the reference voltage to a value smaller than the reference voltage when the frequency of the clock signal is the first frequency. The pulse width modulation circuit according to claim 1, further comprising a voltage switching circuit. The chargeable voltage is a difference between a power supply voltage and the reference voltage in the first detection circuit and the second detection circuit,
The power supply voltage switching means switches the power supply voltage to a value larger than the power supply voltage when the frequency of the clock signal is the first frequency when the frequency of the clock signal is the second frequency. The pulse width modulation circuit according to claim 1, further comprising a voltage switching circuit. The voltage in the first integration circuit is changed in a first period which is a half cycle of a predetermined clock signal based on the current based on the input signal, and the first phase shifted from the first period by a half cycle based on a constant bias current. In the second period following one period, the voltage in the first integration circuit is changed in the direction opposite to the increase / decrease direction in the first period, and the second integration circuit is different from the first integration circuit based on the current based on the input signal. The voltage in the integration circuit is changed, and the voltage in the second integration circuit is increased or decreased in the second period in a third period following the second period that is shifted from the second period by a half cycle based on the bias current. A voltage control circuit to change in the reverse direction;
A first detection circuit for detecting a time from when the second period starts until the voltage in the first integration circuit reaches a predetermined reference voltage;
A second detection circuit that detects a time from when the third period starts until the voltage in the second integration circuit reaches a predetermined reference voltage;
A pulse signal generation circuit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection circuit and the second detection circuit every half cycle of the clock signal;
Frequency control means for switching the frequency of the clock signal to at least a first frequency and a second frequency that is lower than the first frequency;
When the frequency of the clock signal is the second frequency, the amount of voltage change during charging and discharging of the first integration circuit and the second integration circuit, and when the frequency of the clock signal is the first frequency And a voltage change amount switching means for making the voltage change amount smaller than the voltage change amount.   When the frequency of the clock signal is the second frequency, the voltage change amount switching means indicates the capacitance of the first integration circuit and the second integration circuit, and the frequency of the clock signal is the first frequency. The pulse width modulation circuit according to claim 4, further comprising a capacitance switching circuit for switching to a value larger than the capacitance.   When the frequency of the clock signal is the second frequency, the voltage change amount switching means indicates the current based on the input signal and the bias current, and the input signal when the frequency of the clock signal is the first frequency. The pulse width modulation circuit according to claim 4, further comprising: a current switching circuit that switches to a value smaller than each of the current based on the bias current and the bias current. The voltage in the first integration circuit is changed in a first period which is a half cycle of a predetermined clock signal based on the current based on the input signal, and the first phase shifted from the first period by a half cycle based on a constant bias current. In the second period following one period, the voltage in the first integration circuit is changed in the direction opposite to the increase / decrease direction in the first period, and the second integration circuit is different from the first integration circuit based on the current based on the input signal. The voltage in the integration circuit is changed, and the voltage in the second integration circuit is increased or decreased in the second period in a third period following the second period that is shifted from the second period by a half cycle based on the bias current. A voltage control circuit to change in the reverse direction;
A first detection circuit for detecting a time from when the second period starts until the voltage in the first integration circuit reaches a predetermined reference voltage;
A second detection circuit that detects a time from when the third period starts until the voltage in the second integration circuit reaches a predetermined reference voltage;
A pulse signal generation circuit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection circuit and the second detection circuit every half cycle of the clock signal;
Frequency control means for switching the frequency of the clock signal to at least a first frequency and a second frequency that is lower than the first frequency;
When the frequency of the clock signal is the second frequency, the maximum charge voltage of the first integration circuit and the second integration circuit when the input signal is no signal is expressed as the first integration circuit and the second integration. A pulse width modulation circuit comprising: setting means for setting the voltage to ½ or less of the chargeable voltage of the circuit.