JP4752829B2 - Pulse width modulation circuit and switching amplifier using the same - Google Patents

Description

  The present invention relates to a pulse width modulation circuit that outputs, for example, a pulse width modulation (PWM) of an audio signal and a switching amplifier (for example, an audio amplifier) using the same.

  2. Description of the Related Art Conventionally, switching amplifiers that use a pulse width modulation circuit (see, for example, Patent Document 1) that modulates an audio signal as an input signal and outputs the modulated signal have been proposed. In this switching amplifier, a predetermined power supply voltage is switched based on the modulation signal output from the pulse width modulation circuit, and the switched output signal is output to a load (for example, a speaker) through, for example, a low-pass filter.

JP 2004-320097 A

FIG. 7 is a configuration diagram illustrating an example of a conventional switching amplifier. This switching amplifier includes a pulse width modulation circuit 51 connected to the audio signal generation source AU, a switching circuit 52, and a low-pass filter circuit 53. According to this switching amplifier, the amplitude of the audio signal e _S output from the audio signal generation source AU is subjected to pulse width modulation in the pulse width modulation circuit 51, and the modulated signal OUT1 thus modulated is opposite in phase to the modulation signal OUT1. The modulation signal OUT2 is output to the switching circuit 52.

In the switching circuit 52, the positive and negative power supply voltages + V _D and −V _D are alternately switched by the switches SW-a and SW-b based on the modulation signals OUT1 and OUT2. A high frequency component is removed from the switched output by the low-pass filter circuit 53 and the output signal V ₀ is supplied to a load (not shown).

FIG. 8 is a circuit diagram showing a schematic configuration of the pulse width modulation circuit 51 shown in FIG. FIG. 9 is a timing chart showing voltage waveforms of signals of the pulse width modulation circuit 51 shown in FIG. The pulse width modulation circuit 51 generates and outputs a modulation signal OUT1 by pulse width modulating, for example, the audio signal e _S as an input signal. In this pulse width modulation circuit 51, two charging capacitors (described later) are alternately charged with a current based on the audio signal e _S , and a pulse width is generated by detecting the time when the capacitor is discharged with a constant discharge amount. is doing.

  As shown in FIG. 8, the pulse width modulation circuit 51 includes a clock generation circuit 54, a voltage / current conversion circuit 55, a discharge bias current source 56, first to fourth switches SW1 to SW4, and a charging capacitor. The first and second integration circuits C1 and C2, the first and second comparison circuits 57 and 58, the first and second reset circuits 59 and 60, and the signal output circuit 61 are configured.

In the pulse width modulation circuit 51, as shown in FIG. 9A, when the first switching signal φ1 from the clock generation circuit 54 is at a high level in the first period T1, the first switch SW1 is turned on. The current (Ic + Δi) corresponding to the sum of the audio signal e _S converted into the voltage-current in the voltage-current conversion circuit 55 and the charging bias current Ic generated by the charging bias current source (not shown) is the first integrating circuit C1. To be supplied. The first integration circuit C1 is charged by this current (Ic + Δi) until the first switch SW1 is turned off (see the waveform “a” in FIG. 9C).

  Next, when the first switching signal φ1 becomes low level and the second switching signal φ2 becomes high level in the second period T2 (see FIG. 9B), the first switch SW1 is turned off and the third switch SW3 is turned on. Turns on. As a result, the electric charge in the first integration circuit C1 flows to the discharge bias current source 56, and the first integration circuit C1 is discharged with a constant discharge amount (see waveform A).

  In this case, when the charging voltage in the first integration circuit C1 reaches the reference voltage Vref of the first comparison circuit 57, the output of the first comparison circuit 57 is inverted (refer to the waveform indicated by a dot in FIG. 9 (d)). The output of the AND circuit 62 of the reset circuit 59 is also inverted from the low level to the high level (see the waveform at point c in FIG. 9E). As a result, the fifth switch SW5 is turned on, whereby the charges discharged by the first integrating circuit C1 are discharged to the ground potential all at once through the fifth switch SW5.

  The output of the first comparison circuit 57 is output as a part of the pulse width modulation signal PWMout through the NAND circuit 64 of the signal output circuit 61. That is, the pulse width modulation signal PWMout is shifted to the second period T2 and the time from when the discharge of the first integration circuit C1 is started until the fifth switch SW5 is turned on and the first integration circuit C1 is discharged all at once. It is obtained by detecting t (refer to the point waveform in FIG. 9F).

  Also in the second integration circuit C2, since the same operation as that of the first integration circuit C1 is performed with a half cycle shift, the OR circuit 66 of the signal output circuit 61 generates the output of the first NOR circuit 64 and the output of the second NOR circuit 65. It is synthesized and output as a pulse width modulation signal PWMout (see waveform (e) in FIG. 9 (g)).

  FIG. 10 is a partially enlarged view of the waveform at point a in FIG. The alternate long and short dash line shown in FIG. 10 is an ideal waveform during operation, and the solid line is the waveform when an offset voltage described later occurs. The waveform shown in FIG. 10 shows the waveform in the first integration circuit C1, and hereinafter, the first integration circuit C1 will be described, but the same applies to the second integration circuit C2.

  According to the ideal operation waveform, the first integration circuit C1 is gradually charged from the reference potential (ground potential), and the maximum charge is obtained when the levels of the first and second switching signals φ1 and φ2 are switched. The voltage Va is reached, and then discharge is started. Then, when the charging voltage reaches the reference voltage Vref, the first integrating circuit C1 is discharged at once by the fifth switch SW5, and the charging voltage becomes the reference potential. Thereafter, when the levels of the first and second switching signals φ1 and φ2 are switched, charging of the first integrating circuit C1 is started again from the reference potential (0 [V]). In other words, in an ideal operation waveform, the new charge start voltage in the first integration circuit C1 is always 0 [V] of the reference potential.

  In the pulse width modulation circuit 51, as described above, the first and second integration circuits C1 and C2 are discharged by a constant amount, and the charging voltages of the first and second integration circuits C1 and C2 reach the reference voltage Vref, respectively. The pulse width modulation signal PWMout is generated based on the time t1 until the start.

  Here, if the charging period of the first integrating circuit C1 is T and the capacity of the first integrating circuit C1 is C, the maximum charging voltage Va is expressed by Equation 1.

  When the discharge bias current by the discharge bias current source 56 is set to Id and the charging bias current Ic of the voltage-current conversion circuit 55 is set to be equal to (3/2) Id, Formula 1 is transformed into Formula 2.

  If the time from when the discharge is started in the first integration circuit C1 until the charging voltage reaches the reference voltage Vref is t1, t1 is expressed by Equation 3.

  If the reference voltage Vref is set to be (2/3) Va and Va in Expression 2 is substituted, Expression 3 is transformed into Expression 4.

  Further, if the time from when the charging voltage of the first integrating circuit C1 reaches the reference voltage Vref until the next charging is started is t2, the modulation degree m in the pulse width modulation circuit 51 is expressed by Equation 5. be able to.

  Since the discharge period T of the first integration circuit is T = t1 + t2, if the formula 5 is modified based on this and the t1 of the formula 4 is substituted, the modulation degree m is expressed by the formula 6.

Thus, it can be seen that the modulation degree m is proportional to the magnitude Δi of the audio signal e _S.

  By the way, the fifth switch SW5 of the pulse width modulation circuit 51 is configured by a combination of elements such as MOSFETs. However, such a fifth switch SW5 normally generates an on-resistance when turned on from an off operation. .

When the on-resistance occurs, a current flows to the discharge bias current source 56 through the on-resistance, and an offset voltage ΔV (where ΔV is a negative voltage with respect to the reference potential) is generated by this current. Here, when the on-resistance is Ron, the voltage at the start of charging is represented by Id × Ron by the on-resistance Ron and the discharge current Id. In this case, if the on-resistance Ron varies, the voltage at the start of charging becomes Id × (Ron + ΔRon) (ΔRon indicates the variation of the on-resistance Ron), and the charging start voltage varies by the amount of Id × ΔRon. . Further, the time until the voltage at the start of charging is varied varies depending on the time constant between the on-resistance Ron and the first integration circuit C1.

  For example, as shown by the solid line in FIG. 10, when the offset voltage ΔV is generated at the start of a new charge of the first integrating circuit C1, the maximum charge voltage becomes Va ′ that is offset from the Va by the offset voltage ΔV, and the discharge is performed. It may occur that the time t1 from the start until the charging voltage reaches the reference voltage Vref is not properly detected (a time t1 ′ shorter than the time t1 is detected in FIG. 10), and as a result, the pulse width modulation signal PWMout Will be distorted. Further, when the internal temperature of a device such as a switching amplifier including the pulse width modulation circuit 51 rises during the operation of the pulse width modulation circuit 51, the change in temperature causes variation in the on-resistance, and the offset voltage ΔV is generated. .

  When the offset voltage ΔV is generated, the maximum charging voltage Va ′ = Va + ΔV is obtained, and t1 ′ in this case is expressed by Equation 7.

  Further, the modulation degree m ′ in this case is expressed by Equation 8.

  By transforming Equation 8 and substituting t1 ′ in Equation 7, the modulation degree m ′ is expressed by Equation 9.

  Comparing Equation 9 and Equation 6, as is apparent, in Equation 9, (2C / IdT) ΔV in the second term on the right side of the last row becomes noise and is superimposed on the pulse width modulation signal PWMout, resulting in distortion of the signal waveform. Cause.

  The present invention has been conceived under the circumstances described above, and an appropriate pulse width modulation signal can be output by suppressing an offset voltage when charging of the integration circuit is started. It is an object of the present invention to provide a pulse modulation circuit and a switching amplifier to which the pulse modulation circuit is applied.

  In order to solve the above problems, the present invention takes the following technical means.

The pulse width modulation circuit provided by the first aspect of the present invention comprises a clock signal generating means for generating a first clock signal and a second clock signal obtained by inverting the level of the first clock signal, A first charge accumulating means capable of accumulating; a second charge accumulating means capable of accumulating charges; a voltage-current converting means for converting an input signal inputted as a voltage into a current; and a constant current generating constant. During the high level period of the first clock signal, the current generation unit charges the first charge storage unit with the current output from the voltage-current conversion unit, and the second charge storage unit generates the constant current. The second charge storage means is charged with the current output from the voltage-current conversion means during the high level period of the second clock signal. Charge / discharge control means for controlling the charge storage means to discharge with a constant current output from the constant current generation means; and discharge with constant current from the constant current generation means during a low level period of the first clock signal. And a constant current from the constant current generating means in the low level period of the second clock signal, the first detecting means for detecting the timing at which the voltage of the first charge storage means changes to a predetermined reference voltage. Based on the second detection means for detecting the timing at which the voltage of the second charge storage means changes to the reference voltage by the discharge due to, the first clock signal and the detection signal of the first detection means, For each low level period of the first clock signal, the time from the start of each low level period to the time when the voltage of the first charge storage means reaches the reference voltage is pulsed. A low-level period of the second clock signal based on the first pulse signal generating means for generating the first pulse signal having a width, the second clock signal and the detection signal of the second detection means Second pulse signal generation means for generating a second pulse signal having a pulse width as a time from the start of each low level period to the time when the voltage of the second charge storage means reaches the reference voltage, A pulse width modulation circuit comprising: a pulse width modulation signal generating unit configured to combine the first pulse signal and the second pulse signal to generate a pulse width modulation signal of the input signal; The control means includes a first switch means comprising a semiconductor element connected in parallel to the first charge storage means, and a second switch means comprising a semiconductor element connected in parallel to the second charge storage means. And said After the voltage-current conversion means is connected to the first charge storage means at the timing when the level of the first clock signal becomes high level, the connection is released at the timing when the level becomes low level, and the second clock signal A first connection control means for releasing the connection at a timing when the voltage-current conversion means is connected to the second charge storage means at a timing when the level becomes a high level, and then at a timing when the level becomes a low level; After the constant current generating means is connected to the first charge storage means at the timing when the level of the clock signal becomes low level, the first clock signal is inverted to high level from the detection timing of the first detecting means. The connection is released at a predetermined timing until the level of the second clock signal becomes low, and the constant current generating means is Second connection control for releasing the connection at a predetermined timing from the detection timing of the second detection means to the inversion of the second clock signal to the high level after the connection to the second charge storage means And turning on the first switch means at the detection timing of the first detection means, then turning off the first switch means at a timing when the first clock signal is inverted to a high level, First switch control for turning off the second switch means at a timing when the second clock signal is inverted to a high level after turning on the second switch means at the detection timing of the second detection means. Means (claim 1).

According to this configuration, in the high-level period of the first clock signal, the first charge storage means the input signal (e.g. audio signal) in the voltage-current converted current by the voltage-current conversion means is charged. In the subsequent low level period, the accumulated charge of the first charge accumulating unit is discharged by the constant current generated by the constant current generating unit . On the other hand, in the high level period of the second clock signal (low level period of the first clock signal) , the second charge storage means is charged with the current output from the voltage-current conversion means , and in the subsequent low level period. the charge accumulated in the second charge storage means is discharged at a constant current generated by the constant current generation unit.

In the low-level period of the first clock signal, the timing at which the voltage of the first charge accumulation means is changed to a predetermined reference voltage is detected by the discharge by a constant current generation unit, the low-level period of the second clock signal the timing of the voltage of the second charge storage means is changed to a predetermined reference voltage by the discharge by constant current generation means is detected. Then, the time from the start of each low level period until the voltage of the first charge storage means reaches the reference voltage for each low level period of the first clock signal by the first pulse signal generation means is set as the pulse width. A first pulse signal is generated, and from the start of each low level period for each low level period of the second clock signal by the second pulse signal generation unit until the voltage of the second charge storage unit reaches the reference voltage A second pulse signal having the pulse width as the time of is generated.

In the low-level period of the first clock signal, based on a detection signal of the first detecting means, the first switching means connected to be on-the parallel to the first charge storage means, the charges accumulated in the first charge storing means is discharged all through the first switching means. After this discharge , the connection between the constant current generating means and the first charge storage means is released at a predetermined timing until the first clock signal is inverted to a high level . In the low-level period of the second clock signal, based on a detection signal of the second detecting means, the second switching means connected to be on-the parallel to the second charge storage means , charges accumulated in the second charge storage means is discharged all through the second switch means. After this discharge , the connection of the constant current generating means with the second charge storage means is released at a predetermined timing until the second clock signal is inverted to the high level .

First switching means, which is configured by a semiconductor device having an on-resistance, when the constant current generation means to the first clock signal is inverted to high level and is connected to the first charge storage means, When a constant current from the constant current generating means flows through the first switch means, a voltage drop occurs due to the on-resistance, and the first charge storage means is newly charged in the next high level period, the first offset voltage arising in the charge storage means. The same applies to the second switch means. Further, when the internal temperature of the switching amplifier including the pulse width modulation circuit rises during the operation of the pulse width modulation circuit, an offset voltage may be generated similarly. According to the present invention, after all the accumulated charges of the first and second charge accumulating means are discharged through the first and second switch means, the first and second clock signals are inverted to the high level. first constant current generating means at a predetermined timing, so the connection between the second charge storage means is released, when the first and second charge storage means is newly charged at the next high level period Generation of an offset voltage is suppressed. Therefore, new charging can be started from 0 [V], and an appropriate pulse width modulation signal can be output.

In the pulse width modulation circuit of the present invention, the first connection control means is provided between the voltage-current conversion means and the first charge storage means, and third switch means for opening and closing the connection between the two means. And a fourth switch means provided between the voltage-current conversion means and the second charge storage means for opening and closing the connection between the two means, and a timing at which the level of the first clock signal becomes high. After the third switch means is turned on, the third switch means is turned off at the timing when it becomes low level, and the fourth switch means at the timing when the level of the second clock signal becomes high level. Second switch control means for turning off the fourth switch means at a low level after turning on, the second connection control means comprising the constant current generation Provided between the stage and the first charge storage means, provided between the constant current generation means and the second charge storage means, a fifth switch means for opening and closing the connection of both means, The sixth switch means for opening and closing the connection of both means, and the detection timing of the first detection means after turning on the fifth switch means at the timing when the level of the first clock signal becomes low level The fifth switch means is turned off at a predetermined timing from when the first clock signal at the low level is inverted to the high level, and at the timing when the level of the second clock signal becomes the low level. After the switch means is turned on, the second timing signal is detected at a predetermined timing from the detection timing of the second detection means until the second clock signal at the low level is inverted to the high level. The switching means may comprise a third switch control means for turning off (claim 2).

The third switch control means turns off the fifth switch means at the detection timing of the first detection means, and turns off the sixth switch means at the detection timing of the second detection means. it may be (claim 3).

The first detection means is constituted by a first comparison circuit that compares the voltage of the first charge storage means with the reference voltage, and the second detection means is the second charge storage means. The third switch control means compares the second clock signal and the first output signal output from the first comparison circuit. Of the first logic circuit for controlling on / off of the first switch means based on the first NAND signal, the first clock signal, and the second clock signal. A second logical circuit that generates a second NAND signal with the comparator circuit and controls on / off of the second switch means based on the second NAND signal, The second switch control means includes the second clock signal and A third logical circuit for generating a first logical product signal with the first negative logical product signal and controlling on / off of the fifth switch means based on the first logical product signal; A second logical product signal of the first clock signal and the second negative logical product signal is generated, and on / off of the sixth switch means is controlled based on the second logical product signal. It is good to comprise with the 4th logic circuit (Claim 4).

The switching amplifier provided by the second aspect of the present invention includes a pulse width modulation circuit provided by the first aspect of the present invention, a voltage source that outputs a predetermined power supply voltage, and an output from the pulse width modulation circuit. based on the modulated signal, it is characterized by comprising a switching circuit for switching the predetermined power source voltage supplied from the voltage source (claim 5).

  According to this configuration, since this switching amplifier includes the pulse width modulation circuit provided by the first aspect of the present invention, the same effect as the pulse width modulation circuit provided by the first aspect can be obtained. Play.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a switching amplifier to which a pulse width modulation (PWM) circuit according to the present invention is applied. FIG. 2 is a block circuit diagram showing an embodiment of the pulse width modulation circuit shown in FIG. The switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, positive and negative power supply voltage + E _B, the first power supply 4 and supplies -E _B A second power source 5 is provided. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

The pulse width modulation circuit 1 generates and outputs a modulation signal PWMout by performing pulse width modulation on the audio signal e _S as an input signal output from the audio signal generation source AU. The modulation signal PWMout output from the pulse width modulation circuit 1 is input to the switching circuit 2.

In the switching circuit 2, the first power supply 4 and the second power supply 5 from the positive and negative supply voltages + E _B, is -E _B is supplied, on the basis of the modulation signal modulated PWMout, the supply voltage + E _B, -E _B are alternately Switched. That is, the switching circuit 2 includes a switching element SW-A that is turned on and off based on the modulation signal PWMout, an inverter 2a that inverts the phase of the modulation signal PWMout output from the pulse width modulation circuit 1, and the inverter 2a. Based on the modulation signal PWMout ′ obtained by inverting the modulation signal PWMout, the switch element SW-B is turned on and off, and the reverse current prevention diode D− is connected to both ends of the switch elements SW-A and SW-B. A and D-B.

The switch elements SW-A and SW-B are alternately turned on and off by the modulation signal PWMout and the inverted modulation signal PWMout ′, and the switched positive and negative power supply voltages + E _B and −E _B are low-pass filtered. Supply to circuit 3 and load RL.

The low-pass filter circuit 3 is configured by an LC circuit including a coil L ₀ and a capacitor C ₀ . The low-pass filter circuit 3 is a circuit that removes a high-frequency component of the output signal output from the switching circuit 2 and supplies it to the load RL, and has a cutoff frequency of 60 kHz, for example. In the low-pass filter circuit 3, the high-frequency components of the switched positive and negative power supply voltages + E _B and −E _B are removed, and the output is supplied to the load RL and is output from the load RL as sound.

  As shown in FIG. 2, the pulse width modulation circuit 1 includes a clock generation circuit 11, a voltage / current conversion circuit 12, a discharge bias current source 13, first to fourth switches SW1 to SW4, first and first switches. 2 integration circuits C1, C2, first and second comparison circuits 15, 16, first and second reset circuits 17, 18, first and second discharge control circuits 19, 20, and signal output circuit 21, It is constituted by.

  The clock generation circuit 11 is a circuit that generates first and second switching signals φ1 and φ2 for switching the first and second switches SW1 and SW2 based on the output of the clock signal generator 11a. The clock signal generator 11a outputs a first switching signal φ1 that is a clock signal having a duty ratio of approximately 50%. The output of the clock signal generator 11a is inverted by the NOT circuit 11b, and a second switching signal φ2 having an opposite phase relationship to the first switching signal φ1 is generated.

  Note that the clock generation circuit 11 may be provided outside the pulse width modulation circuit 1 and configured to supply a clock signal to the pulse width modulation circuit 1 from the outside. Further, a dead time generation circuit (not shown) may be provided at the subsequent stage of the clock generation circuit 11. The dead time generation circuit is a circuit that delays the time of level inversion of the first and second switching signals φ1 and φ2 by a predetermined time so that the output levels of the first and second switching signals φ1 and φ2 do not coincide at the same time.

In the following description, for convenience, In Fig. 3 and 4, the period during which the first switching signal φ1 first becomes the high level first period T1, the subsequent period of the second period of the low level T2, followed by The high level period is referred to as a third period T3.

Returning to FIG. 2, the voltage-current conversion circuit 12 is a circuit that performs voltage-current conversion on the audio signal e _S supplied from the audio signal generation source AU (see FIG. 1) to the pulse width modulation circuit 1. The voltage-current conversion circuit 12 has a charging bias current source (not shown), and is a circuit that charges the first and second integrating circuits C1 and C2. As will be described later, the voltage-current conversion circuit 12 is connected to the first and second integration circuits C1, C2 via the first and second switches SW1, 2, respectively. Is turned on , the first and second integration circuits C1 and C2 are charged, respectively.

Here, when the conversion conductance in the voltage-current conversion circuit 12 is Gm, the current Δi converted from the audio signal e _S by the voltage-current conversion circuit 12 can be expressed by Δi = Gm · e _S. If the charging bias current in the charging bias current source is Ic, the current supplied to the first and second integrating circuits C1 and C2 can be expressed as Ic + Gm · e _S = Ic + Δi. The magnitude of this current (Ic + Δi) depends on the positive and negative directions and the magnitude of the amplitude of the audio signal e _S.

The discharge bias current source 13 is connected to a negative power supply voltage [−V], and discharges the electric charge accumulated in the first or second integration circuit C1, C2 with a discharge bias current Ib that is a constant current. It is. That is, the discharge bias current source 13 is connected to the first and second integrating circuits C1 and C2 via the third and fourth switches SW3 and 4, respectively, as will be described later, and the third and fourth switches When SW3,4 is turned on, the charge accumulated in the first and second integration circuits C1, C2, Ru was discharged at a bias current I d.

First and second switches SW1, SW2 is a switch for controlling the charging of the first and second integration circuits C1, C2. The first and second switches SW1 and SW2 are turned on and off based on the first and second switching signals φ1 and φ2 output from the clock generation circuit 11. That is, as shown in FIG. 3A, the first switch SW1 is turned on when the first switching signal φ1 is at a high level, and is turned off when the first switching signal φ1 is at a low level. Further, as shown in FIG. 3B, the second switch SW2 is turned on when the second switching signal φ2 is at a high level, and is turned off when the second switching signal φ2 is at a low level.

The third and fourth switches SW3 and SW4 are for controlling the discharge of the charges accumulated in the first and second integrating circuits C1 and C2 using the discharge bias current Id supplied by the discharge bias current source 13. Switch . The third and fourth switches SW3 and SW4 are turned on and off based on control signals φ3 and φ4 from first and second discharge control circuits 19 and 20, which will be described later. That is, the third switch SW3 is turned on when the control signal φ3 is at a high level, and is turned off when the control signal φ3 is at a low level. The fourth switch SW4 is turned on when the control signal φ4 is at a high level and turned off when the control signal φ4 is at a low level. The control signals φ3 and φ4 are output from first and second AND circuits 19a and 20a described later of the first and second discharge control circuits 19 and 20, respectively.

Each of the first and second integrating circuits C1 and C2 is constituted by a charging capacitor, and accumulates electric charge by the current from the voltage / current conversion circuit 12, and releases the electric charge by a constant current from the discharging bias current source 13. is the circuitry that will be. Specifically, in the first integration circuit C1, in the first period T1, the first switch SW1 is turned on (the third switch SW3 is turned off at this time), whereby the current from the voltage-current conversion circuit 12 ( It is charged with Ic + Δi). Further, the first integration circuit C1 has the charge accumulated in the first integration circuit C1 by the third switch SW3 being turned on during this second period T2 (at this time, the first switch SW1 is turned off). Flows into the discharge bias current source 13 and is discharged.

  On the other hand, the second integration circuit C2 performs voltage-current conversion by turning on the second switch SW2 (at this time, turning off the fourth switch SW4) in the second period T2 during which the first integration circuit C1 is discharged. It is charged with the current (Ic + Δi) from the circuit 12. In addition, the second integration circuit C2 has the charge accumulated in the second integration circuit C2 by the fourth switch SW4 being turned on (in this case, the second switch SW2 is turned off) during the next third period T3. Flows into the discharge bias current source 13 and is discharged.

  As described above, in the first and second integration circuits C1 and C2, the unit period in which the levels of the first and second switching signals φ1 and φ2 are maintained (for example, the first period T1 or the second period T2 shown in FIG. 3). Every time, charging and discharging are performed alternately.

  Here, a circuit connection configuration relating to charging / discharging of the first and second integration circuits C1 and C2 will be described. The voltage-current conversion circuit 12 is connected to one end of each of the first and second switches SW1 and SW2, and the first The other end of the switch SW1 is connected to one end of the first integrating circuit C1 (see point A in FIG. 2), thereby forming a charging path for the first integrating circuit C1. The other end of the first integrating circuit C1 is connected to the ground potential. One end of the first integrating circuit C1 is also connected to one end of the third switch SW3, and the other end of the third switch SW3 is connected to the discharging bias current source 13, thereby causing the first integrating circuit C1 to A discharge path is formed.

  On the other hand, the other end of the second switch SW2 is connected to one end of the second integrating circuit C2 (see point A ′ in FIG. 2), thereby forming a charging path for the second integrating circuit C2. The other end of the second integration circuit C2 is connected to the ground potential. One end of the second integrating circuit C2 is also connected to one end of the fourth switch SW4, and the other end of the fourth switch SW4 is connected to the discharging bias current source 13, thereby allowing the second integrating circuit C2 to A discharge path is formed.

First and second comparator circuits 15 and 16, by compare a predetermined reference voltage Vref and the ratio of the voltage in the charging period of the first and second integration circuits C1, C2, the pulse of the pulse width modulated signal PWMout at its output It is a circuit for defining and outputting the width. When the first and second comparison circuits 15 and 16 are constituted by, for example, CMOS inverter elements, the reference voltage Vref corresponds to a threshold value defined by the high level and the low level of the CMOS inverter element. The threshold value is set to about ½ of the power supply voltage of the CMOS inverter element. For example, if the power supply voltage of the CMOS inverter element is about 5V, the reference voltage Vref is about 2.5V, which is half of that.

  The reference voltage Vref is input to the positive (+) side input terminals of the first and second comparison circuits 15 and 16, respectively, and the first and second integration circuits C1 and C2 are input to the negative (−) side input terminals. One end is connected to each other.

  The outputs of the first and second comparison circuits 15 and 16 (see the points B and B ′ in FIG. 2) are normally at a high level, and the voltages (first and second integration circuits C1 and C2) at the negative input terminals. When the charging voltage is higher than the reference voltage Vref, a low level signal is output from the output terminal.

  The first and second reset circuits 17 and 18 forcibly end the discharge in the first and second integration circuits C1 and C2 during the period in which the first and second integration circuits C1 and C2 are discharged, respectively ( Circuit for resetting). The first reset circuit 17 includes a first NAND circuit 17a, a first NOT circuit 17b, and a fifth switch SW5. The second reset circuit 18 includes a second NAND circuit 18a, a second NOT circuit 18b, and a sixth switch SW6.

  The first NAND circuit 17a has one input terminal connected to the output terminal of the first comparison circuit 15, the other input terminal connected to the clock generation circuit 11, and the second switching signal φ2 being input thereto. The output of the first NAND circuit 17a (see point C in FIG. 2) is connected to the input terminal of the first NOT circuit 17b, and the output of the first NOT circuit 17b (see point E in FIG. 2) is connected to the fifth switch SW5. The on / off operation of the fifth switch SW5 is controlled by the first NAND circuit 17a and the first NOT circuit 17b.

  On the other hand, one input terminal of the second NAND circuit 18a is connected to the output terminal of the second comparison circuit 16, the other input terminal is connected to the clock generation circuit 11, and the first switching signal φ1 is input. The output of the second NAND circuit 18a (see point C ′ in FIG. 2) is connected to the input terminal of the second NOT circuit 18b, and the output of the second NOT circuit 18b (see point E ′ in FIG. 2) is connected to the sixth switch SW6. Then, the ON / OFF operation of the sixth switch SW6 is controlled by the second NAND circuit 18a and the second NOT circuit 18b.

  The first and second discharge control circuits 19 and 20 include first and second AND circuits 19a and 20a, respectively. The first and second discharge control circuits 19 and 20 output control signals φ3 and φ4 to the third and fourth switches SW3 and SW4 to turn on and off the third and fourth switches SW3 and SW4. The discharging operation in the first and second integrating circuits C1 and C2 is controlled. Further, as will be described later, the first and second discharge control circuits 19 and 20 turn off the third and fourth switches SW3 and SW4 at a predetermined timing, whereby the fifth and sixth switches SW5 and SW6 are turned on. Prevent the occurrence of offset voltage due to on-resistance.

  The first AND circuit 19a has one input terminal connected to the output terminal of the first NAND circuit 17a, the other input terminal connected to the clock generation circuit 11, and the second switching signal φ2 being input thereto. The output of the first AND circuit 19a (see point D in FIG. 2) is connected to the third switch SW3, and the first AND circuit 19a calculates the logical product of the output of the first NAND circuit 17a and the second switching signal φ2. Thus, the on / off operation of the third switch SW3 is controlled.

  The second AND circuit 20a has one input terminal connected to the output terminal of the second NAND circuit 18a, the other input terminal connected to the clock generation circuit 11, and the first switching signal φ1 input thereto. The output of the second AND circuit 20a (see point D 'in FIG. 2) is connected to the fourth switch SW4, and the second AND circuit 20a calculates the logical product of the output of the second NAND circuit 18a and the first switching signal φ1. Thus, the on / off operation of the fourth switch SW4 is controlled.

  The signal output circuit 21 includes first and second NOR circuits 21a and 21b and an OR circuit 21c. The first NOR circuit 21a has one input terminal connected to the output terminal of the first comparison circuit 15 (see point B in FIG. 2), and the other input terminal connected to the clock generation circuit 11 to be connected to the first switching signal φ1. Is entered. On the other hand, the second NOR circuit 21b has one input terminal connected to the output terminal of the second comparison circuit 16 (see the point B 'in FIG. 2), and the other input terminal connected to the clock generation circuit 11 and the second NOR circuit 21b. A switching signal φ2 is input.

  The output terminal of the first NOR circuit 21a (see point F in FIG. 2) and the output terminal of the second NOR circuit 21b (see point F ′ in FIG. 2) are connected to each input terminal of the OR circuit 21c, and the output of the OR circuit 21c. The terminal (see point G in FIG. 2) is connected to the subsequent switching circuit 2 (see FIG. 1) as the pulse width modulation signal PWMout.

  The first NOR circuit 21a calculates a negative logical sum of the first switching signal φ1 and the output of the first comparison circuit 15 to start discharge of the first integration circuit C1. A high level is output at time t until the voltage reaches the reference voltage Vref. The second NOR circuit 21b calculates the negative logical sum of the second switching signal φ2 and the output of the second comparison circuit 16 to start the discharge by the second integration circuit C2, and then the second integration circuit C2 A high level is output at time t until the voltage reaches the reference voltage Vref.

  The OR circuit 21c calculates the logical sum of the outputs of the first and second NOR circuits 21a and 21b, and sets the outputs of the first and second NOR circuits 21a and 21b as one pulse width modulation signal PWMout to the switching circuit 2. Output.

3 and 4 are diagrams showing timing charts of the respective signals in the pulse width modulation circuit 1. FIG. 3 mainly shows the respective signals relating to the charge / discharge operation in the first integration circuit C1, and FIG. Each signal regarding the charge / discharge operation in the second integration circuit C2 is shown. 3 and 4 show the case where the audio signal e _S is no signal (G · e _S = 0).

  In the first period T1 in FIG. 3, the first switching signal φ1 from the clock generation circuit 11 is at the high level (the second switching signal φ2 is at the low level) (see FIG. 3A), thereby the first switch SW1. Is turned on (the third switch SW3 is turned off). Therefore, the current (Ic + Δi) from the current-voltage conversion circuit 12 is supplied to the first integration circuit C1, and the first integration circuit C1 is charged (see the waveform at point A in FIG. 3C).

  The slope indicated by the point A waveform when the first integrating circuit C1 is charged is proportional to the magnitude of the current (Ic + Δi) from the current-voltage conversion circuit 12. That is, when the current (Ic + Δi) is large, the slope shown in the A point waveform becomes steep, and when the current (Ic + Δi) is small, the slope shown in the A point waveform becomes gentle.

  In the first period T1, when the voltage resulting from charging of the first integration circuit C1 in the first comparison circuit 15 exceeds the reference voltage Vref, the output of the first comparison circuit 15 changes from the high level to the low level (FIG. 3). (See point B waveform in (d)). At this time, the output of the first comparison circuit 15 is input to the first NAND circuit 17a, but the output of the first NAND circuit 17a is maintained at the high level because the second switching signal φ2 is maintained at the low level. (Refer to the point C waveform in FIG. 3 (e)).

  Further, since the second switching signal φ2 is at a low level in the first period T1, the second switch SW2 is turned off and the fourth switch SW4 is turned on, so that the second integrating circuit C2 has the first period. The charge charged in the period T0 half a cycle before T1 flows to the discharge bias current source 13 and is discharged at a constant discharge amount (see waveform A ′ in FIG. 4C).

  The charging operation in the first integrating circuit C1 is continued until the level of the first switching signal φ1 is inverted, and when the first switching signal φ1 is inverted and becomes a low level (see the second period T2), the first switch SW1 is turned on. The off operation is performed, and the charging operation in the first integrating circuit C1 ends.

Therefore, the charging in the first integrating circuit C1 becomes maximum when the level of the first switching signal φ1 is inverted, and becomes the maximum charging voltage Va as shown in FIG. Note that the maximum charging voltage Va when the audio signal e _S is no signal is set as a circuit constant so as to be a value about twice the reference voltage Vref.

  Next, in the second period T2, the second switching signal φ2 changes from the low level to the high level. At this time, since the output of the first comparison circuit 15 and the second switching signal φ2 are input to the first NAND circuit 17a, the output of the first NAND circuit 17a remains at the high level (refer to the point C waveform). Since the output of the first NAND circuit 17a and the second switching signal φ2 are input to the first AND circuit 19a, the output of the first AND circuit 19a (control signal φ3) changes as the level of the second switching signal φ2 changes. Then, the level changes from the low level to the high level (see the waveform at point D in FIG. 3 (f)). The third switch SW3 is turned on by the control signal φ3.

  Due to the ON operation of the third switch SW3, the charge charged in the first integration circuit C1 in the first period T1 flows to the discharge bias current source 13 through the third switch SW3. In this case, since the discharge bias current Id is constant, the first integrating circuit C1 is discharged with a constant discharge amount (see waveform at point A).

  In the second period T2, when the charging voltage of the first integration circuit C1 falls below the reference voltage Vref in the first comparison circuit 15, the output of the first comparison circuit 19 changes from the low level to the high level (refer to the point B waveform). As a result, the output of the first NAND circuit 17a changes from the high level to the low level (see waveform at point C). The output of the first NAND circuit 17a is inverted by the first NOT circuit 17b, and this is output to the fifth switch SW5 as a reset signal (see waveform at point E in FIG. 3G).

  That is, the fifth switch SW5 changes from the off state to the on state, and the electric charge discharged from the first integrating circuit C1 to the discharging bias current source 13 flows to the ground terminal through the fifth switch SW5, forcibly and at once. Discharge occurs.

On the other hand, the output of the first AND circuit 19a is changed from the high level to the low level when the output of the first NAND circuit 17a is changed from the high level to the low level (refer to the waveform at the point C), whereby the third switch SW3 is turned off. It becomes operation. Since the discharge bias current source 13 is disconnected from the fifth switch SW5 by the off operation of the third switch SW3, the influence of the on-resistance due to the fifth switch SW5 can be suppressed.

That is, in the conventional configuration, since the discharge bias current source 13 is connected to the fifth switch SW5, a current flows toward the discharge bias current source 13 via the ON resistance of the fifth switch SW5. When charging is newly started in the first integration circuit C1, an offset voltage ΔV is generated in the first integration circuit C1, and the charge / discharge waveform (point A waveform) is distorted due to the influence of the offset voltage.

However, in the present embodiment, after the first integration circuit C1 is reset in the fifth switch SW5, since the third switch SW3 is by being off operation, the discharging bias current source 13 is disconnected from the fifth switch SW5 In the subsequent third period T3, the first switch SW1 is turned on by the first switching signal φ1 and charging is newly started in the first integration circuit C1 (see the waveform at point A). However, the first integration circuit The discharge current flowing from C1 to the fifth switch SW5 is zero, that is, the offset voltage ΔV is not generated in the first integrating circuit C1, and charging is started from the reference potential of 0 [V]. A modulated signal can be output.

  FIG. 5 is a diagram showing a charge / discharge waveform in the first integration circuit C1 when the present embodiment is applied. According to FIG. 5, the charging voltage of the first integration circuit C1 after the reset of the fifth switch SW5 is the reference potential of 0 [V]. Therefore, good pulse width modulation can be performed even when charging is newly started.

  Returning to FIG. 3, since the first switching signal φ1 and the output of the first comparison circuit 15 are input to the first NOR circuit 21a of the signal output circuit 21, the first NOR circuit 21a has the first NOR circuit 21a in the first period T1. A high level is output at a time t from when the integrating circuit 17 starts discharging until it is forcibly reset (see the waveform at point F in FIG. 3 (h)).

  Next, the charging / discharging operation in the second integrating circuit C2 will be described with reference to FIG. 4. In the second integrating circuit C2, charging / discharging is performed for a unit period (half cycle) as compared with the charging / discharging operation in the first integrating circuit C1. It differs in that the operation is shifted.

  That is, in the first integrating circuit C1, charging is started in the first period T1, and discharging is performed in the second period T2. In the second integrating circuit C2, charging is started in the second period T2, and in the third period T3. Discharge occurs. Thus, in the 1st integration circuit C1 and the 2nd integration circuit C2, charging / discharging operation | movement is performed by a half cycle shift.

  In the second integration circuit C2, when the second switch SW2 is turned on in the second period T2, the current (Ic + Δi) from the current-voltage conversion circuit 12 is supplied through the second switch SW2 and charged.

When the second switch SW2 is turned off and the fourth switch SW4 is turned on in the third period T3, the second integration circuit C2 is discharged, and the charging voltage of the second integration circuit C2 reaches the reference voltage Vref. The sixth switch SW6 is turned on by the reset signal, and the charge accumulated in the second integration circuit C2 is discharged at a stroke. Immediately thereafter, the fourth switch SW4 is turned off, so that the current due to the on-resistance of the sixth switch SW6 is prevented from flowing to the discharge bias current source 13. Therefore, similarly to the first integration circuit C1, when charging is newly started in the second integration circuit C2, the offset voltage ΔV in the second integration circuit C2 is suppressed, and an appropriate pulse width modulation signal can be output. it can.

  The first switching signal φ1 and the output of the second comparison circuit 20 are input to the second NOR circuit 21b of the signal output circuit 21, but the output of the second NOR circuit 21b maintains a low level (FIG. 4). (Refer to the F ′ point waveform in (h)). Accordingly, the output of the OR circuit 21c (see the waveform at point G in FIG. 4 (i)) is directly output as the pulse width modulation signal PWMout as the high level output from the first NOR circuit 21a.

  Thus, in the present embodiment, the third switch SW3 is turned on to discharge the charge accumulated in the first integrating circuit C1 with a constant discharge amount, and the fifth switch SW5 is turned on during the discharge. As a result, the first integrating circuit C1 is discharged at once and forcibly. Immediately thereafter, the third switch SW3 that has been turned on is turned off, so that the discharge path of the first integrating circuit C1 that reaches the discharge bias current source 13 via the third switch SW3 can be cut off. The offset voltage ΔV due to the ON resistance of the fifth switch SW5 can be suppressed, and an appropriate pulse width modulation signal PWMout can be output.

  Similarly, in the second integration circuit C2, the offset voltage ΔV due to the ON resistance of the sixth switch SW6 is suppressed, and an appropriate pulse width modulation signal PWMout can be output.

  In the above embodiment, the third switch SW3 is turned off almost simultaneously with the reset operation of the first integrating circuit C1 by the fifth switch SW5. However, the timing at which the third switch SW3 is turned off is the fifth switch SW3. Any time after the reset operation by SW5 and until a new charge is started (see period TA in FIG. 3) may be used. This is because the potential at one end of the first integration circuit C1 should be zero when charging is newly started in the first integration circuit C1.

  FIG. 6 is a diagram showing a pulse width modulation circuit 1A according to a modification of the pulse width modulation circuit 1 shown in FIG. In the pulse width modulation circuit 1 shown in FIG. 2, the first and second discharge control circuits 19 and 20 are configured by first and second AND circuits 19a and 20a, respectively. The circuit 19b and a NOT circuit 19c connected to the output of the circuit 19b may be used. The second discharge control circuit 20A may also be configured by a NAND circuit 20b and a NOT circuit 20c connected to the output thereof. This pulse width modulation circuit 1A also provides the same operational effects as the pulse width modulation circuit 1 shown in FIG.

  Of course, the scope of the present invention is not limited to the above-described embodiment, and the circuit configurations shown in the first and second embodiments are examples, and various circuits can be used as long as they have equivalent functions. Can be applied.

It is a block diagram showing a switching amplifier to which a pulse width modulation circuit according to the present invention is applied. FIG. 2 is a block circuit diagram illustrating an embodiment of the pulse width modulation circuit illustrated in FIG. 1. It is a timing chart which shows the voltage waveform of each signal, and is a figure which mainly shows the charging / discharging operation | movement in a 1st integration circuit. It is a timing chart which shows the voltage waveform of each signal, and is a figure which mainly shows the charging / discharging operation | movement in a 2nd integration circuit. It is a figure which shows the charging / discharging waveform in the integration circuit which concerns on this embodiment. FIG. 3 is a diagram showing a modification of the pulse width modulation circuit shown in FIG. 2. It is a block diagram which shows the switching amplifier with which the conventional pulse width modulation circuit is applied. It is a circuit diagram which shows the conventional pulse width modulation circuit. It is a timing chart which shows the voltage waveform of each signal in the conventional pulse width modulation circuit. It is a figure which shows the charging / discharging waveform in the conventional integration circuit.

DESCRIPTION OF SYMBOLS 1 Pulse width modulation circuit 2 Switching circuit 3 Low pass filter circuit 4 1st power supply 5 2nd power supply 11 Clock generation circuit 12 Voltage current conversion circuit 13 Bias current source 15 for discharge 1st comparison circuit 16 2nd comparison circuit 17 1st reset circuit 18 second reset circuit 19 first discharge control circuit 20 second discharge control circuit 21 signal output circuit C1 first integration circuit C2 second integration circuit e _S audio signal Ic charge bias current Id discharge bias current SW1 first switch SW2 second Switch SW3 third switch SW4 fourth switch SW5 fifth switch SW6 sixth switch T1 first period T2 second period T3 third period Vref reference voltage φ1 first switching signal φ2 second switching signal φ3 control signal φ4 control signal

Claims (5)

Clock signal generating means for generating a first clock signal and a second clock signal obtained by inverting the level of the first clock signal;
First charge storage means capable of storing charge;
A second charge accumulating means capable of accumulating charges;
Voltage-current conversion means for converting an input signal input by voltage into current;
A constant current generating means for generating a constant current;
During the high level period of the first clock signal, the first charge storage unit is charged with the current output from the voltage-current conversion unit, and the second charge storage unit is output from the constant current generation unit. Discharging with a constant current, charging the second charge storage means with a current output from the voltage-current conversion means during the high level period of the second clock signal, and generating the first charge storage means with the constant current Charge / discharge control means for controlling discharge at a constant current output from the means;
First detection means for detecting a timing at which the voltage of the first charge storage means changes to a predetermined reference voltage due to discharge by a constant current from the constant current generation means in a low level period of the first clock signal. When,
Second detection means for detecting a timing at which the voltage of the second charge storage means changes to the reference voltage due to discharge by a constant current from the constant current generation means in a low level period of the second clock signal; ,
Based on the first clock signal and the detection signal of the first detection means, the voltage of the first charge storage means from the start of each low level period for each low level period of the first clock signal. First pulse signal generation means for generating a first pulse signal having a pulse width as a time until the reference voltage is reached;
Based on the second clock signal and the detection signal of the second detection means, the voltage of the second charge storage means from the start of each low level period for each low level period of the second clock signal Second pulse signal generation means for generating a second pulse signal having a pulse width as a time until the reference voltage is reached;
Pulse width modulation signal generating means for combining the first pulse signal and the second pulse signal to generate a pulse width modulation signal of the input signal;
A pulse width modulation circuit comprising:
The charge / discharge control means includes
First switch means comprising a semiconductor element connected in parallel to the first charge storage means;
Second switch means comprising a semiconductor element connected in parallel to the second charge storage means;
After the voltage-current conversion means is connected to the first charge storage means at the timing when the level of the first clock signal becomes high, the connection is released at the timing when the level becomes low, and the second clock First connection control means for releasing the connection at a low level after connecting the voltage-current conversion means to the second charge storage means at a timing when the signal level becomes high;
After the constant current generating means is connected to the first charge storage means at a timing when the level of the first clock signal becomes low level, the first clock signal is detected from the detection timing of the first detecting means. After the connection is released at a predetermined timing until it is inverted to a high level, and the constant current generating means is connected to the second charge storage means at a timing when the level of the second clock signal becomes low level, Second connection control means for releasing the connection at a predetermined timing from the detection timing of the second detection means until the second clock signal is inverted to a high level;
After turning on the first switch means at the detection timing of the first detection means, the first switch means is turned off at the timing when the first clock signal is inverted to the high level, and the second switch means First switch control means for turning off the second switch means at a timing when the second clock signal is inverted to a high level after turning on the second switch means at the detection timing of the detection means;
The pulse width modulation circuit which comprises a. The first connection control means includes:
A third switch means provided between the voltage-current conversion means and the first charge storage means to open and close the connection between the two means;
A fourth switch means provided between the voltage-current conversion means and the second charge storage means, which opens and closes the connection between the two means;
After the third switch means is turned on at the timing when the level of the first clock signal becomes high level, the third switch means is turned off at the timing when the level becomes low level, and the second clock signal Second switch control means for turning off the fourth switch means at a low level after turning on the fourth switch means at a time when the level becomes a high level,
The second connection control means includes:
A fifth switch means provided between the constant current generating means and the first charge storage means, for opening and closing a connection between the two means;
A sixth switch means provided between the constant current generation means and the second charge storage means, and opens and closes a connection between the two means;
After turning on the fifth switch means at the timing when the level of the first clock signal becomes low level, the first clock signal at low level becomes high level from the detection timing of the first detection means. After the fifth switch means is turned off at a predetermined timing until inversion, and the sixth switch means is turned on at a timing when the level of the second clock signal becomes low level, the second detection means And third switch control means for turning off the sixth switch means at a predetermined timing from the detection timing of the means until the second clock signal at the low level is inverted to the high level,
The pulse width modulation circuit according to claim 1. The third switch control means includes:
The pulse width field according to claim 2 , wherein the fifth switch means is turned off at the detection timing of the first detection means, and the sixth switch means is turned off at the detection timing of the second detection means. Modulation circuit. The first detection means includes a first comparison circuit that compares the voltage of the first charge storage means and the reference voltage,
The second detection means includes a second comparison circuit that compares the voltage of the second charge storage means and the reference voltage,
The third switch control means includes:
A first NAND signal of the second clock signal and the output signal output from the first comparison circuit is generated, and the first switch means is configured to generate a first NAND signal based on the first NAND signal. A first logical circuit that controls on / off, a second negative logical product signal of the first clock signal and the second comparison circuit are generated, and based on the second negative logical product signal And a second logic circuit for controlling on / off of the second switch means,
The second switch control means includes:
A first logical product signal of the second clock signal and the first negative logical product signal is generated, and on / off of the fifth switch means is controlled based on the first logical product signal. A sixth logic circuit that generates a second logical product signal of the third logical circuit and the first clock signal and the second negative logical product signal, and the sixth switch means based on the second logical product signal; And a fourth logic circuit for controlling on / off of the
The pulse width modulation circuit according to claim 3. The pulse width modulation circuit according to any one of claims 1 to 4,
A voltage source that outputs a predetermined power supply voltage;
A switching circuit for switching a predetermined power supply voltage supplied from the voltage source based on a modulation signal output from the pulse width modulation circuit;
A switching amplifier characterized by comprising:

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