CN117491765A - Direct current detection circuit and electronic equipment suitable for class D amplifier - Google Patents

Abstract

The application discloses a direct current detection circuit and electronic equipment suitable for a class D amplifier, wherein a charging and discharging circuit is controlled to provide charging current for a capacitor so as to establish precharge voltage or provide discharging current required by capacitor discharging; the PWM signal processing circuit controls the charge-discharge circuit according to the duty ratio difference value of the first pulse width modulation signal and the second pulse width modulation signal; the reset circuit is connected between the charge-discharge node and the common terminal; the comparator compares the voltage of the charge-discharge node with a base reference voltage. The reset circuit is used for resetting the voltage of the charge-discharge node when the audio signal crosses the zero point when the input signal is a normal audio signal; or, when the input signal is a direct current signal, the reset operation is not performed; or, when the input signal is switched from the normal audio signal to the direct current signal, the reset operation is ended. The reset circuit is added in the embodiment of the application, so that erroneous judgment during normal audio signals and direct current switching is avoided, and the accuracy and reliability of the direct current detection circuit are improved.

Description

Direct current detection circuit and electronic equipment suitable for class D amplifier

Technical Field

The present disclosure relates to the field of electronic circuits, and in particular, to a dc detection circuit suitable for a class D amplifier and an electronic device.

Background

The core component responsible for making sound in the audio equipment is a loudspeaker, also called a loudspeaker, which is a transducer for converting an electric signal into an acoustic signal, is an indispensable member in a vehicle entertainment and audio system, and is usually driven to work by a high-efficiency class-D audio amplifier, and a plurality of protection detection circuits (short circuit, open circuit, direct current, overcurrent, clipping and the like) exist in the working process of the class-D audio amplifier driving the loudspeaker, so that the normal use of the loudspeaker is ensured; the D-class audio amplifier is subjected to direct current detection to judge whether the output voltage of the loudspeaker has direct current components or not, and the detection threshold is set to prevent the loudspeaker from being damaged due to overlarge direct current signals so as to protect the loudspeaker.

However, if the dc detection circuit fails or is abnormal, erroneous judgment may occur when the input signal is a normal audio signal or the input signal is switched from a normal audio signal to a dc signal, thereby reducing the reliability of the dc detection circuit.

Disclosure of Invention

Aiming at the problems in the prior art, the application provides a direct current detection circuit suitable for a class D amplifier and electronic equipment.

In a first aspect, embodiments of the present application provide a dc detection circuit suitable for a class D amplifier, where the class D amplifier generates a first pulse width modulation signal and a second pulse width modulation signal according to an input signal; the direct current detection circuit includes:

the capacitor is connected between the charge and discharge node and the common terminal; the charge-discharge circuit is connected with the charge-discharge node;

a PWM signal processing circuit configured to generate a first control signal dc_pwmn and a second control signal dc_pwmp according to a duty ratio difference between the first pulse width modulation signal and the second pulse width modulation signal, the first control signal dc_pwmn and the second control signal dc_pwmp controlling the charge and discharge circuit to supply the charge current or the discharge current to the charge and discharge node;

the reset circuit is connected between the charge and discharge node and the common terminal;

the comparator is used for comparing the voltage of the charge-discharge node with a base reference voltage and outputting a comparison result;

the reset circuit is used for executing a reset operation when the audio signal crosses zero when the input signal is a normal audio signal, wherein the reset operation is to reset the voltage of the charge-discharge node to the voltage of the common terminal; or, when the input signal is a direct current signal, not performing the reset operation; or, when the input signal is switched from the normal audio signal to the direct current signal, the reset operation is ended.

In a second aspect, embodiments of the present application provide an electronic device including a dc detection circuit as described above.

Compared with the prior art, the beneficial technical effects are achieved:

the direct current detection circuit provided by the embodiment of the application is provided with the reset circuit, and when an input signal is a normal audio signal, the reset operation is executed when the audio signal crosses the zero point; or, when the input signal is a direct current signal, the reset operation is not performed; or when the input signal is switched from the normal audio signal to the direct current signal, the reset operation is ended, so that the erroneous judgment of the direct current detection circuit can be avoided, and the reliability of the direct current detection circuit is ensured.

The direct current detection circuit provided by the embodiment of the application charges and discharges the charging and discharging node by the charging current and the reference current which are proportional to the battery voltage, and the charging time is determined by the PWM signal difference value generated by the class D amplifier loop, so that the direct current detection threshold value is prevented from being related to the battery voltage.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a typical class D loop architecture for a class D audio amplifier;

FIG. 2 is a circuit diagram of a prior art DC detection circuit;

FIG. 3 is a signal timing diagram of the DC detection circuit shown in FIG. 2;

fig. 4 is a schematic diagram of a dc detection circuit according to a first embodiment of the present disclosure;

fig. 5 is a schematic diagram of a reset signal generating circuit in a dc detection circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a reset signal generating circuit in a dc detection circuit according to a second embodiment of the present disclosure;

fig. 7 is a schematic diagram of a first current source circuit in a dc detection circuit according to a third embodiment of the present disclosure;

fig. 8 is a schematic diagram of a second current source circuit in the dc detection circuit according to the third embodiment of the present application;

fig. 9 is a normal audio signal timing sequence of the reset circuit in the dc detection circuit according to the first embodiment of the present application;

fig. 10 is a timing diagram of a reset circuit DC signal (DC signal) in the DC detection circuit according to the first embodiment of the present application;

reference numerals:

the circuit comprises a 1-direct current detection circuit, a 11-charge-discharge circuit, a 12-PWM signal processing circuit, a 13-reset circuit, a 14-comparator, a 15-first timer, a 101-first current mirror circuit, a 102-second current mirror circuit, a 111-first current source circuit, a 112-second current source circuit, a 131-transistor, a 132-reset signal generation circuit, a 1301-first reset logic unit, a 1302-second reset logic unit, a 1303-third reset logic unit, a 201-first NOT gate, a 202-second NOT gate, a 203-third NOT gate, a 204-fourth NOT gate, a 205-fifth NOT gate, a 206-sixth NOT gate, a 207-seventh NOT gate, a 208-eighth NOT gate, a 301-first NOT gate, a 302-second NOT gate, a 303-third NOT gate, a 304-fourth NOT gate, a 305-fifth NOT gate, a 401-first NOT gate, a 501-first trigger, a 502-second trigger and a 503-third trigger.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. The terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion. Since the source and drain of the transistor used in the present application are symmetrical, the source and drain can be interchanged. The middle terminal of the transistor is defined as the gate, the signal input terminal is the source, and the output terminal is the drain according to the form in the figure.

It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

The following disclosure provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not in themselves indicate the relationship between the various embodiments and/or arrangements discussed.

Fig. 1 is a typical class D loop architecture for a class D audio amplifier, the class D loop referring to a feedback loop for controlling the class D audio amplifier. The class D audio amplifier shown in fig. 1 includes an input amplifier, an integrator, a comparator, a logic control module, and a driving module. The class D audio amplifier is powered by a single power supply, and the high and low levels of pulse output signals SPKP and SPKN are respectively composed of battery voltage VBAT, ground GND, INT1 and an operational amplifier INT 2. When the class D audio amplifier works, an audio input signal VIN generates signals INT2_OUTP and INT2_OUTN through an integrator, the signals are modulated through a triangular wave carrier signal VRAMP, a first pulse width modulation signal PWMP and a second pulse width modulation signal PWMN are generated, and two paths of pulse signals SPKP and SPKN are output through a logic control and driving module to drive a loudspeaker to sound.

In the prior art, fig. 2 is a circuit diagram of a DC detection circuit in the prior art, and as shown in fig. 2, pulse width modulation signals PWMP and PWMN output from a PWM modulation comparator of a class D amplifier are compared with a reference signal pwm_ref (PWM reference signal representing a DC component), and a DC (DC) detection judgment signal is output by an or gate and a timer with a lock function. As shown in fig. 1, the pulse width modulation signal PWMP and the pulse width modulation signal PWMN are generated by modulating an analog audio signal output from the integrator with a triangular wave.

FIG. 3 is a signal timing diagram of the DC detection circuit shown in FIG. 2; as shown in fig. 3, PWMP and PWMN are equal and 50% duty cycle signal (regardless of mismatch) when no signal is input; when an input signal exists, the duty ratio of the pulse width modulation signal PWMP and the pulse width modulation signal PWMN is increased, otherwise, the duty ratio of the other signal PWMP and the pulse width modulation signal PWMN is decreased; when a normal audio signal is input, the duty ratio of the pulse width modulation signal PWMP and the pulse width modulation signal PWMN are alternately changed; when the direct current signal is input, the duty ratio of the pulse width modulation signal PWMP and the pulse width modulation signal PWMN is kept fixed, one end is large, the other end is small, when the duty ratio of the reference signal pwm_ref is set to 55%, as long as the duty ratio of any one end of the pulse width modulation signal PWMP or the pulse width modulation signal PWMN exceeds 55%, the RESET signal will become high, the timer with the locking function is started, when the timer exceeds the set time, the dc_detect output is high, the direct current input is judged to be larger than the judging threshold, and at the moment, the system will turn off the class D amplifier to protect the loudspeaker.

However, by adopting the direct current detection mode, the accuracy and reliability of the direct current detection circuit may be affected by erroneous detection judgment during normal audio signals and direct current switching. The frequency range of the normal audio signal referred to in this application is typically 20Hz to 20,000Hz, which range is referred to as the human hearing range. Frequencies below 20Hz are referred to as infrasonic waves, and frequencies above 20,000Hz are referred to as ultrasonic waves. The abnormal audio signal includes ultrasonic waves (higher than 20,000 Hz) or infrasonic waves (lower than 20 Hz).

Example 1

In order to solve the technical problem that the current dc detection circuit may misjudge, the first embodiment of the present application provides a dc detection circuit 1 suitable for a D-class amplifier, where the D-class amplifier is configured to generate a first pulse width modulation signal PWMP and a second pulse width modulation signal PWMN to drive a speaker to sound.

As shown in fig. 4, the direct current detection circuit 1 includes a capacitor C1, a charge-discharge circuit 11, a PWM signal processing circuit 12, a reset circuit 13, and a comparator 14.

The capacitor C1 is connected between the charge-discharge node B and the common terminal VSS, and the charge-discharge node B is used for controlling charge and discharge of the capacitor C1; the charge-discharge circuit 11 is connected with the charge-discharge node B and is used for receiving a charge current I1 for charging the capacitor C1 or a discharge current I2 required by discharging the capacitor C1; the PWM signal processing circuit 12 is configured to generate a first control signal dc_pwmn and a second control signal dc_pwmp according to a duty ratio difference between the first pulse width modulation signal PWMP and the second pulse width modulation signal PWMN, and control the charge/discharge circuit 11 to supply a charge current to the capacitor or a discharge current required for discharging the capacitor; the reset circuit 13 is connected between the charge-discharge node and the common terminal VSS; the comparator 14 compares the voltage vccharge of the charge-discharge node B with the base reference voltage vth_dc, and outputs a comparison result. Wherein, the reset circuit 13 is used for executing a reset operation when the audio signal crosses zero when the input signal is a normal audio signal, and the reset operation is to reset the voltage of the charge-discharge node to the voltage of the common terminal VSS; or, when the input signal is a direct current signal, the reset operation is not performed; or, when the input signal is switched from the normal audio signal to the direct current signal, the reset operation is ended.

The common VSS (Voltage Source Ground), which is referred to as a common ground pin or common ground node in the circuit, is commonly used as a reference site for the circuit and serves to provide a stable potential reference to ensure that the potential difference between the various parts of the circuit is properly measured and controlled. It is typically connected to the negative pole of the power supply as a common place for the various parts of the circuit. The common terminal VSS may also be used to connect loads in circuits, signal grounds, and elsewhere. It is noted that the common terminal VSS is not necessarily the actual ground (ground is typically the actual physical ground), but is a reference point defined in the circuit.

In this embodiment, the reset circuit 13 includes a transistor 131, a gate of the transistor 131 is connected to a detection reset signal, and a drain and a source of the transistor 131 are connected in series between the charge and discharge node and the common terminal.

As an example, the direct current detection 1 circuit further includes a reset signal generation circuit 132, and the detection reset signal is generated by the reset signal generation circuit 132. The reset signal generation circuit 132 includes a first reset logic unit 1301, a second reset logic unit 1302, and a third reset logic unit 1303. The first reset logic unit 1301 is configured to generate reset signals of the first flip-flop 501 and the second flip-flop 502 according to the enable signal and signals output by the first flip-flop 501 and the second flip-flop 502; a second reset logic unit 1302, configured to generate clock signals of the first flip-flop 501 and the second flip-flop 502 according to duty ratios of an inverse signal of the first pulse width modulation signal and an inverse signal of the second pulse width modulation signal, and output states of input terminals of the first flip-flop 501 and the second flip-flop 502 to output terminals when clock edges of the clock signals arrive, respectively; the second reset logic 1302 is further configured to generate a clock signal of the third flip-flop 503 according to the output signals of the first flip-flop 501 and the second flip-flop 502; the third reset logic unit 1303 is configured to generate a reset signal of the third flip-flop 503 according to the clock signal of the class D amplifier and an inverse of the enable signal, and the third flip-flop 503 outputs the detection reset signal.

As shown in fig. 5, the reset signal generating circuit 132 in the dc detection circuit provided in the first embodiment of the present application includes a first not gate 201, a second not gate 202, a third not gate 203, a fourth not gate 204, a fifth not gate 205, a sixth not gate 206, a seventh not gate 207, an eighth not gate 208, a first not gate 301, a second not gate 302, a third not gate 303, a fourth not gate 304, a fifth not gate 305, a first not gate 401, a first flip-flop 501, a second flip-flop 502, and a third flip-flop 503.

The input end of the second NOT gate 202 is connected to the inverse signal PWMP_B of the first pulse width modulation signal PWMP, and the input end of the third NOT gate 203 is connected to the inverse signal PWMN_B of the second pulse width modulation signal PWMN; the output of the second not gate 202 and the inverse signal pwmn_b of the second pwm signal PWMN are connected to the two inputs of the second nand gate 302, and the output of the third not gate 203 and the inverse signal pwmp_b of the first pwm signal PWMP are connected to the two inputs of the third nand gate 303.

The output signal of the second nand gate 302 is connected to the input end of the fourth nand gate 204, and the output end of the third nand gate 303 is connected to the input end of the fifth nand gate; the output terminal of the fourth not gate 204 is connected to the clock terminal of the first flip-flop 501, and the output terminal of the fifth not gate 205 is connected to the clock terminal of the second flip-flop 502.

The input end of the first trigger 501 and the input end of the second trigger 502 are both connected with a high level, the forward output end of the first trigger 501 and the forward output end of the second trigger 502 are respectively connected with two input ends of the fourth NAND gate 304, the output end of the fourth NAND gate 304 is connected with the clock end of the third trigger 503 after passing through the fifth NAND gate 205, and the input end of the third trigger 503 is connected with a high level.

One input end of the first NAND gate 301 is connected with an enable signal, the other input end of the first NAND gate 301 is connected with the output end of the fourth NAND gate 304, the output end of the first NAND gate 301 is connected with the input end of the first NAND gate 201, and the output end of the first NAND gate 201 is connected with the reset end of the first trigger 501 and the reset end of the second trigger 502.

The input end of the seventh NOT gate 207 is connected to a clock signal (PWM_CLK) of the class D loop, and is connected to one input end of the fifth NOT gate 305, the output end of the seventh NOT gate 207 is connected to the other input end of the fifth NOT gate 305, the output end of the fifth NOT gate 305 is connected to one input end of the first NOT gate 401 after passing through the eighth NOT gate 208, the other input end of the first NOT gate 401 is connected to an inverse signal of an enable signal, the output end of the first NOT gate 401 is connected to a reset end of the third trigger 503, the input end of the third trigger 503 is connected to a high level, and the output end of the third trigger 503 outputs a detection reset signal.

In some embodiments, the dc detection circuit 1 further includes a first timer 15, the comparator 14 (COMP) outputs to the first timer 15, and when the comparator 14 outputs high, the first timer 15 with the lock function counts time, and the audio signal is at least 20Hz, so the set value of the first timer 15 needs to be at least greater than 50ms. Only when the time when the output voltage of the comparator COMP exceeds the time threshold counted by the first timer 15, the output dc_detect of the first timer 15 is locked high, and the class D amplifier is judged to be outputting a DC signal at this time. The first timer 15 output DC DETECT is locked high and the first timer 15 triggers a protection mechanism, such as turning off the power amplifier (class D amplifier) output or otherwise reducing the DC bias, ensuring that the DC bias does not last too long, thereby protecting the speaker and power amplifier from potential damage. It provides a mechanism to monitor and respond to dc bias to ensure proper operation of the power amplifier and safety of the speaker.

The DC detection circuit 1 provided in this embodiment can be applied to an audio class d power amplifier to implement a DC detection function, and maintains the precharge voltage VX of the precharge node a equal to the voltage vcharg of the charge-discharge node B when the first control signal dc_pwmn is asserted, and establishes the precharge voltage VX by using the charge voltage when the second control signal dc_pwmp is asserted, thereby improving the charge efficiency. In some embodiments, the first timer 15 with locking function is added after the comparator 14, and the first timer 15 is locked for more than 50ms, so that false overturn can be avoided.

Example two

A schematic diagram of the reset signal generating circuit 132 in the dc detection circuit provided in the second embodiment of the present application is shown in fig. 6. Unlike the reset signal generation circuit 132 shown in fig. 5, a fourth flip-flop 504 is also included in the present embodiment. The clock signal (pwm_clk) of the class d loop is connected to the clock terminal of the fourth flip-flop 504, the input terminal of the fourth flip-flop 504 is connected to the inverting output terminal, and the forward output terminal is connected to the seventh not gate 207. The phase delay or timing control of the clock signal may be implemented using an inverting D flip-flop through the fourth flip-flop 504.

In the RESET signal generation circuit 132, the first RESET logic unit 1301 is the RESET logic of the first flip-flop 501 (dff 1) and the second flip-flop 502 (dff 2), and avoids that the output detection RESET signal RESET is always locked high when the normal audio signal is switched to the DC signal; the second reset logic unit 1302 is a main body portion of the reset signal generating circuit 132, and by detecting the duty ratios of the pwmp_b and pwmn_b signals, the first to third flip-flops 501 to 503 behave differently when normal audio signals and DC signals are input, and will be described specifically with reference to the following reset principle.

The third reset logic unit 1303 is a reset logic of the third flip-flop 503 of the second reset logic unit 1302 in the reset signal generating circuit 132, and periodically generates the reset signal dff3_rst of the third flip-flop 503 by using the clock pwm_clk of the switching frequency.

Description of reset principle: the embodiment of the application proposes the reset logic of the voltage VCHARGE of the charge-discharge node B, as shown in fig. 5. When a normal audio signal is input, the timing is shown in fig. 9, the voltage vccharge of the charge-discharge node B is briefly RESET at the zero crossing point of the normal audio signal, that is, the voltage vccharge of the charge-discharge node B is RESET to the voltage of the common terminal VSS, specifically, near the zero crossing point of the audio signal, the clock port dff3_ck of the third flip-flop 503 is hopped low to high, and then is RESET by dff3_rst (generated by the switching frequency of the classD loop) of the RESET port of the third flip-flop 503, so that a pulse width which is briefly high is generated, so that the detected RESET signal RESET output by the third flip-flop 503 appears as a pulse width which is high, and the output of the comparator 14 (COMP) becomes 0, which also serves as a RESET for the first timer 15. When a direct current signal is input, the timing is as shown in fig. 10, and since the duty ratio of pwmp_b or pwmn_b is always larger at one end than at the other end, the clock port dff3_ck of the third flip-flop 503 is kept at a low level, so the detection RESET signal RESET output by the third flip-flop 503 does not work. When the input signal is switched from the normal audio signal to the dc signal, the RESET signal RESET is not always high due to the RESET of the third flip-flop 503, i.e., the RESET operation is exited, so that the dc signal is normally detected. The RESET logic has the RESET function of resetting the normal audio signal, so that erroneous judgment is avoided, and the detection reliability is improved.

As shown in fig. 4, the charge-discharge circuit 11 includes a first current mirror circuit 101, a first switch S1, a second switch S2, and a second current mirror circuit 102. The first current mirror circuit 101 is configured to supply a charging current I1 to the capacitor C1; the first switch S1 is connected with the first current mirror circuit 101 in series, and the first switch S1 is also connected with the charge-discharge node B; the second switch S2 is connected with the first current mirror circuit 101 in series, and the second switch S2 is also connected with the charge-discharge node B; the second current mirror circuit 102 is connected to the charge-discharge node B to provide a discharge current I2 to discharge from the capacitor C1.

In this embodiment, the second switch S2 is electrically connected to the charge-discharge node B through the operational amplifier AMP; the inverting input terminal of the operational amplifier AMP is connected to the second switch S2, the output terminal of the operational amplifier AMP is connected to the inverting input terminal, and the non-inverting input terminal of the operational amplifier AMP is connected to the charge-discharge node B. The operational amplifier AMP with unity gain is used to clamp the precharge voltage VX to be equal to the voltage vccharge of the charge-discharge node B when the charge-discharge circuit 11 is not charging the capacitor C1, so as to ensure the establishment of the charge voltage at the next charge, thereby improving the charge efficiency.

In this embodiment, the charging current source i_charge that mirrors the charging current I1 is generated by the battery voltage VBAT, and the charging current I1 is related to the battery voltage VBAT, if the charging current is a dc input signal, the influence of the battery voltage VBAT is just counteracted. As shown in fig. 4, the first current mirror circuit 101 includes a first current source circuit 111, and the second current mirror circuit 102 includes a second current source circuit 112.

Example III

As an example, on the basis of the above embodiment, in the third embodiment, the first current source circuit 111 is shown in fig. 7, and the second current source circuit 112 is shown in fig. 8. As shown in fig. 7, the charging mirrored current source i_charge in the first current source circuit 111 is generated by dividing the battery voltage VBAT by the first resistor R1 and the second resistor R2; the first current source circuit 111 provides a charge image current source i_charge proportional to the battery voltage VBAT, and/or; the second current source circuit 112 provides a discharge image current source i_discharge based on the reference voltage VREF.

I1＝M*I_charge；

I2＝N*I_charge；

Where VREF is a reference voltage, M is a current mirror coefficient of the first transistor M1 and the second transistor M2 in fig. 4, N is a current mirror coefficient of the third transistor M3 and the fourth transistor M4 in fig. 4, D is duty ratio difference information of the sampled first pulse width modulation signal PWMP and the sampled second pulse width modulation signal PWMN, T is a switching period of the class D loop, and VDC is an output dc voltage threshold of the preset class D loop.

In the above example, the baseline reference voltage vth_dc may be set according to a preset DC voltage threshold VDC of the classD loop output.

As can be seen from the above deduction, in the DC detection circuit 1 provided in the third embodiment, when the battery voltage VBAT changes, the DC voltage threshold VDC required for the voltage VCHARGE of the charge-discharge node B to reach the reference voltage vth_dc does not change. The first current source circuit 111 and the second current source circuit 112 provided by the embodiment of the application avoid the influence of the battery voltage VBAT on the direct current detection of the class D power amplifier, the vehicle-mounted battery voltage variation range is large, the application scene is many, and the method is suitable for the direct current detection of the vehicle-mounted audio power amplifier.

In the embodiment of the present application, the first switch S1 and the second switch S2 are P-type transistors; the gate of the first switch S1 is connected to the second control signal dc_pwmp, and the gate of the second switch S2 is connected to the first control signal dc_pwmn. The PWM signal processing circuit 12 controls on or off of the first switch S1 and the second switch S2 in the charge-discharge circuit 11.

In a specific embodiment, the first pwm signal PWMP and the second pwm signal PWMN are subjected to level conversion and then logic operation to obtain the first control signal dc_pwmn and the second control signal dc_pwmp.

In the present embodiment, as shown in fig. 4, the PWM signal processing circuit 12 includes an exclusive or gate and an nor gate; the two input ends of the exclusive-or gate respectively input an inverse signal PWMP_B of the first pulse width modulation signal PWMP and an inverse signal PWMN_B of the second pulse width modulation signal PWMN, and the output end of the exclusive-or gate outputs a first control signal DC_PWMN; the input terminal of the not gate inputs the first control signal dc_pwmn, and the output terminal of the not gate outputs the second control signal dc_pwmp.

In this embodiment, the difference between the first pwm signal PWMP and the second pwm signal PWMN is sampled by the exclusive or gate to obtain the first control signal dc_pwmn and the second control signal dc_pwmp, where pwmp_b is the inverse direction of the first pwm signal PWMP output by the pwm comparator in the class d loop, and pwmn_b is the inverse direction of the first pwm signal PWMN. The capacitor C1 connected to the charge-discharge node B is controlled to be charged and discharged by the first control signal dc_pwmn and the second control signal dc_pwmp, the charge current is I1, and the discharge current is I2.

In fig. 4, the discharging current I2 is always present to always discharge the voltage vccharge of the charging and discharging node B, and the charging time of the charging current I1 to the voltage vccharge of the charging and discharging node B is determined by the first control signal dc_pwmn and the second control signal dc_pwmp. When the second control signal dc_pwmp is low and the first control signal dc_pwmn is high, i.e. the first switch S1 is turned on and the second switch S2 is turned off, charging the charge-discharge node B; when the second control signal dc_pwmp is high and the first control signal dc_pwmn is low, that is, the second switch S2 is turned on and the first switch S1 is turned off, the charging and discharging node B is not charged, and at this time, the precharge voltage VX of the precharge node a is clamped by the unit gain op AMP, so as to ensure the establishment of the next charging. The comparator 14 includes a comparator COMP that compares the voltage VCHARGE of the charge-discharge node B with the reference voltage vth_dc, and when the voltage VCHARGE of the charge-discharge node B is greater than the reference voltage vth_dc, the comparator COMP outputs high.

In the dc detection circuit 1 provided in this embodiment, the charging current I1 is generated by the charging current source i_charge proportional to the battery voltage VBAT, the discharging current I2 is generated according to the reference voltage VREF, so as to charge and discharge the charging node B, and the charging time is determined by the PWM signal difference generated by the class d loop, so that the dc detection threshold is prevented from being related to the battery voltage.

The embodiment of the application also provides electronic equipment, which comprises the direct current detection circuit 1 provided by any one of the possible implementations.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the present description, which falls within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.

Claims (10)

1. The direct current detection circuit is suitable for a class-D amplifier, and is characterized in that the class-D amplifier generates a first pulse width modulation signal and a second pulse width modulation signal according to an input signal; the direct current detection circuit includes:

the capacitor is connected between the charge and discharge node and the common terminal;

a charge-discharge circuit (11), wherein the charge-discharge circuit (11) is connected with the charge-discharge node;

a PWM signal processing circuit (12), where the PWM signal processing circuit (12) is configured to generate a first control signal and a second control signal according to a duty ratio difference between the first pulse width modulation signal and the second pulse width modulation signal, and the first control signal and the second control signal control the charge/discharge circuit (11) to provide a charge current or a discharge current to the charge/discharge node;

the reset circuit (13) is connected between the charge and discharge node and the common terminal;

a comparator (14), wherein the comparator (14) is used for comparing the voltage of the charge-discharge node with a base reference voltage and outputting a comparison result;

the reset circuit (13) is used for executing a reset operation when the audio signal crosses zero when the input signal is a normal audio signal, wherein the reset operation is to reset the voltage of the charge-discharge node to the voltage of the common terminal; or, when the input signal is a direct current signal, not performing the reset operation; or, when the input signal is switched from the normal audio signal to the direct current signal, ending the reset operation.

2. The direct current detection circuit according to claim 1, wherein the reset circuit (13) comprises a transistor (131), a gate of the transistor (131) is connected to a detection reset signal, and a drain and a source of the transistor (131) are connected in series between the charge and discharge node and the common terminal.

3. The direct current detection circuit according to claim 2, further comprising a reset signal generation circuit (132), the detection reset signal being generated by the reset signal generation circuit (132);

the reset signal generation circuit (132) comprises a first reset logic unit (1301), a second reset logic unit (1302) and a third reset logic unit (1303);

the first reset logic unit (1301) is configured to generate reset signals of the first flip-flop (501) and the second flip-flop (502) according to an enable signal and signals output by the first flip-flop (501) and the second flip-flop (502);

the second reset logic unit (1302) is configured to generate clock signals of the first flip-flop (501) and the second flip-flop (502) according to duty ratios of inverse signals of the first pulse width modulation signal and inverse signals of the second pulse width modulation signal, and output states of input terminals of the first flip-flop (501) and the second flip-flop (502) to output terminals when clock edges of the clock signals arrive, respectively; the second reset logic unit (1302) is further configured to generate a clock signal of a third flip-flop (503) according to output signals of the first flip-flop (501) and the second flip-flop (502), and the third flip-flop (503) outputs the detection reset signal;

the third reset logic unit (1303) is configured to generate a reset signal of the third flip-flop (503) according to a clock signal of the class D amplifier and an inverse of the enable signal.

4. A direct current detection circuit according to claim 3, wherein the reset signal generation circuit (132) comprises a first not gate (201), a second not gate (202), a third not gate (203), a fourth not gate (204), a fifth not gate (205), a sixth not gate (206), a seventh not gate (207), an eighth not gate (208), a first not gate (301), a second not gate (302), a third not gate (303), a fourth not gate (304), a fifth not gate (305), a first not gate (401), a first flip-flop (501), a second flip-flop (502), and a third flip-flop (503);

the input end of the second NOT gate (202) is connected with the inverse signal of the first pulse width modulation signal, and the input end of the third NOT gate (203) is connected with the inverse signal of the second pulse width modulation signal; the output signal of the second NOT gate (202) and the inverse of the second pulse width modulation signal are connected to the two input ends of the second NOT gate (302), and the output signal of the third NOT gate (203) and the inverse of the first pulse width modulation signal are connected to the two input ends of the third NOT gate (303);

the output end of the second NAND gate (302) is connected with the input end of the fourth NAND gate (204), and the output end of the third NAND gate (303) is connected with the input end of the fifth NAND gate; the output end of the fourth NOT gate (204) is connected with the clock end of the first trigger (501), and the output end of the fifth NOT gate (205) is connected with the clock end of the second trigger (502);

the input end of the first trigger (501) and the input end of the second trigger (502) are both connected with a high level, the forward output end of the first trigger (501) and the forward output end of the second trigger (502) are respectively connected with two input ends of the fourth NAND gate (304), the output end of the fourth NAND gate (304) is connected with the clock end of the third trigger (503) after passing through the fifth NAND gate (205), and the input end of the third trigger (503) is connected with a high level;

one input end of the first NAND gate (301) is connected with an enabling signal, the other input end of the first NAND gate is connected with the output end of the fourth NAND gate (304), the output end of the first NAND gate (301) is connected with the input end of the first NAND gate (201), and the output end of the first NAND gate (201) is connected with the reset end of the first trigger (501) and the reset end of the second trigger (502);

the input end of the seventh NAND gate (207) is connected with a clock signal of a class D loop, the input end of the seventh NAND gate (305) is connected, the output end of the seventh NAND gate (207) is connected with the other input end of the fifth NAND gate (305), the output end of the fifth NAND gate (305) is connected with one input end of the first NOR gate (401) after passing through the eighth NAND gate (208), the other input end of the first NOR gate (401) is connected with an inverse signal of the enabling signal, the output end of the first NOR gate (401) is connected with the reset end of the third trigger (503), the input end of the third trigger (503) is connected with a high level, and the output end of the third trigger (503) outputs the detection reset signal.

5. The direct current detection circuit according to claim 1, wherein the charge-discharge circuit (11) includes:

a first current mirror circuit (101) for providing the charging current to the capacitor;

a first switch connected in series with the first current mirror circuit (101), the first switch further connected with the charge-discharge node;

a second switch connected in series with the first current mirror circuit (101), the second switch further connected with the charge-discharge node;

and the second current mirror circuit (102) is connected with the charge and discharge node and is used for providing the discharge current.

6. The direct current detection circuit according to claim 5, wherein the second switch is electrically connected to the charge-discharge node through an operational amplifier;

the inverting input end of the operational amplifier is connected with the second switch, the output end of the operational amplifier is connected with the inverting input end, and the non-inverting input end of the operational amplifier is connected with the charge-discharge node.

7. The direct current detection circuit of claim 5, wherein the first switch and the second switch are P-type transistors;

the grid electrode of the first switch is connected with the second control signal, the grid electrode of the second switch is connected with the first control signal, and the first control signal and the second control signal are obtained by performing level conversion on the first pulse width modulation signal and the second pulse width modulation signal and then performing logic operation.

8. The direct current detection circuit according to claim 7, wherein,

the PWM signal processing circuit (12) comprises an exclusive OR gate and an NOT gate;

the two input ends of the exclusive-or gate respectively input an inverse signal of the first pulse width modulation signal and an inverse signal of the second pulse width modulation signal, and the output end of the exclusive-or gate outputs a first control signal;

the input end of the NOT gate inputs the first control signal, and the output end of the NOT gate outputs the second control signal.

9. The direct current detection circuit according to claim 5, wherein the first current mirror circuit (101) comprises a first current source circuit (111), and the second current mirror circuit (102) comprises a second current source circuit (112);

the first current source circuit (111) provides a charge image current source proportional to a battery voltage, and/or the second current source circuit (112) provides a discharge image current source based on a reference voltage; the charging image current source and the charging current are image currents, and the discharging image current source and the discharging current are image currents.

10. An electronic device comprising a dc detection circuit as claimed in any one of claims 1 to 9.