JP4811148B2 - Pulse width modulation circuit and switching amplifier using the same - Google Patents

Description

  The present invention relates to a pulse width modulation circuit that outputs, for example, a pulse width modulation (PWM) of an audio signal and a switching amplifier (for example, an audio amplifier) using the same.

  Conventionally, switching amplifiers that use a pulse width modulation circuit (see, for example, Patent Document 1) that performs pulse width modulation on an audio signal as an input signal and outputs the modulated signal have been proposed. In this switching amplifier, a predetermined power supply voltage is switched based on the modulation signal output from the pulse width modulation circuit, and the switched output signal is output to a load (for example, a speaker) through, for example, a low-pass filter.

JP 2004-320097 A

FIG. 23 is a configuration diagram illustrating an example of a conventional switching amplifier. This switching amplifier includes a pulse width modulation circuit 51 connected to the audio signal generation source AU, a switching circuit 52, and a low-pass filter circuit 53. According to this switching amplifier, the amplitude of the audio signal e _S output from the audio signal generation source AU is subjected to pulse width modulation in the pulse width modulation circuit 51, and the modulated modulation signal OUT 1 is output to the switching circuit 52. . The modulation signal OUT2 obtained by inverting the modulation signal OUT1 by the inverting circuit 54 is output to the switching circuit 52. In the switching circuit 52, the positive and negative power supply voltages + V _D and −V _D are alternately switched based on the modulation signals OUT1 and OUT2, and the high-frequency component is removed from the switched output by the low-pass filter circuit 53, and the output signal V _0. As shown in FIG.

FIG. 24 is a circuit diagram showing an example of the internal configuration of the pulse width modulation circuit 51 shown in FIG. FIG. 25 is a timing chart showing voltage waveforms at points A to H of the pulse width modulation circuit 51. The operation of the pulse width modulation circuit 51 will be briefly described. Based on the first and second clock signals φ1 and φ2 generated from the clock generation circuit 61, the first and fourth switches SW11, 14 and the second and third switches SW12 and SW13 are alternately turned on and off. By this on and off operation, the bias current Ib from the charging bias current source 63 and the audio signal e _S from the audio signal conversion circuit 64 are obtained. There summed sum current (Ib + G · e _S) is charged in the first and second integrating capacitors C11, C12 are supplied alternately.

For example, in the first period T1 (see FIG. 25) in which the first clock signal φ1 is at the high level and the second clock signal φ2 is at the low level, the second and third switches SW12 and SW13 are turned on to perform the second integration. Capacitor C12 is charged. The slope of the voltage waveform during charging (the voltage at point A in FIG. 24) depends on the positive and negative states of the audio signal e _S and the magnitude of the amplitude. For example, in a state where the audio signal e _S is positive (0 <G · e _S <Ib / 2), the slope of the voltage waveform in the first period T1 is steep, and the audio signal e _S is negative (0> G · e _S. In the state of> −Ib / 2), the slope of the voltage waveform becomes gentle.

In the second period T2 following the first period T1, the first and fourth switches SW11 and SW14 are turned on, and the second integration capacitor C12 is charged by the discharge bias current source 65 with the charge charged in the first period T1. Discharged with a constant discharge amount. When the second integration capacitor C12 is discharged, the voltage at point B (see FIG. 24) is compared with a predetermined reference voltage Vref by the second comparison circuit 68, and when the voltage at the second integration capacitor C12 becomes the reference voltage Vref, The second integrating capacitor C12 is instantaneously discharged by the sixth switch SW16 of the second reset circuit 70. When discharging the second integration capacitor C12, since the discharge amount is always constant, the time t from when the second period T2 is started until the voltage at the second integration capacitor C12 reaches the reference voltage Vref is It changes depending on the slope of the voltage waveform (voltage at point A in FIG. 25), that is, the positive / negative state of the audio signal e _S and the amplitude thereof.

  On the other hand, in the first integration capacitor C11, an operation shifted by a half cycle from the charge / discharge operation in the second integration capacitor C12 is performed. That is, in the first integrating capacitor C11, the charge charged in the first period T1 is discharged by the fifth switch SW15 of the first reset circuit 69 in the second period T2. Thereafter, charging and discharging are repeated in the first and second integrating capacitors C11 and C12 every half cycle.

  In the signal voltage circuit 71, the pulse width of the pulse width modulation signal PWM-OUT is generated based on the time t from when discharge is started in the first or second integration capacitor C11, C12, and the cycle is constant. The pulse width can be generated based on the clock signals φ1 and φ2.

FIG. 26 is a circuit diagram showing an internal configuration of a modified example of the pulse width modulation circuit 51 shown in FIG. FIG. 27 is a timing chart showing voltage waveforms at points A to J in another pulse width modulation circuit 80. In the pulse width modulation circuit 80, the audio signal voltage-current converted by the audio signal conversion circuit 82 to the third and fourth integration capacitors C 13 and C 14 based on the clock signal φ 3 output from the clock generation circuit 81. and e _S, the sum current of the bias current Ib from the charging bias current source _{83,84 (Ib + G · e S} ) is alternately supplied to and charged in the third and fourth integrating capacitor C13, C14.

For example, in the first period T1, the switch circuit 85 is switched to the third integration capacitor C13 side and the third integration capacitor C13 is charged by the sum current (Ib + G · e _S ). In the second period T2, the switch circuit 85 is switched to the fourth integration capacitor C14 side, and is charged with a constant charge amount only by the bias current Ib. In the second period T2, when the third comparison circuit 86 detects that the voltage in the third integration capacitor C13 has reached the reference voltage Vref, the first RS flip-flop circuit 87 and the third reset circuit 88 7 switch SW17 is turned on, and the third integrating capacitor C13 is instantaneously discharged.

On the other hand, the fourth integrating capacitor C14 is charged with the sum current (Ib + G · e _S ) in the second period T2, and charged with a constant charge amount only with the bias current Ib in the third period T3. In the third period T3, when the fourth comparison circuit 89 detects that the voltage in the fourth integration capacitor C14 has reached the reference voltage Vref, the second RS flip-flop circuit 90 and the fourth reset circuit 91 The eighth switch SW18 is turned on, and the fourth integrating capacitor C14 is instantaneously discharged. Thereafter, charging and discharging are repeated in the third and fourth integrating capacitors C13 and C14 every half cycle.

  In the signal voltage circuit 71, the pulse of the pulse width modulation signal PWM-OUT is based on the time t from the start of charging with the constant bias current Ib to the reset in the third or fourth integration capacitor C13, C14. A width is generated, and a pulse width can be generated based on a clock signal φ3 having a constant period.

In the circuits in FIGS. 24 and 26, the pulse width of the pulse width modulation signal PWM-OUT is set according to the positive / negative state of the audio signal e _S and the amplitude, but the audio signal e _S is an analog signal. For this reason, the maximum value may not be specified. In such a case, the third or fourth integration capacitor C13, C14 is not reset, and the charge is left in the third or fourth integration capacitor C13, C14, and the next charging period is started. As a result, an error occurs in the time t from the start of the discharge to the reset at the time of discharge, and the pulse width cannot be accurately modulated in the next period.

For example, in the pulse width modulation circuit 51 shown in FIG. 24, the first integration capacitor C11 is charged with the sum current (Ib + G · e _S ) in the second period T2. However, when the audio signal e _S is a positive excessive signal, as shown in FIG. 28, the charging voltage in the first integrating capacitor C11 becomes too large, and a constant discharge amount is applied by the bias current Ib in the third period T3. Even when discharged at, the voltage at the first integrating capacitor C11 does not reach the reference voltage Vref (see waveform at point A). For this reason, the first integration capacitor C11 is reset by the fifth switch SW15 when the voltage at the first integration capacitor C11 reaches the reference voltage Vref, but the voltage at the first integration capacitor C11 is the reference. Since the voltage Vref is not reached, the charged charge remains in the first integrating capacitor C11 without being reset.

Therefore, in the subsequent fourth period T4, charging is performed with the sum current (Ib + G · e _S ) without being reset (the voltage of the first integrating capacitor C11 does not return to 0). The capacitor C11 is charged with electric charge remaining, and charging is performed in a state where excess electric charge is accumulated. The error is accumulated, and the voltage in the first integrating capacitor C11 is used as a reference in the next period. It may happen that the voltage Vref is not reached. For this reason, for example, the voltage waveform at point G shown in FIG. 28 remains high level during the third period T3 and is output as it is as the pulse width modulation signal PWM-OUT. The pulse width is not accurately modulated.

As shown in FIG. 29, when the audio signal e _S is a negative excessive signal, the charging voltage due to the sum current (Ib + G · e _S ) of the first integrating capacitor C11 does not increase greatly in the second period T2. Also in this case, the voltage in the first integrating capacitor C11 never reaches the reference voltage Vref even in the second period T2 and the third period T3. For this reason, the voltage waveform at point G shown in FIG. 29 is maintained at the low level during the second and third periods T2 and T3, and is output as it is as the pulse width modulation signal PWM-OUT. The pulse width is not accurately modulated in the next period.

  In addition, when a low level (or high level) signal is continuously output as the pulse width modulation signal PWM-OUT, the effective frequency (switching frequency) decreases or the maximum modulation degree differs between positive and negative signals. There is also a problem that a direct current component is generated when an excessive signal is input.

On the other hand, in the pulse width modulation circuit 80 shown in FIG. 26, when the audio signal e _S that is a negative excessive signal is input, the audio signal e _S is small at the end of the first period T1, as shown in FIG. Therefore, the charging voltage becomes negative, and the voltage of the third integrating capacitor C13 may not reach the reference voltage Vref even if charging is performed in the subsequent second period T2. For this reason, the third integration capacitor C13 is not reset by the fifth switch SW15, and the charged charge remains in the third integration capacitor C13.

Therefore, in the subsequent third period T3, charging is performed with the sum current (Ib + G · e _S ), but the third integration capacitor C13 remains charged (the voltage does not return to 0). It will be charged. Therefore, the pulse width may not be accurately modulated in the next period.

Further, as shown in FIG. 31, when the audio signal e _S is a positive excessive signal, the voltage in the third integrating capacitor C13 does not exceed the reference voltage Vref in the first period T1. Since the audio signal e _S is a positive excessive signal, the voltage in the third integrating capacitor C13 exceeds the reference voltage Vref, and is reset when shifting to the second period T2. In the subsequent second period T2, the reset state is maintained, and charging using only the bias current Ib that should be performed is not performed.

  Therefore, the voltage waveform at point E shown in FIG. 31 becomes low level in the second period T2, and the voltage waveform at point G becomes high level, which is output as it is as the pulse width modulation signal PWM-OUT. Is done. Therefore, the pulse width is not accurately modulated in the next period.

In order to solve the above problem, a so-called limiter may be provided in the input circuit for the audio signal e _S so that the audio signal e _S falls within a range regulated by the limiter. However, since the input audio signal e _S is an analog signal, depending on the setting of the limit value of the limiter, the audio signal e _S itself may be affected by distortion or the like. Further, the limit value of the limiter may be slightly shifted due to the influence of circuit constants and temperature changes, and there is a problem in installing the limiter in the input circuit.

  The present invention has been conceived under the circumstances described above, and provides a pulse modulation circuit that suppresses problems caused by excessive input signals (for example, audio signals) and a switching amplifier to which the pulse modulation circuit is applied. Is the issue.

  In order to solve the above problems, the present invention takes the following technical means.

  The pulse width modulation circuit provided by the first aspect of the present invention charges the first integration circuit based on a current based on an input signal in a first period which is a half cycle of a predetermined clock signal, and In the second period following the first period shifted by a half cycle from the period, the charging voltage accumulated in the first integration circuit is changed based on a constant bias current, and the input signal is changed in the second period. A second integrating circuit different from the first integrating circuit is charged based on the current based on the charging current, and the charging voltage accumulated in the second integrating circuit is based on a constant bias current in a third period following the second period. An integration control circuit for changing, a first detection circuit for detecting a time from when the second period starts until a voltage in the first integration circuit reaches a predetermined reference voltage, and the third period A second detection circuit for detecting a time from when the voltage is started until the voltage in the second integration circuit reaches a predetermined reference voltage, and the first detection circuit and the second detection circuit are provided every half cycle of the clock signal. And a pulse width generation circuit for generating a pulse width based on the time detected by the first detection circuit and the time detected by the second detection circuit, which are alternately and repeatedly output, and each period is switched. A pulse generation circuit for generating a first pulse signal output immediately before, and when the input signal is excessive and the voltage in the first integration circuit does not reach a predetermined reference voltage in the second period; Based on the first pulse signal generated by the pulse generation circuit, the voltage charged in the first integration circuit is forcibly discharged, and the input signal When the voltage in the second integration circuit does not reach a predetermined reference voltage in the third period, the second integration circuit is based on the first pulse signal generated by the pulse generation circuit. And a discharge control circuit that forcibly discharges the voltage charged in (1).

  According to this configuration, in the first period which is a half cycle of the clock signal, the first integration circuit (for example, the first integration capacitor) is charged based on the current based on the input signal (for example, the audio signal), and the subsequent first period. In the second period, the charging voltage accumulated in the first integrating circuit is changed (for example, discharged or further charged) based on a constant bias current. On the other hand, in the second period, the second integration circuit (for example, the first integration capacitor) is charged based on the current based on the input signal, and in the subsequent third period, the second integration is performed based on the constant bias current. The charging voltage stored in the circuit is changed (for example, discharged or further charged). In the second period, the time from the start of the second period until the voltage in the first integration circuit reaches a predetermined reference voltage is detected. In the third period, the third period is started. Until the voltage in the second integration circuit reaches a predetermined reference voltage. These detected times are repeatedly output alternately every half cycle of the clock signal, and a pulse width is generated based on these times.

  In such a pulse width modulation circuit, for example, when the audio input signal is excessive and the voltage in the first integration circuit does not reach the predetermined reference voltage in the second period, the first generated by the pulse generation circuit. Based on the pulse signal, the voltage charged in the first integration circuit is forcibly discharged. In addition, when the voltage in the second integration circuit does not reach the predetermined reference voltage in the third period, the voltage charged in the second integration circuit is forcibly discharged based on the first pulse signal. That is, when the audio input signal is excessive, each period is switched even when the voltage in the first integration circuit does not reach the predetermined reference voltage and the pulse width modulation cannot be accurately performed in the next period. Since the first and second integration circuits are forcibly discharged by the first pulse signal output immediately before, the first and second integration circuits can be returned to the initial charging state. Problems during input can be suppressed.

  In the pulse width modulation circuit according to the present invention, the pulse generation circuit generates a second pulse signal that is output immediately after the switching of each period, and the pulse width generation circuit is configured such that the input signal is excessive. When the voltage in the first integration circuit does not reach a predetermined reference voltage in the second period, the second pulse signal generated by the pulse generation circuit is output as a pulse width modulation signal, and When the input signal is excessive and the voltage in the second integration circuit does not reach a predetermined reference voltage in the third period, the second pulse signal generated by the pulse generation circuit is converted into a pulse width modulation signal. (Claim 2).

  In the pulse width modulation circuit of the present invention, the first detection circuit includes a first comparison circuit that compares a charge voltage accumulated in the first integration circuit in the second period with a predetermined reference voltage, The second detection circuit includes a second comparison circuit that compares a charging voltage accumulated in the second integration circuit in the third period with a predetermined reference voltage, and the discharge control circuit includes the first comparison circuit. A first discharge circuit for forcibly discharging the charging voltage accumulated in the first integration circuit based on the output of the first pulse signal or the first pulse signal, and the output of the second comparison circuit or the first pulse signal A second discharge circuit for forcibly discharging the charge voltage accumulated in the second integration circuit may be provided.

  In the pulse width modulation circuit of the present invention, the integration control circuit includes a first discharge circuit that discharges with a constant discharge amount based on a constant bias current in the second period, and a constant bias current in the third period. And a second discharge circuit that discharges with a constant discharge amount.

  In the pulse width modulation circuit of the present invention, the integration control circuit includes: a first charging circuit that charges the first integration circuit at a constant rate based on a constant bias current in the second period; and And a second charging circuit that charges the second integration circuit at a constant rate based on a constant bias current.

  The switching amplifier provided by the second aspect of the present invention includes a pulse width modulation circuit provided by the first aspect of the present invention, a voltage source that outputs a predetermined power supply voltage, and an output from the pulse width modulation circuit. A switching circuit that switches a predetermined power supply voltage supplied from the voltage source based on a modulated signal, wherein the integration control circuit includes the first integration circuit and the second integration circuit A bias current generating circuit for generating a constant bias current to be supplied to the circuit, detecting an average voltage of an amplitude of a modulation signal output from the pulse width modulation circuit, and detecting the average voltage with respect to the bias current generating circuit; An average voltage detection circuit for outputting is further provided (claim 6).

  According to this configuration, since this switching amplifier can output the average voltage of the amplitude of the modulation signal output from the pulse width modulation circuit to the bias current generation circuit, the average voltage is fed back to the bias current generation circuit. The offset component in the pulse width modulation circuit can be removed.

  The switching amplifier according to the present invention may further include a current proportional circuit that makes the bias current generated by the bias current generating circuit proportional to the power supply voltage output from the voltage source.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a configuration diagram showing a switching amplifier to which a pulse width modulation (PWM) circuit according to a first embodiment of the present invention is applied. FIG. 2 is a block circuit diagram showing an embodiment of the pulse width modulation circuit 1 shown in FIG. The switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, positive and negative power supply voltage + E _B, the first power supply 4 and supplies -E _B A second power source 5 is provided. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

The pulse width modulation circuit 1 generates and outputs a modulation signal PWM-OUT by pulse width modulating the audio signal e _S as an input signal output from the audio signal generation source AU. The modulation signal PWM-OUT output from the pulse width modulation circuit 1 is input to the switching circuit 2.

In the switching circuit 2, positive and negative power supply voltages + E _B and −E _B supplied from the first power supply 4 and the second power supply 5 are alternately switched based on the modulated modulation signal PWM-OUT. That is, the switching circuit 2 includes an inverter 2a that inverts the phase of the modulation signal PWM-OUT output from the pulse width modulation circuit 1, a switch element SW-A that operates on and off based on the modulation signal PWM-OUT, Based on the modulation signal PWM-OUT ′ obtained by inverting the modulation signal PWM-OUT by the inverter 2a, the switch element SW-B that is turned on and off is connected to both ends of both switch elements SW-A and SW-B. Reverse-current preventing diodes DA and DB are provided.

The switch elements SW-A and SW-B are alternately turned on and off by the modulation signal PWM-OUT and the inverted modulation signal PWM-OUT ′, and are switched with respect to the low-pass filter circuit 3 and the load RL. positive and negative power supply voltage + E _B, supplies -E _B.

The low-pass filter circuit 3 is configured by an LC circuit including a coil L ₀ and a capacitor C ₀ and is a circuit that removes a high-frequency component of an output signal output from the switching circuit 2 and supplies the output signal to the load RL. Has a frequency. In the low-pass filter circuit 3, the high-frequency components of the switched positive and negative power supply voltages + E _B and −E _B are removed, and the output is supplied to the load RL and is output from the load RL as sound.

  As shown in FIG. 2, the pulse width modulation circuit 1 includes an audio signal conversion circuit 11, a charging bias current source 12, a current adding circuit 13, a switch circuit 14, a clock generation circuit 15, and a discharging bias current. A source 16, first and second integration circuits 17 and 18, first and second comparison circuits 19 and 20, first and second reset circuits 21 and 22, and a signal output circuit 23 are configured. .

The audio signal conversion circuit 11 is a circuit for voltage-current conversion of the audio signal e _S supplied from the audio signal generation source AU (see FIG. 1) to the pulse width modulation circuit 1. Here, when the conversion conductance in the audio signal conversion circuit 11 is G, the current flowing into the downstream current addition circuit 13 can be expressed as G · e _S.

The charging bias current source 12 is a circuit that converts a predetermined positive power supply voltage + Va into a bias current Ib and supplies the bias current Ib to the downstream current adding circuit 13. The current adding circuit 13 adds the current (G · e _S ) converted by the audio signal conversion circuit 11 and the bias current Ib converted by the charging bias current source 12 (G · e _S + Ib). Is supplied to the downstream switch circuit 14.

The switch circuit 14 includes first to fourth switches SW1 to SW4, and the first clock signal output from the clock generation circuit 15 is the sum current (G · e _S + Ib) added by the current addition circuit 13. This circuit is switched by second and third clock signals φ2 and φ3 (described later) generated based on φ1 (not shown) and is supplied to the first and second integrating circuits 17 and 18 in the subsequent stage.

  The connection configuration will be described. One end of each of the first and second switches SW1, SW2 is connected to the current adding circuit 13, and the other end of the first switch SW1 (see point A in FIG. 2) is connected to the first integrating circuit. 17, thereby forming a charging path for the first integrating circuit 17. The other end of the first switch SW 1 is also connected to one end of the third switch SW 3, and the other end of the third switch SW 3 is connected to the discharge bias current source 16. A discharge path is formed. On the other hand, the other end of the second switch SW2 (see the point B in FIG. 2) is connected to the second integration circuit 18, thereby forming a charging path for the second integration circuit 18. The other end of the second switch SW2 is also connected to one end of the fourth switch SW4, and the other end of the fourth switch SW4 is connected to the discharge bias current source 16, whereby the second integrating circuit 18 A discharge path is formed.

  The clock generation circuit 15 generates a plurality of types of clock signals based on the first clock signal φ1 serving as a reference clock, and generates the first to fourth switches SW1 to SW4 and the first and second reset circuits 21 and 22. , And the signal output circuit 23, respectively.

  As shown in FIG. 3, the clock generation circuit 15 generates a second clock signal φ2 obtained by delaying the first clock signal φ1 having a duty ratio of approximately 50% by ΔT and a second clock signal φ2 by a period (for example, 10 to 20 nsec). The inverted third clock signal φ3, the fifth clock signal φ5 representing the exclusive OR of the first clock signal φ1 and the second clock signal φ2, and the fourth clock signal obtained by delaying the second clock signal φ2 by a period ΔT. A sixth clock signal φ6 representing an exclusive OR of φ4 and the second clock signal φ2 is output.

  As shown in FIG. 2, the clock generation circuit 15 is connected to the switch circuit 14 and outputs the second and third clock signals φ 2 and φ 3 to the switch circuit 14. The clock generation circuit 15 is connected to the first and second reset circuits 21 and 22, and outputs the third and fifth clock signals φ 3 and φ 5 to the first reset circuit 21 and the second to the second reset circuit 22. And fifth clock signals φ2 and φ5, respectively. The clock generation circuit 15 is connected to the signal output circuit 23 and outputs second, third, and sixth clock signals φ2, φ3, and φ6.

  The clock generation circuit 15 is provided outside the pulse width modulation circuit 1, and the second, third, fifth, and sixth clock signals φ2, φ3, φ5, and φ6 are respectively supplied as external clock signals to the pulse width modulation circuit 1. It may be configured to give to.

  As shown in FIG. 4, the clock generation circuit 15 includes a reference clock generation circuit 24, a first delay circuit 25, a first NOT circuit N1, a second NOT circuit N2, a second delay circuit 26, and a first EX-OR. The circuit EX1 and the second EX-OR circuit EX2 are configured.

  The reference clock generation circuit 24 outputs a first clock signal φ1 (see FIG. 3) serving as a reference, and includes a multivibrator including a plurality of inverters, resistors, and capacitors. The output of the reference clock generation circuit 24 is connected to one input terminal of the first delay circuit 25 and the first EX-OR circuit EX1.

  The first delay circuit 25 is configured by an RC circuit including a resistor and a capacitor, and delays the first clock signal φ1 by a predetermined period ΔT. The output of the first delay circuit 25 is connected to the first NOT circuit N1.

  The first NOT circuit N1 inverts the output of the first delay circuit 25. The output of the first NOT circuit N1 is a third clock signal φ3, which is connected to the second NOT circuit N2 and has an output terminal. Is output to the outside. The second NOT circuit N2 inverts the output of the first NOT circuit N1, and the output of the second NOT circuit N2 is the second clock signal φ2. The output of the second NOT circuit N2 is output to the outside through an output terminal, and is connected to the other input terminal of the second delay circuit 26 and the first EX-OR circuit EX1, respectively.

  The second delay circuit 26 is configured by an RC circuit including a resistor and a capacitor, and delays the output of the second NOT circuit N2 by a predetermined period ΔT. The output of the second delay circuit 26 is the fourth clock signal φ4 and is connected to one input terminal of the second EX-OR circuit EX2.

  In the first EX-OR circuit EX1, the first clock signal φ1 from the reference clock generation circuit 24 is input to one input terminal, and the second clock signal φ2 from the second NOT circuit N2 is input to the other input terminal. Is calculated and output as the fifth clock signal φ5 to the outside through the output terminal.

  In the second EX-OR circuit EX2, the second clock signal φ2 from the second NOT circuit N2 is input to one input terminal, and the fourth clock signal φ4 from the second delay circuit 26 is input to the other input terminal. Are calculated and output to the outside through the output terminal as the sixth clock signal φ6.

  Returning to FIG. 2, the second and third switches SW2 and SW3 of the switch circuit 14 are both turned on and off by the third clock signal φ3, and both the first and fourth switches SW1 and SW4 are controlled by the second clock signal φ2. Is turned on and off by. Therefore, the second and third switches SW2 and SW3 and the first and fourth switches SW1 and SW4 are alternately turned on and off.

For example, as shown in FIG. 3, when the second clock signal φ2 is at a high level and the third clock signal φ3 is at a low level (hereinafter referred to as “first period T1”), the first and fourth switches SW1, SW4 Is turned on, and the second and third switches SW2 and SW3 are turned off. In this case, the sum current (G · e _S + Ib) from the current adding circuit 13 flows to the first integrating circuit 17 via the first switch SW1, thereby charging the first integrating circuit 17.

On the other hand, when the second clock signal φ2 is at a low level and the third clock signal φ3 is at a high level (hereinafter referred to as “second period T2”), the second and third switches SW2 and SW3 are turned on, and the first The fourth switches SW1 and SW4 are turned off (see the state of the switch circuit 4 in FIG. 2). In this case, the sum current (G · e _S + Ib) flows to the second integration circuit 18 via the second switch SW2, thereby charging the second integration circuit 18.

The first and second integrating circuits 17 and 18 are constituted by a first integrating capacitor C1 and a second integrating capacitor C2, respectively. As described above, in the first integration capacitor C1, the first switch SW1 is turned on and the third switch SW3 is turned off in the second period T2, whereby the sum current (G • Charged by e _S + Ib). The first integrating capacitor C1 is charged when the first switch SW1 is turned off and the third switch SW3 is turned on during the next half-cycle period (hereinafter referred to as “third period T3”). The discharged electric charge flows into the discharge bias current source 16 to discharge with a constant discharge amount.

  On the other hand, in the second integration capacitor C2, the sum current flowing from the current addition circuit 13 is turned on when the second switch SW2 is turned on and the fourth switch SW4 is turned off in the first period T1 (see FIG. 3). Is charged by. In the second integration capacitor C2, in the next second period T2, the second switch SW2 is turned off and the fourth switch SW4 is turned on, so that the charged charge flows to the discharge bias current source 16. As a result, the battery is discharged at a constant discharge amount. That is, the first and second integrating capacitors C1 and C2 are alternately charged and discharged every unit period (for example, the first period T1) in which the levels of the second and third clock signals φ2 and φ3 are maintained. Is called.

  The discharging bias current source 16 is connected to the negative power supply voltage −Va, and has the same magnitude as the bias current Ib flowing in the charging bias current source 12 when the first or second integrating capacitor C1 or C2 is discharged. This is for flowing the bias current Ib. The discharging bias current is not the same as the bias current Ib flowing through the charging bias current source 12, and may be set individually.

  The first and second comparison circuits 19 and 20 compare the voltage accumulated in the first and second integration circuits 17 and 18 with a predetermined reference voltage Vref, so that the pulse width modulation signal PWM− is output at the output. It is a circuit for defining the pulse width of OUT. The first and second comparison circuits 19 and 20 are circuits for forcibly resetting the first and second integration circuits 17 and 18 when the first and second integration circuits 17 and 18 are discharged. When the first and second comparison circuits 19 and 20 are constituted by, for example, CMOS inverter elements, the reference voltage Vref corresponds to a threshold value defined by the high level and the low level of the CMOS inverter element. The threshold value is set to about ½ of the power supply voltage of the CMOS inverter element. For example, if the power supply voltage of the CMOS inverter element is about 5V, the reference voltage Vref is about 2.5V, which is half of that.

  The reference voltage Vref is input to the positive (+) side input terminals of the first and second comparison circuits 19 and 20, respectively, and the first and second integration capacitors C1 and C2 are input to the negative (−) side input terminals. One end of each is connected. The first and second comparison circuits 19 and 20 can be configured by, for example, CMOS inverter elements (not shown). When the first and second comparison circuits 19 and 20 are configured by CMOS inverter elements, the high and low levels of the CMOS inverter elements are set. A prescribed threshold value is set as the reference voltage Vref.

  The outputs of the first and second comparison circuits 19 and 20 (see the points C and D in FIG. 2) are normally at a high level, and the voltages (first and second integration capacitors C1 and C2) at the negative input terminals. When the charging voltage is higher than the reference voltage Vref, a low level signal is output from the output terminal.

  The first and second reset circuits 21 and 22 forcibly end the discharge in the first and second integration capacitors C1 and C2 during the period in which the first and second integration circuits 17 and 18 are discharged, respectively. This is a circuit for resetting. The first reset circuit 21 includes first and second AND circuits A1 and A2, a first OR circuit O1, and a fifth switch SW5. The second reset circuit 22 includes third and fourth AND circuits A3 and A4, and a second OR circuit. O2 and the sixth switch SW6.

  The first AND circuit A1 of the first reset circuit 21 has one input terminal connected to the output terminal of the first comparison circuit 19 and the other input terminal connected to one input terminal of the second AND circuit A2. The third clock signal φ3 is input by being connected to the clock generation circuit 15. The second input circuit A2 has the other input terminal connected to the clock generation circuit 15 and receives the fifth clock signal φ5. The output terminals of the first AND circuit A1 and the second AND circuit A2 are connected to the input terminal of the first OR circuit O1, respectively. The output terminal of the first OR circuit O1 (see point E in FIG. 2) is connected to the fifth switch SW5, and the output of the first OR circuit O1 controls the on / off operation of the fifth switch SW5.

  On the other hand, the third AND circuit A3 of the second reset circuit 22 has one input terminal connected to the output terminal of the second comparison circuit 20, and the other input terminal connected to one input terminal of the fourth AND circuit A4. In addition, the second clock signal φ2 is input by being connected to the clock generation circuit 15. In the fourth AND circuit A4, the other input terminal is connected to the clock generation circuit 15 and the fifth clock signal φ5 is input. The output terminals of the third AND circuit A3 and the fourth AND circuit A4 are connected to the input terminal of the second OR circuit O2, respectively. The output terminal of the second OR circuit O2 (see point F in FIG. 2) is connected to the sixth switch SW6, and the output of the second OR circuit O2 controls the on / off operation of the sixth switch SW6.

  The signal output circuit 23 includes first and second NOR circuits NR1 and NR2 and a third OR circuit O3. The first NOR circuit NR1 has one input terminal connected to the output terminal of the first comparison circuit 19 (see point C in FIG. 2), and the other input terminal connected to the clock generation circuit 15 to be connected to the second clock signal φ2. Is entered. On the other hand, the second NOR circuit NR2 has one input terminal connected to the output terminal of the second comparison circuit 20 (see point D in FIG. 2), and the other input terminal connected to the clock generation circuit 15 to be connected to the third clock. Signal φ3 is input.

  The first NOR circuit N1 calculates the negative logical sum of the second clock signal φ2 and the output of the first comparison circuit 19 to start discharging by the first integration capacitor C1, and then the first integration capacitor C1. A high level is output at time t (described later) until the voltage of C1 reaches the reference voltage Vref. The second NOR circuit N2 calculates the negative logical sum of the first clock signal φ1 and the output of the second comparison circuit 20, thereby starting the discharge by the second integration capacitor C2, and then the second integration capacitor A high level is output at time t (described later) until the voltage of C2 reaches the reference voltage Vref.

  The third OR circuit O3 has three input terminals. The output of the first NOR circuit NR1 (see point G in FIG. 2), the output of the second NOR circuit NR2 (see point H in FIG. 2), and a clock generation circuit The sixth clock signal φ6 from 15 is input. In the third OR circuit O3, the output terminal of the third OR circuit O3 is connected to the subsequent switching circuit 2 (see FIG. 1) as the pulse width modulation signal PWM-OUT. The third OR circuit O3 calculates the logical sum of the outputs and outputs the outputs of the first and second NOR circuits N1 and N2 and the sixth clock signal φ6 to the switching circuit 2 as one pulse width modulation signal PWM-OUT. To do.

Next, the operation of the pulse width modulation circuit 1 will be described with reference to the timing chart shown below. First, in FIG. 5, described the case where the pulse width modulation circuit 1 to operate properly (if the audio signal e _S is a non-signal (e _S = 0)), then the audio signal e _S is positive in FIG. 6 If excessive signals _{(G · e S ≧ Ib /} 2), where the audio signal e _S is a negative excessive signal for _{(G · e S ≦ -Ib /} 2) described in FIG.

In the first period T1 in FIG. 5, the second clock signal φ2 from the clock generation circuit 15 is at a high level (the third clock signal φ3 is at a low level), and thereby the first switch SW1 is turned on, The switch element SW3 is turned off. Therefore, the first integration capacitor C1 of the first integration circuit 17 is supplied with the sum current (G · e _S + Ib) from the current addition circuit 13, and the first integration capacitor C1 is charged (point A waveform). reference).

  In the first period T1, the second switch SW2 is turned off, while the fourth switch SW4 is turned on, so that the second integrating capacitor C2 of the second integrating circuit 18 is half a cycle before the first period T1. During this period T0, the charge charged flows into the discharge bias current source 16 and is discharged at a constant discharge amount (see waveform at point B).

  In the first period T1, when the voltage resulting from charging of the second integration capacitor C2 in the second comparison circuit 20 falls below the reference voltage Vref, the output of the second comparison circuit 20 changes from low level to high level. (Refer to the waveform at point D) and input to one input terminal of the third AND circuit A3 of the second reset circuit 22. Since the high level of the second clock signal φ2 is input to the other input terminal of the third AND circuit A3, the output terminal of the third AND circuit A3 also changes from the low level to the high level, which is supplied to the second OR circuit O2. The reset signal is output to the sixth switch SW6 from the output terminal of the second OR circuit O2 (see waveform at point F).

  As a result, the sixth switch SW6 changes from the OFF state to the ON state, and the electric charge discharged by the second integrating capacitor C2 flows to the ground terminal via the sixth switch SW6 and is discharged forcibly and at once. Is called.

  Note that immediately before the end of the first period T1, the fifth clock signal φ5 is turned on for the period ΔT, the on signal is input to the fourth AND circuit A4, and the second AND circuit A4 is at the high level. Since the clock signal φ2 is also input, the output of the fourth AND circuit A4 becomes high level for the period ΔT. Since the output of the third AND circuit A3 is also input to the second OR circuit O2, as a result, the output of the second OR circuit O2 becomes high level in the second half of the first period T1.

  Further, immediately before the end of the first period T1, the ON signal of the fifth clock signal φ5 is also input to the second AND circuit A2, but the third clock signal φ3 that is at a low level is input to the second AND circuit A2. Therefore, the output of the second AND circuit A2 becomes low level, the output of the first OR circuit O1 becomes low level in the first period T1, and does not affect the on / off operation of the fifth switch SW5.

  Since the third clock signal φ3 and the output of the second comparison circuit 20 are input to the second NOR circuit NR2 of the signal output circuit 23, the second integration circuit 18 has the second integration circuit 18 in the first period T1. A high level is output at a time t from the start of discharge until it is forcibly reset (see waveform at point H). Further, the second clock signal φ2 and the output of the first comparison circuit 19 are input to the first NOR circuit NR1, but the output of the first NOR circuit NR1 is maintained at a low level (see waveform at point G). Accordingly, the output of the third OR circuit O3 is directly output as the pulse width modulation signal PWM-OUT as the high level as the output of the second NOR circuit NR2.

  Note that immediately after the start of the first period T1, the sixth clock signal φ6 is turned on for the period ΔT, and the on signal is input to the third OR circuit O3, but the third OR circuit O3 receives the signal from the second NOR circuit NR2. Since the high level is input, as a result, the output of the third OR circuit O3 becomes the high level in the first half of the first period T1.

Next, in the second period T2, the third clock signal φ3 from the clock generation circuit 15 is inverted from the low level to the high level (the second clock signal φ2 is inverted from the high level to the low level). While the second switch SW2 is turned on, the fourth switch element SW4 is turned off. Therefore, the second integration capacitor C2 of the second integration circuit 18 is supplied with the sum current (G · e _S + Ib) from the current addition circuit 13, and the second integration capacitor C2 is charged (point B waveform). reference).

  In the second period T2, the first switch SW1 is turned off and the third switch SW3 is turned on, so that the first integrating capacitor C1 of the first integrating circuit 17 is charged in the first period T1. The discharged electric charge flows into the discharge bias current source 16 and is discharged with a constant discharge amount (see waveform at point A).

  Thereafter, when the voltage resulting from charging of the first integration capacitor C1 in the first comparison circuit 19 falls below the reference voltage Vref, the output of the first comparison circuit 19 changes from low level to high level (see waveform at point C). Are input to one input terminal of the first AND circuit A1 of the first reset circuit 21. Since the high level of the third clock signal φ3 is input to the other input terminal of the first AND circuit A1, the output terminal of the first AND circuit A1 also changes from the low level to the high level, which is the level of the first OR circuit O1. This becomes an output (refer to the waveform at point E) and is output as a reset signal to the fifth switch SW5.

  As a result, the fifth switch SW5 changes from the OFF state to the ON state, and the electric charge discharged by the first integrating capacitor C1 flows to the ground terminal via the fifth switch SW5, and is discharged forcibly and at once. Is called.

  Note that immediately before the end of the second period T2, the fifth clock signal φ5 is turned on for the period ΔT, the on signal is input to the second AND circuit A2, and the second AND circuit A2 is at a high level. Since the clock signal φ3 is also input, the output of the second AND circuit A2 becomes high level for the period ΔT. Since the output of the first AND circuit A1 is also input to the first OR circuit O1, as a result, the output of the first OR circuit O1 becomes high level in the second half of the second period T2.

  Also, immediately before the end of the second period T2, the ON signal during which the fifth clock signal φ5 is only for the period ΔT is also input to the fourth AND circuit A4, but the fourth AND circuit A4 has a low-level second clock signal. Since φ2 is input, the output of the fourth AND circuit A4 becomes low level, and the output of the second OR circuit O2 becomes low level in the second period T2.

  The second NOR circuit NR2 of the signal output circuit 23 receives the third clock signal φ3 and the output of the second comparison circuit 20, but the output of the second NOR circuit NR2 maintains a low level (point H waveform). reference). On the other hand, since the second clock signal φ2 and the output of the first comparison circuit 19 are input to the first NOR circuit NR1, the first integration circuit 17 starts discharging in the second period T2. A high level is output at a time t from when the signal is forcibly reset (see waveform at point G). Accordingly, the output of the third OR circuit O3 is directly output as the pulse width modulation signal PWM-OUT as the high level as the output of the first NOR circuit NR1.

  Note that immediately after the start of the second period T2, the sixth clock signal φ6 is turned on for the period ΔT, and the on signal is input to the third OR circuit O3. The third OR circuit O3 receives the signal from the first NOR circuit NR1. Since the high level is input, as a result, the output of the third OR circuit O3 becomes the high level in the first half of the second period T2.

Thereafter, in the third period T3, since the second and third clock signals φ2 and φ3 are inverted, charging is performed in the first integrating capacitor C1, while discharging is performed in the second integrating capacitor C2. Thereafter, each time a half cycle elapses, the second and third clock signals φ2 and φ3 are inverted, and the first and second integrating capacitors C1 and C2 are alternately charged and discharged. Therefore, the pulse width modulation signal PWM-OUT is output at the timing shown in FIG. 5, and the pulse width modulation signal PWM-OUT corresponding to the amplitude of the audio signal e _S is output.

Next, as shown in FIG. 6, the case where the audio signal e _S is a positive excessive signal will be described. In the first period T1, the second integration capacitor C2 is discharged with a constant discharge amount of the charge charged in the period T0 half a cycle before the first period T. In the conventional configuration, as shown in FIG. 28, when the audio signal e _S is a positive excessive signal, even when the audio signal e _S is discharged at a constant discharge amount, the discharge voltage reaches before the reference voltage Vref. The discharge period ends, that is, the second integration capacitor C2 is charged in the next period with the charge remaining, and the residual charge becomes an error, resulting in the next period. It may not be possible to accurately modulate the pulse width.

  In the present embodiment, the first and second integrating capacitors C1, C2 use the fifth clock signal φ5 having a pulse width that is turned on for the period ΔT immediately before the end of each period Tn (n = 1, 2,...). The residual charge is forcibly reset.

  As described above, the clock generation circuit 15 outputs the fifth clock signal φ5 in the period ΔT immediately before the levels of the second clock signal φ2 and the third clock signal φ3 are switched, and the fifth clock signal φ5 The second AND circuit A2 and the fourth AND circuit A4 of the second reset circuit 21 and 22 are respectively input to the input terminals.

According to FIG. 6, since the second clock signal φ2 is at a high level in the first period T1, the first switch SW1 is turned on, whereby the sum current (G · e _S + Ib) is changed to the first integrating capacitor. C1 is supplied and the first integrating capacitor C1 is charged (see waveform at point A). At this time, since the audio signal e _S is a positive excessive signal, the voltage waveform at the point A has a steep slope. When the voltage at the first integrating capacitor C1 exceeds the reference voltage Vref of the first comparison circuit 19, the output of the first comparison circuit 19 (see waveform at point C) changes from high level to low level.

  Next, in the second period T2, the second clock signal φ2 is inverted from the high level to the low level, and the third clock signal φ3 changes to the high level, so that the first switch SW1 is turned off and the third switch SW3 is turned on. As a result, the charge charged in the first integrating capacitor C1 in the first period T1 is supplied to the discharging bias current source 16 and discharged with a constant discharge amount.

  Immediately before the end of the second period T2, the ON signal of the fifth clock signal φ5 is input to one input terminal of the second AND circuit A2 of the first reset circuit 21, but the third input terminal of the second AND circuit A2 is the third input terminal. Since the clock signal φ3 is input, the operation result of the logical product of both is output from the second AND circuit A2. This output signal is output as a reset signal to the fifth switch SW5 via the first OR circuit O1 (see the waveform at point E), and turns on the fifth switch SW5.

  By the ON operation of the fifth switch SW5, the first integrating capacitor C1 is immediately and forcibly discharged (reset). Accordingly, the residual charge in the first integration capacitor C1 is eliminated, and thus the first integration capacitor C1 is charged from the charge 0 in the next third period T3.

  Since the second clock signal φ2 and the output of the first comparison circuit 19 are input to the first NOR circuit NR1 of the signal output circuit 23, the output of the first NOR circuit NR1 (see waveform at point G) is in the first period. It is maintained at the low level at T1, and in the second period T2, it is inverted to the high level as the second clock signal φ2 is inverted, and the fifth switch SW5 is turned on based on the ON signal of the fifth clock signal φ5 At this timing, the signal is inverted again to the low level.

  In other words, the first NOR circuit NR1 outputs a high level at a time t from when the first integrating capacitor C1 starts discharging in the second period T2 until it is forcibly reset. Accordingly, the output of the third OR circuit O3 is directly output as the pulse width modulation signal PWM-OUT as the high level as the output of the first NOR circuit NR1.

  Note that immediately after the start of the second period T2, the sixth clock signal φ6 is turned on for the period ΔT, and the on signal is input to the third OR circuit O3. The third OR circuit O3 receives the signal from the first NOR circuit NR1. Since the high level is input, as a result, the output of the third OR circuit O3 is output as it is.

  On the other hand, the operation of the second integrating capacitor C2 will be described. Since the third clock signal φ3 is at a low level in the first period T1, the second switch SW2 is turned off and the fourth switch SW4 is turned on. Turned on. As a result, the charge of the second integrating capacitor C2 charged in the period T0 half a cycle before the first period T1 is supplied to the discharging bias current source 16 and discharged at a constant discharge amount (point B). Waveform reference).

  Immediately before the end of the second period T2, the ON signal of the fifth clock signal φ5 is input to one input terminal of the fourth AND circuit A4 of the second reset circuit 22, but the second input terminal of the fourth AND circuit A4 receives the second signal. Since the clock signal φ2 is input, the operation result of the logical product of both is output from the fourth AND circuit A4. This output signal is output as a reset signal to the sixth switch SW6 via the second OR circuit O2 (see the F point waveform), and turns on the sixth switch SW6.

  By the ON operation of the sixth switch SW6, the second integrating capacitor C2 is immediately and forcibly discharged (reset). Therefore, the residual charge in the second integration capacitor C2 disappears, and thus the second integration capacitor C2 is charged from the charge 0 in the next second period T2.

  Since the third clock signal φ3 and the output of the second comparison circuit 20 are input to the second NOR circuit NR2 of the signal output circuit 23, the output of the second NOR circuit NR2 (see waveform at point H) is in the period T0. In the first period T1, the third clock signal φ3 is inverted to a high level as it is inverted, and the sixth switch SW6 is turned on based on the ON signal of the fifth clock signal φ5 in the first period T1. Then, it is inverted again to the low level.

  That is, the second NOR circuit NR2 outputs a high level at a time t from when the second integration capacitor C2 starts discharging in the first period T1 until it is forcibly reset. Accordingly, the output of the third OR circuit O3 is directly output as the pulse width modulation signal PWM-OUT as the high level as the output of the second NOR circuit NR2.

  Note that immediately after the start of the first period T1, the sixth clock signal φ6 is turned on for the period ΔT, and the on signal is input to the third OR circuit O3, but the third OR circuit O3 receives the signal from the second NOR circuit NR2. Since the high level is input, as a result, the output of the third OR circuit O3 is output as it is.

  As described above, the ON signal output immediately before the end of each period Tn of the fifth clock signal φ5 is generated by forcibly resetting the first and second integration capacitors C1 and C2, thereby causing each of the ON signals to be output in the next period. The capacitor C1, C2 has a function of setting the electric charge to zero. Therefore, as in the conventional configuration, the first and second integrating capacitors C1 and C2 can be prevented from being charged in the next period with the charge remaining in the present embodiment. The pulse width can be accurately modulated in the next period.

Next, the case where the audio signal e _S is a negative excessive signal as shown in FIG. 7 will be described. In the first period T1, the first integrating capacitor C1 is charged by the sum current (G · e _S + Ib). In the conventional configuration, as shown in FIG. 29, when the audio signal e _S is a negative excessive signal, the magnitude of the audio signal e _S is excessive even if the first integrating capacitor C1 is charged. Since the charging voltage is small, the first period T1 ends before the charging voltage reaches the reference voltage Vref. Then, although the battery is discharged at a constant discharge amount in the second period T2, since the charging voltage has not reached the reference voltage Vref, the pulse width modulation signal PWM-OUT continues to be at a low level and is accurately detected in the next period. In some cases, pulse width modulation cannot be performed.

  In the present embodiment, the sixth clock signal φ6 having the pulse width of the period ΔT that is turned on immediately after the start of each period Tn (n = 1, 2,...) Is output as the pulse width modulation signal PWM-OUT. In the next period, the pulse width is accurately modulated.

  That is, the first integration capacitor C1 is charged in the first period T1 and discharged in the second period T2, but as shown in the waveform at point A in FIG. Since the voltage Vref is not reached, the output of the first comparison circuit 19 (refer to the point C waveform) is maintained at a high level. The second integration capacitor C2 is charged in the second period T2 and discharged in the third period T3. As shown in the waveform B in FIG. 7, the charge voltage in the second integration capacitor C2 is the reference voltage. Since the voltage Vref is not reached, the output of the second comparison circuit 20 (refer to the point D waveform) is maintained at a high level.

  Therefore, the output of the first NOR circuit N1 (refer to the point G waveform) and the output of the second NOR circuit N2 (refer to the point H waveform) are maintained at a low level. The outputs of the first and second NOR circuits N1 and N2 are input to the third OR circuit O3. Since the sixth clock signal φ6 is also input to the third OR circuit O3, the output is the pulse width modulation signal PWM-OUT. Is output as That is, the sixth clock signal φ6 that is turned on for the period ΔT immediately after the start of each period Tn (n = 1, 2,...) Is output as it is as the pulse width modulation signal PWM-OUT.

That is, in the first embodiment, when the audio signal e _S is a negative excessive signal, since the audio signal e _S is too small, the reference voltage Vref is not reached and the pulse width modulation signal PWM-OUT cannot be output. However, by using the sixth clock signal φ6 as the pulse width modulation signal PWM-OUT, the pulse width modulation signal PWM-OUT when the audio signal e _S is a negative excessive signal is forcibly generated. Yes. Thereby, the pulse width can be accurately modulated in the next period.

  In addition, when a low level (or high level) signal is continuously output as the pulse width modulation signal PWM-OUT, the effective frequency (switching frequency) decreases or the maximum modulation degree differs between positive and negative signals. In some cases, a DC component may be generated when an excessive signal is input. However, these problems can be solved by using the sixth clock signal φ6 as the pulse width modulation signal PWM-OUT.

  Incidentally, in the pulse width modulation circuit 1 shown in FIG. 2, when it is actually used, an offset component may be generated on the circuit. For example, in the pulse width modulation circuit 1, values of the charging bias current Ib1 and the discharging bias current Ib2 (here, the discharging bias current Ib2 can be individually set with respect to the charging bias current Ib1), The values of the capacitor capacities of the first and second integrating capacitors C1 and C2, the value of the reference voltage Vref of the first and second comparison circuits 19 and 20, and the clock period of each clock signal φ1 to φ6 are all values. Have some variation. For this reason, even if the pulse width modulation circuit 1 is manufactured with the same design, different offset components are generated in the actual circuit due to these variations. Therefore, it is desirable that the pulse width modulation circuit 1 is provided with an offset adjustment function so as to vary any of the above-described variations.

Here, when we seek modulation m in the pulse width modulation circuit 1, Ib1 the charging bias current, the discharging bias current Ib2, C ₁ to capacitance of the first integration capacitor C1, the second integration capacitor the capacitance of C2 C _2, the reference voltage Vref1 of the first comparator circuit 19, a reference voltage of the second comparator circuit 20 Vref2, the charging period of the first integrating capacitor C1 (a discharge period of the second integrating capacitor C2 E1), T2 is the charging period of the second integrating capacitor C2 (corresponding to the discharging period of the first integrating capacitor C1), and T2 is discharged from the first integrating capacitor C1. The period during which the voltage drops to the reference voltage Vref1 is t1, and the voltage of the second integration capacitor C2 after the discharge of the second integration capacitor C2 is started When the period decreases to the reference voltage Vref2 and t2, time t1 and time t2 is expressed by the following equation.

  At this time, the modulation degree m is expressed by the following equation.

  In the above equation, if T1 + T2 = 2T, the degree of modulation m is transformed into the following equation.

Here, in order to make the modulation degree m proportional to only the audio signal e _S , that is, in order not to generate an offset component, the values of the first term and the second term on the right side of the above equation are set. Need to be equal. When the first term and the second term on the right side are arranged for the charging bias current Ib1, the following equation is obtained.

  At this time, the modulation degree m is expressed by the following equation.

In relation to the offset shown in equation 4 to zero, charging bias currents Ib1, the discharging bias current Ib2, capacitance C ₁ of the first integration capacitor C1, the capacitor capacitance C ₂ of the second integration capacitor C2 Any one of the reference voltage Vref1 of the first comparison circuit 19, the reference voltage Vref2 of the second comparison circuit 20, and the sum T of the charging period T1 by the first integrating capacitor C1 and the charging period T2 by the second integrating capacitor C2. Even if it changes, the offset changes. Therefore, the offset can be adjusted by changing any one or more of these constants. In the pulse width modulation circuit 1, since it is easiest to vary the current in terms of the circuit configuration, the offset adjustment is generally performed by adjusting the charging bias current Ib1 and the discharging bias current Ib2. Is.

  For example, FIG. 8 is a detailed circuit diagram of the charging bias current source 12 and the discharging bias current source 16 capable of performing offset adjustment. The charging bias current source 12 and the discharging bias current source 16 shown in FIG. 8 include first and second current mirror circuits each having two transistors Qa and Qb and two transistors Qa ′ and Qb ′. The discharge bias currents Ib1 and Ib2 can be varied independently.

  A positive power supply voltage + Va is connected to the two transistors Qa and Qb of the first current mirror circuit, the A terminal is connected to the transistor Qb via the transistor Qd, and the addition circuit shown in FIG. 2 is connected to the A terminal. 13 is connected. The negative power supply voltage −Va is connected to the two transistors Qa ′ and Qb ′ of the second current mirror circuit, the B terminal is connected to the transistor Qb ′ via the transistor Qd ′, and the B terminal is shown in FIG. The third and fourth switches SW3 and SW4 shown in Fig. 2 are connected. The transistor Qa of the first current mirror circuit and the transistor Qa ′ of the second current mirror circuit are connected via two variable resistors (semi-fixed resistors) VR1 and VR2 connected in series, and the variable resistor VR2 has a predetermined resistance. A power supply voltage Vc is connected.

  In the charging bias current source 12 and the discharging bias current source 16 shown in FIG. 8, the charging bias current Ib1 is manually adjusted by the variable resistor VR1, and the discharging bias current Ib2 is manually adjusted by the variable resistor VR2, respectively. 1 offset component can be removed. However, the offset adjustment method performed using the two variable resistors VR1 and VR2 is to remove the offset component finally while repeating the variable resistors VR1 and VR2 alternately and finely adjusting, so that adjustment is generally difficult. There are some disadvantages. Moreover, in these offset adjustment methods, the offset component in the initial state can be removed. However, if the temperature changes or each constant changes over time, the offset component itself also changes slightly. Therefore, the offset adjustment method cannot cope with changes in the offset component due to temperature or drift over time. Also have.

  Therefore, in the first embodiment, as shown in FIG. 9, the average voltage of the pulse width modulation signal PWM-OUT is detected, and this average voltage is negatively fed back to the pulse width modulation circuit 1, so that the offset component is reduced. It is automatically removed.

  FIG. 9 is a block diagram showing a switching amplifier configured to remove the offset component. In this switching amplifier, an average voltage detection circuit 27 is added based on the switching amplifier shown in FIG. In the switching amplifier shown in FIG. 9, the audio signal conversion circuit 11, the charging bias current source 12, and the discharging bias current source 16 are described separately from the pulse width modulation circuit 1.

The average voltage detection circuit 27 detects the average voltage of the pulse width modulation signal PWM-OUT, and negatively feeds the average voltage to the charging bias current source 12 in the previous stage of the pulse width modulation circuit 1. The input of the average voltage detection circuit 27 is connected to the connection point of the coil L ₀ and the capacitor C ₀ of the low-pass filter circuit 3, and the average voltage detection circuit 27 is output from the switching circuit 2 by the low-pass filter circuit 3. An output voltage (an output voltage supplied to the load RL) from which a high frequency component of the output signal has been removed is input. The output of the average voltage detection circuit 27 is connected to the charging bias current source 12, and the average voltage Vco (DC component) of the output signal of the low-pass filter circuit 3 is output.

  The average voltage detection circuit 27 receives an output signal output from the switching circuit 2 (an output signal before high-frequency components are removed by the low-pass filter circuit 3) as indicated by dotted lines L1 and L2 in FIG. Alternatively, the pulse width modulation signal PWM-OUT output from the pulse width modulation circuit 1 may be input.

  FIG. 10 is a detailed circuit diagram of the average voltage detection circuit 27, where (a) shows a basic circuit and (b) shows a modified circuit in the case of inverting the output. The average voltage detection circuit 27 in FIG. 10A uses an operational amplifier OP1, and an input signal (for example, an output voltage from the low-pass filter circuit 3) is input to the negative input terminal of the operational amplifier OP1 via a current limiting resistor R1. Is entered. A predetermined reference voltage Vref3 is input to the positive input terminal of the operational amplifier OP1.

  As the reference voltage Vref3, when the input to the average voltage detection circuit 27 is an output from the low-pass filter circuit 3 or an output from the switching circuit 2, it is desirable to adopt a ground potential (0 V). In addition, when the input of the average voltage detection circuit 27 is the pulse width modulation signal PWM-OUT, it is desirable to employ a voltage value that is ½ of the amplitude of the pulse width modulation signal PWM-OUT.

A resistor R2 and a capacitor Ca are connected in parallel to the negative input terminal and output terminal of the operational amplifier OP1, respectively. The resistor R2 is for limiting the loop gain of the DC component. That is, it is desirable that the gain of the average voltage detection circuit 27 is normally designed to be sufficiently large in the DC region and the ultra-low region with respect to the signal band (usually 20 Hz to 20 kHz). The loop gain is large with respect to the voltage, and the loop gain is small (for example, 1 or less) with respect to the signal band. As a result, only the offset component can be improved without affecting the audio signal e _S.

However, if the audio signal e _S having ultra low frequency component is input, consequently it would reduce the gain for the audio signal e _S, the low frequency cut-off for the audio signal e _S by this negative feedback The values of the resistor R2 and the capacitor Ca are preferably selected so that the frequency is, for example, less than 10 Hz, usually about several Hz.

  When the average voltage detection circuit 27 requires the input of an inverted level signal due to the circuit configuration of the charging bias current source 12 connected thereto, as shown in FIG. A configuration in which an inverting circuit composed of OP2 is added may be employed.

  FIG. 11 is a detailed circuit diagram showing a modified example of the average voltage detection circuit 27, where (a) shows a basic circuit and (b) shows a modified circuit in the case of inverting the output. The average voltage detection circuit 27 ′ shown in FIG. 11 uses a CMOS inverter I1, and the average voltage detection circuit 27 ′ only receives the pulse width modulation signal PWM-OUT output from the pulse width modulation circuit 1. Used. Since the threshold voltage of the CMOS inverter I1 is normally ½ of the supplied power supply voltage, the average voltage detection circuit 27 ′ has the same power supply as the CMOS gate (not shown) that outputs the pulse width modulation signal PWM-OUT. Is used to generate an output voltage proportional to the difference between the average voltage Vco of the pulse width modulation signal PWM-OUT and the threshold voltage of the COMS inverter I1. The value of the current flowing through the charging bias current source 12 is controlled by this output voltage.

  Note that the average voltage detection circuit 27 ′ is shown in FIG. 11 (FIG. 11) when it is necessary to input an inverted level signal due to the circuit configuration of the charging bias current source 12 connected to the average voltage detection circuit 27 ′. As shown in b), an inverting circuit constituted by a CMOS inverter I2 may be added.

  12 is a detailed circuit diagram of the charging bias current source 12 and the discharging bias current source 16 applied to the switching amplifier of FIG. The charging bias current source 12 is configured by a current mirror circuit including two transistors Qa and Qb. That is, the charging bias current source 12 has substantially the same configuration as that of the first current mirror circuit shown in FIG. 8, the average voltage detection circuit 27 is connected to the transistor Qa, and the average voltage Vco is input. Further, the discharging bias current source 16 has a configuration substantially similar to that of the second current mirror circuit shown in FIG.

  According to the above configuration, if the variable resistor VR1 is manually set to the discharge bias current Ib2 to a predetermined current value (design value), the charge bias current Ib1 is automatically set to the discharge bias current Ib2. It is automatically adjusted so that the offset is always zero according to the value. If the accuracy of the circuit constant is high, manual adjustment with the variable resistor VR1 is unnecessary.

  FIG. 13 is a detailed circuit diagram showing a modification of the charging bias current source 12 and the discharging bias current source 16. In this circuit, the charging bias current source 12 and the discharging bias current source 16 are integrally configured, and the transistor Qa of the first current mirror circuit and the transistor Qa ′ of the second current mirror circuit have the variable resistor VR1. The average voltage detection circuit 27 is connected in parallel to the variable resistor VR1.

  According to the above configuration, if the charging and discharging bias currents Ib1 and Ib2 are roughly adjusted by the variable resistor VR1, the distribution of the charging and discharging bias currents Ib1 and Ib2 is automatically performed so that the offset becomes zero. It has come to be adjusted. In this case, it is desirable that the resistance value of the resistor Rb ′ connected to the average voltage detection circuit 27 is designed to be sufficiently larger than the resistance value of the resistor Rf connected to the variable resistor VR1.

  As described above, the charging bias current source 12 and the discharging bias current source 16 shown in FIGS. 12 and 13 are adopted, and the average voltage Vco from the average voltage detection circuit 27 is input to them, whereby the pulse width. The offset component in the modulation circuit 1 can be appropriately removed.

By the way, the output voltage V0 after passing through the low-pass filter circuit 3 of the switching amplifier is assumed that the modulation degree is m and the positive and negative power supply voltages output from the first power supply 4 and the second power supply 5 are + E _B and −E _B. V0 = m · E _B can be expressed. Therefore, the voltage gain A of this switching amplifier can be expressed as A = V0 / e _S = m · E _B / e _S. Thus, it can be seen that the voltage gain A is directly proportional to the power supply voltages + E _B and −E _B of the first power supply 4 and the second power supply 5. In other words, this switching amplifier has a drawback that the voltage gain A also changes when the power supply voltages + E _B and -E _B change.

FIG. 14 is a configuration diagram showing a modification of the switching amplifier shown in FIG. In this switching amplifier, in addition to the average voltage detection circuit 27 shown in FIG. 9, a voltage / current conversion circuit 28 for converting the power supply voltages + E _B and −E _B into a current, and a current converted by the voltage / current conversion circuit 28. And a bias current generating circuit 29 for generating a bias current for charging based on the above, and by these circuits, fluctuations in the power supply voltages + E _B and −E _B affect the voltage gain A of the switching amplifier. I try to suppress it.

The voltage / current conversion circuit 28 is a circuit for making the discharge bias current Ib2 proportional to the power supply voltages + E _B and −E _B. That is, referring to Equation 5 described above, it can be seen that the degree of modulation m in the pulse width modulation circuit 1 is inversely proportional to the discharge bias current Ib2. Therefore, if the discharging bias current Ib2 to be proportional to the supply voltage E _B, the power supply voltage + E _B of the first power supply 4 and the second power supply 5, also -E _B is varied, the voltage gain A accordingly Will not change. When this is expressed by a mathematical formula, Ib2 = G ′ · E _B , and G ′ indicates a converted conductance.

Here, referring to Expression 4 which is a conditional expression for zero offset, Expression 4 represents the charging bias current Ib1, and in the second term on the right side, the discharging bias current Ib2 (= G ′ -E _B ) is included. Therefore, when the power supply voltages + E _B and −E _B change, the discharging bias current Ib2 also changes. However, if the charging bias current Ib1 remains unchanged, the condition for setting the offset of Equation 4 to zero cannot be satisfied. Therefore, a new offset component is generated.

Supply voltage + E _B, variation of -E _B, the variation of the commercial AC power source itself, ripple occurs rectified, and the voltage drop due the load current is due to a variety of causes, has various frequency components. In the offset adjustment based on the negative feedback of the average voltage by the average voltage detection circuit 27, the time constant is in units of seconds, so that it cannot respond to fluctuations in the power supply voltages + E _B and −E _B. Therefore, in the present embodiment, in order to maintain the offset zero with respect to the change of the discharge bias current Ib2, a current corresponding to 1/2 of the change current of the discharge bias current Ib2 is set as the charge bias current Ib1. I am trying to change it.

The bias current generating circuit 29 is a circuit for generating a charging bias current Ib1 based on a current that is ½ of the discharging bias current Ib2. That is, referring again to Equation 4, the first term on the right side of Equation 4 corresponds to a fixed value Ib0 determined by a circuit constant that does not depend on fluctuations in the power supply voltages + E _B and −E _B. On the other hand, the second term on the right side corresponds to a value determined by a discharge bias current Ib2 that depends on fluctuations in the power supply voltages + E _B and -E _B. Therefore, with respect to the fixed value Ib0 for adjusting the offset that is the first term on the right side, a current that is 1/2 of the discharge bias current Ib2 that is proportional to the power supply voltages + E _B and −E _B that is the second term on the right side. the added value, if the charging bias current Ib1, supply voltage + E _B, even after changing the discharging bias current Ib2 depending on the variation of -E _B, it is possible to change only the fixed value Ib0, voltage The gain A is not changed, and it is possible to suppress the occurrence of a new offset component and to suppress drift due to the offset component.

FIG. 15 is a detailed circuit diagram showing an example of the voltage / current conversion circuit 28 and the bias current generation circuit 29. In the voltage / current conversion circuit 28, a plurality of transistors Qn1 to Qn4 are used, and a current mirror circuit composed of two transistors Qn5 and Qn6 is combined with them, thereby providing one of the discharge bias current Ib2 and the discharge bias current Ib2. / 2 current (Ib2 / 2) is generated. The power supply voltage + E _B to a plurality of transistors Qn1 to Qn4, by supplying -E _B, are building the power supply voltage + E _B, the relationship to proportional discharging bias current Ib2 in -E _B.

  In addition, the bias current generation circuit 29 adds a current (Ib2 / 2) that is ½ of the discharge bias current Ib2 to the fixed value Ib0 and outputs the result as a charging bias current Ib1, and the fixed value Ib0 detects the average voltage. The circuit 27 is configured to be adjusted.

FIG. 16 is a detailed circuit diagram showing another example of the voltage-current conversion circuit 28 and the bias current generation circuit 29. This circuit also has the same operation as the circuit shown in FIG. That is, by using these circuits, it is possible to prevent the voltage gain A of the switching amplifier from being affected by fluctuations in the power supply voltages + E _B and −E _B , and a new offset component by performing the treatment. Can be removed.

Second Embodiment
FIG. 17 is a block circuit diagram showing a configuration of a pulse width modulation circuit according to the second embodiment of the present invention. The pulse width modulation circuit 30 of the second embodiment corresponds to the pulse width modulation circuit 80 shown in FIG. 26 described in the background art section, and is used for the first clock signal φ1 (or the second clock signal φ2). In contrast to the pulse width modulation circuit 1 of the first embodiment in which the first and second integration capacitors C1 and C2 are charged and discharged every half cycle, the first and second integration capacitors C1 and C2 are only charged. Unlike the first embodiment, measures are taken when an excessive audio signal e _S is input.

  That is, the pulse width modulation circuit 30 includes first and second charging bias current sources 31 and 32, an audio signal conversion circuit 33, a clock generation circuit 34, a switch circuit 35, an inverter circuit 36, and a third And fourth integration circuits 37 and 38, third and fourth comparison circuits 39 and 40, third and fourth reset circuits 41 and 42, first and second RS flip-flop circuits 43 and 44, and a signal output circuit 45.

  The first and second charging bias current sources 31 and 32 convert a predetermined power supply voltage Va into a bias current Ib and supply it to the downstream third and fourth integrating circuits 37 and 38, respectively. Unlike the configuration of the first embodiment, the first and second charging bias current sources 31 and 32 are directly connected to the third and fourth integrating circuits 37 and 38 without passing through the switch circuit. Specifically, the output of the first charging bias current source 31 (see point A in FIG. 17) is connected to the third integrating circuit 37, and the output of the second charging bias current source 32 (in FIG. 17). Is connected to the fourth integration circuit 38. Accordingly, the bias current Ib generated in the first and second charging bias current sources 31 and 32 is always supplied to the third and fourth integrating circuits 37 and 38, respectively.

The audio signal conversion circuit 33 is a circuit for voltage-current conversion of the audio signal e _S supplied from the audio signal generation source AU (see FIG. 1) to the pulse width modulation circuit 1, and according to the second embodiment. Also in the audio signal conversion circuit 33, the current output from the audio signal conversion circuit 33 can be expressed by G · e _S.

  The clock generation circuit 34 is a modification of the clock generation circuit 15 according to the first embodiment, and generates a plurality of types of clock signals φ2, φ3, φ5 to φ9 based on a first clock signal φ1 serving as a reference clock. These are output to the switch circuit 35, the first and second reset circuits 21 and 22, and the signal output circuit 23, respectively.

  As shown in FIG. 18, the clock generation circuit 34 inverts the fifth clock signal φ5 in addition to the second, third, fifth and sixth clock signals φ2, φ3, φ5 and φ6 output from the clock generation circuit 15. Logic of the seventh clock signal φ7, the eighth clock signal φ8 representing the logical sum of the second clock signal φ2 and the fourth clock signal φ4, and the signal obtained by inverting the third clock signal and the fourth clock signal φ4. The ninth clock signal φ9 representing the sum is output.

  As shown in FIG. 17, the clock generation circuit 34 is connected to the switch circuit 35 and outputs a second clock signal φ 2 to the switch circuit 35. The clock generation circuit 34 is connected to the third and fourth reset circuits 41 and 42, and outputs third, fifth and eighth clock signals φ 3, φ 5 and φ 8 to the third reset circuit 41 and the fourth reset circuit 42. The second, fifth and ninth clock signals φ2, φ5 and φ9 are output respectively. The clock generation circuit 34 is connected to the first and second RS flip-flop circuits 43 and 44, and the second RS flip-flop circuit 43 receives the second clock signal φ2 and the second RS flip-flop circuit 44 receives the third clock signal φ3. Output each. The clock generation circuit 34 is connected to the signal output circuit 45 and outputs a seventh clock signal φ7.

  The clock generation circuit 34 is provided outside the pulse width modulation circuit 30, and the second, third, fifth to ninth clock signals φ2, φ3, φ5 to φ9 are respectively supplied as external clock signals to the pulse width modulation circuit 30. It may be configured to give to.

  As shown in FIG. 19, the clock generation circuit 34 includes a reference clock generation circuit 24, a first delay circuit 25, first to fifth NOT circuits N1 to N5, a second delay circuit 26, and first and second EXs. -OR circuit EX1, EX2 and 4th and 5th OR circuit O4, O5 are comprised.

  The difference from the clock generation circuit 15 will be described. The output of the first EX-OR circuit EX1 is inverted by the third NOT circuit N3 and output to the outside through the output terminal as the seventh clock signal φ7. The output of the second delay circuit 26 is connected in series with the fourth and fifth NOT circuits N4 and N5, and is connected to one input terminal of the fourth OR circuit O4. The other input terminal of the fourth OR circuit O4 is supplied with the second clock signal φ2 that is the output of the second NOT circuit N2, and the logical sum of the two is calculated and connected, and the eighth clock signal φ8 is passed through the output terminal. Output to the outside. The output of the fourth NOT circuit N4 is connected to one input terminal of the fifth OR circuit O5. The third clock signal φ3, which is the output of the first NOT circuit N1, is input to the other input terminal of the fifth OR circuit O5, and the logical sum of both is calculated and connected, and the ninth clock signal φ9 is passed through the output terminal. Output to the outside.

Returning to FIG. 17, the switch circuit 35 is switched by the third clock signal φ 3 from the clock generation circuit 34, and the current (G · e _S ) from the audio signal conversion circuit 33 is supplied to the third integration circuit 37. And a state in which the current (G · e _S ) from the audio signal conversion circuit 33 is supplied to the fourth integration circuit 38.

For example, when the third clock signal φ3 is at a high level, the switch circuit 35 is switched to the third integration circuit 37 side (see the state of the switch circuit 35 in FIG. 17), whereby the current from the audio signal conversion circuit 33 ( G · e _S ) is combined with the bias current Ib from the first charging bias current source 31 and supplied to the third integrating circuit 37. At this time, the bias current Ib from the second charging bias current source 32 is directly supplied to the fourth integrating circuit 38.

On the other hand, when the third clock signal φ3 becomes low level, the switch circuit 35 is switched to the fourth integration circuit 38 side, whereby the current (G · e _S ) from the audio signal conversion circuit 33 is used for the second charging. It is combined with the bias current Ib from the bias current source 32 and supplied to the fourth integration circuit 38. At this time, the bias current Ib from the first charging bias current source 31 is directly supplied to the third integrating circuit 37.

  The third and fourth integrating circuits 37 and 38 are constituted by integrating capacitors in the same manner as the first and second integrating circuits 17 and 18 according to the first embodiment, and the third integrating capacitor C3 and the fourth integrating capacitor. Each has C4. The first integration capacitor C1 and the second integration capacitor C2 according to the first embodiment are provided with a charge period and a discharge period for each half cycle of the first or second clock signal φ1, φ2, respectively. However, the third integration capacitor C3 and the fourth integration capacitor C4 according to the second embodiment are continuously charged in one cycle as will be described later.

  The third and fourth comparison circuits 39 and 40 have substantially the same configuration and function as the first and second comparison circuits 19 and 20 according to the first embodiment, and the third integration capacitor C3 and the fourth integration circuit. This is a circuit for defining the pulse width of the pulse width modulation signal PWM-OUT at its output by comparing the voltage at the capacitor C4 with a predetermined reference voltage Vref. The output of the third comparison circuit 39 (see point C in FIG. 20) is connected to the set terminal (S) of the first RS flip-flop circuit 43, and the output of the fourth comparison circuit 40 (see point D in FIG. 17) is The second RS flip-flop circuit 44 is connected to the set terminal (S).

  The third and fourth reset circuits 41 and 42 force the charging states of the third and fourth integration capacitors C3 and C4 during the period when the third and fourth integration capacitors C3 and C4 are charged, respectively. It is a circuit for terminating (resetting). The third reset circuit 41 includes a third NOR circuit N3, a second AND circuit A2, a first OR circuit O1, and a seventh switch SW7. The fourth reset circuit 42 includes a fourth NOR circuit N4, a fourth AND circuit A4, and a second OR circuit O2. And an eighth switch SW8.

  The third NOR circuit NR3 of the third reset circuit 41 has one input terminal connected to the Q (/) terminal (see point E in FIG. 17) of the first RS flip-flop circuit 43, and the other input terminal connected to the clock generation circuit. 34, the eighth clock signal φ8 is input. The second AND circuit A2 has both input terminals connected to the clock generation circuit 34, and receives the third clock signal φ3 and the fifth clock signal φ5, respectively. The output terminals of the third NOR circuit NR3 and the second AND circuit A2 are connected to the input terminal of the first OR circuit O1, respectively. The output terminal of the first OR circuit O1 (see point I in FIG. 17) is connected to the seventh switch SW7, and the output of the first OR circuit O1 controls the on / off operation of the seventh switch SW7.

  On the other hand, the fourth NOR circuit N4 of the fourth reset circuit 42 has one input terminal connected to the Q (/) terminal (see point F in FIG. 17) of the second RS flip-flop circuit 44, and the other input terminal clocked. The ninth clock signal φ9 is input by being connected to the generation circuit. The fourth AND circuit A4 has both input terminals connected to the clock generation circuit 34, and receives the second clock signal φ2 and the fifth clock signal φ5, respectively. The output terminals of the fourth NOR circuit NR4 and the fourth AND circuit A4 are connected to the input terminal of the second OR circuit O2, respectively. The output terminal of the second OR circuit O2 (see point J in FIG. 17) is connected to the eighth switch SW8, and the output of the second OR circuit O2 controls the on / off operation of the eighth switch SW8.

  The first RS flip-flop circuit 43 is a circuit for holding the output of the first comparison circuit 39 for a predetermined period. The first RS flip-flop circuit 43 is configured by combining the fifth and sixth NOR circuits NR5 and NR6. In the first RS flip-flop circuit 43, each output terminal of the fifth and sixth NOR circuits NR5 and NR6 is one of the other. Connected to the input terminal. The other input terminals of the fifth and sixth NOR circuits NR5 and NR6 are connected to the ground terminal via the resistors R5 and R6, respectively, and are normally maintained at a low level.

  The other input terminal of the fifth NOR circuit NR5 is a terminal to which the set signal (S) is input as an RS flip-flop, and the other input terminal of the sixth NOR circuit NR6 is an input to the reset signal (R) as an RS flip-flop. Terminal. The output terminal of the fifth NOR circuit NR5 corresponds to the Q (/) terminal of the RS flip-flop, and the output terminal of the sixth NOR circuit NR6 corresponds to the Q terminal of the RS flip-flop.

  The other input terminal of the fifth NOR circuit NR5 is connected to the output terminal of the first comparison circuit 39, and the other input terminal of the sixth NOR circuit NR6 is connected to the clock generation circuit 34, so that the second clock signal φ2 Is entered.

  The second RS flip-flop circuit 44 is a circuit for holding the output of the second comparison circuit 40 for a predetermined period. The second RS flip-flop circuit 44 is configured by combining the seventh and eighth NOR circuits NR7 and NR8, and has substantially the same configuration as the first RS flip-flop circuit 43. The other input terminal of the eighth NOR circuit NR8 is connected to the clock generation circuit 34 and receives the third clock signal φ3.

  The signal output circuit 45 includes a third OR circuit O3 and a first NAND circuit NA1, and an input terminal of the third OR circuit O3 includes an output terminal (Q terminal) of the sixth NOR circuit NR6 of the first RS flip-flop circuit 43 and a second RS. The output terminal (Q terminal) of the eighth NOR circuit NR8 of the flip-flop circuit 44 is connected. The output terminal of the third OR circuit O3 is connected to one input terminal of the first NAND circuit NA1, and the other input terminal is connected to the clock generation circuit 34 to receive the fifth clock signal φ5. The output terminal of the first NAND circuit NA1 outputs the pulse width modulation signal PWM-OUT.

Next, the operation of the pulse width modulation circuit 30 will be described with reference to the timing chart shown below. First, in FIG. 20, a case where the pulse width modulation circuit 30 operates properly (when the audio signal e _S is negative (0 <G · e _S <Ib / 2)) will be described. Next, in FIG. The case where the signal e _S is a negative excessive signal (G · e _S ≦ −Ib / 2) and the case where the audio signal e _S is a positive excessive signal (G · e _S ≧ Ib / 2) in FIG. 22 will be described. To do.

In the first period T1 in FIG. 20, the second clock signal φ2 from the clock generation circuit 34 is at a high level, whereby the switch circuit 35 is switched to the third integration circuit 37 side. Therefore, the bias current Ib from the first charging bias current source 31 and the current (G · e _S ) from the audio signal conversion circuit 33 are synthesized in the third integrating capacitor C3 of the third integrating circuit 37. The sum current (Ib + G · e _S ) is supplied, whereby the third integrating capacitor C3 is charged (see waveform at point A).

  In the first period T1, since the switch circuit 35 is switched to the third integration circuit 37 side, the fourth integration capacitor C4 of the fourth integration circuit 38 has a bias from the second charging bias current source 32. The current Ib is supplied, and the fourth integrating capacitor C4 is charged with a constant charge amount by the bias current Ib (see waveform at point B).

  When the voltage resulting from charging of the fourth integration capacitor C4 in the fourth comparison circuit 40 reaches the reference voltage Vref, the output of the fourth comparison circuit 40 instantaneously changes from low level to high level (see waveform at point D). ). Since the output of the fourth comparison circuit 40 is input to the set terminal (S) of the second RS flip-flop circuit 44, the Q (/) terminal of the second RS flip-flop circuit 44 is set from high level to low level. The

  The Q (/) terminal of the second RS flip-flop circuit 44 is connected to one input terminal of the fourth NOR circuit N4 of the fourth reset circuit 42, and the other input terminal of the fourth NOR circuit N4 is connected to the inverter circuit 36. Since the low level (the third clock signal φ3 is the high level) is input, the output of the fourth NOR circuit N4 changes from the low level to the high level (see the waveform at point J), and this reset signal is sent to the eighth switch SW8. Is output.

  As a result, the eighth switch SW8 changes from the OFF operation to the ON operation, and the charge stored in the fourth integrating capacitor C4 flows to the ground terminal via the eighth switch SW8, and is discharged forcibly and at once. Is called.

  The output (refer to the waveform at point H) of the Q terminal of the second RS flip-flop circuit 44 is input to the ninth NOR circuit N9 and output as the pulse width modulation signal PWM-OUT.

Next, in the period of the second period T2, the third clock signal φ3 from the clock generation circuit 34 changes from the high level to the low level, whereby the switch circuit 35 is switched to the fourth integration circuit 38 side. For this reason, the sum current (Ib + G · e _S ) is supplied to the fourth integrating capacitor C4 of the fourth integrating circuit 38, whereby the fourth integrating capacitor C4 is charged (see waveform B).

  In the second period T2, since the switch circuit 35 is switched to the fourth integrating circuit 38 side, the third integrating capacitor C3 of the third integrating circuit 37 has a bias from the first charging bias current source 31. Only the current Ib is supplied, and the third integrating capacitor C3 is charged with a constant charge amount by the bias current Ib (see waveform at point A).

  In the second period T2, when the voltage resulting from charging of the third integrating capacitor C3 in the third comparison circuit 39 reaches the reference voltage Vref, the output of the third comparison circuit 39 instantaneously changes from the low level to the high level. (See waveform at point C). Since the output of the third comparison circuit 39 is input to the set terminal (S) of the first RS flip-flop circuit 43, the Q (/) terminal of the first RS flip-flop circuit 43 is set from the high level to the low level. (Refer to point E waveform).

  The Q (/) terminal of the first RS flip-flop circuit 43 is connected to one input terminal of the third NOR circuit N3 of the third reset circuit 41, and the other input terminal of the third NOR circuit N3 is connected to the clock generation circuit 34. Since the third clock signal φ3 (low level in the second period T2) is input, the output of the third NOR circuit N3 changes from the low level to the high level (refer to the waveform at the point I). 7 is output to the switch SW7.

  As a result, the seventh switch SW7 changes from the OFF operation to the ON operation, and the charge stored in the third integrating capacitor C3 flows to the ground terminal via the seventh switch SW7, and is discharged forcibly and at once. Is called.

  The output of the Q terminal of the first RS flip-flop circuit 43 (see waveform at point G) is input to the ninth NOR circuit N9 and output as the pulse width modulation signal PWM-OUT.

Thereafter, in the third period T3, since the third clock signal φ3 is inverted, the third integration capacitor C3 is charged according to the amplitude of the audio signal e _S , while the fourth integration capacitor C4 is biased. Charging according to the current Ib is performed. Thereafter, every time a half cycle elapses, the third clock signal φ3 is inverted, and the third and fourth integration capacitors C3 and C4 are charged according to the amplitude of the audio signal e _S and charged according to the bias current Ib. Repeated alternately.

Here, a case where the audio signal e _S is a negative excessive signal as shown in FIG. 21 will be described. In the first period T1, the third integrating capacitor C3 is charged based on the sum current (G · e _S + Ib), and in the second period T2, it is charged based on the bias current Ib. Then, when the voltage of the third integrating capacitor C3 reaches the reference voltage Vref, a reset is applied. In the conventional configuration, when the audio signal e _S is a negative excessive signal, the charge amount in the third integrating capacitor C3 does not reach the reference voltage Vref, and the second period T2 ends without being reset as it is. Then, the charge shifts to the next third period T3 with the electric charge remaining, and the next charging is performed. Therefore, an error is given to the pulse width of the pulse width modulation signal PWM-OUT. There was a thing.

  In the present embodiment, the residual charge of the fourth integrating capacitor C4 is forcibly reset by the fifth clock signal φ5 having the pulse width of the period ΔT that is turned on immediately before the end of the first period T1.

In the first period T1, since the second clock signal φ2 is at the high level, the switch circuit 35 is switched to the third integration capacitor C3 side, whereby the sum current (G · e _S + Ib) is changed to the third integration capacitor C3. The capacitor C3 is supplied, and the third integrating capacitor C3 is charged (see waveform at point A). At this time, since the audio signal e _S is a negative excessive signal, the voltage waveform at the point A is inclined to the minus side.

  Next, in the second period T2, since the second clock signal φ2 changes from the high level to the low level, the switch circuit 35 is switched to the fourth integration capacitor C4 side. As a result, only the bias current Ib from the first charging bias current source 31 is supplied to the third integrating capacitor C3, and the third integrating capacitor C3 is charged with a constant charge amount by the bias current Ib. (Refer to point A waveform). At this time, since the charge charged in the third integrating capacitor C3 in the first period T1 has been charged to the minus side, when the second period T2 is started, charging is started from a minus voltage.

  Here, immediately before the end of the second period T2, the ON signal of the fifth clock signal φ5 is input to one input terminal of the second AND circuit A2 of the third reset circuit 41. Since the third clock signal φ3 is input to the other input terminal of the second AND circuit A2, the operation result of the logical product of both is output from the second AND circuit A2. This output signal is output as a reset signal to the seventh switch SW7 via the first OR circuit O1 to turn on the seventh switch SW7.

  As the seventh switch SW7 is turned on, the third integrating capacitor C3 is immediately and forcibly discharged (reset). As a result, the residual charge in the third integrating capacitor C3 disappears, and charging is performed from the charge 0 in the next third period T3.

  The outputs of the Q terminal of the first RS flip-flop circuit 43, the Q terminal of the second RS flip-flop circuit 44, and the sixth clock signal φ6 are input to the third OR circuit O3 of the signal output circuit 45. The output of the Q terminal of the first RS flip-flop circuit 43 is maintained at a low level (see waveform at point G), but an ON signal is input immediately after the start of the third period T3 continued by the sixth clock signal φ6. The signal is inverted by the first NAND circuit NA1 and output as it is as the pulse width modulation signal PWM-OUT.

On the other hand, the fourth integration capacitor C4 will be described. In the second period T2, the switch circuit 35 is switched to the fourth integration capacitor C4 side, whereby the sum current (G · e _S + Ib) is changed to the fourth integration capacitor C4. The fourth integration capacitor C4 is charged by being supplied to the capacitor C4 (see waveform at point B). In the next third period T3, only the bias current Ib from the second charging bias current source 32 is supplied and charged with a constant charge amount. However, immediately before the end of the third period T3, Since the eighth switch SW8 is turned on by the 5-clock signal φ5, the fourth integrating capacitor C4 is forcibly discharged.

  As described above, the ON signal output immediately before the end of each period Tn of the fifth clock signal φ5 is generated by forcibly resetting the third and fourth integration capacitors C3 and C4. The capacitor C3, C4 has a function of setting the electric charge to zero. Therefore, it is possible to prevent charging in the next period with the charge remaining on the minus side as in the conventional configuration.

Further, when the audio signal e _S is a negative excessive signal (G · e _S ≦ −Ib / 2), the audio signal e _S is used by using the sixth clock signal φ 6 as the pulse width modulation signal PWM-OUT. The pulse width modulation signal PWM-OUT when is a negative excessive signal is forcibly generated. Thereby, the pulse width can be accurately modulated in the next period.

Next, with reference to FIG. 22, the case where the audio signal e _S is a positive excessive signal will be described. In the first period T1, the third integration capacitor C3 is charged. However, since the audio signal e _S is a positive excessive signal, the third integration capacitor C3 is charged exceeding the reference voltage Vref that is not reached. Is done. Here, when the eighth clock signal φ8 is inverted from the high level to the low level, the seventh switch SW7 is turned on, the third integrating capacitor C3 is reset, and the third integrating capacitor C3 is instantaneously discharged. Is done.

  Since the seventh switch SW7 continues the on operation until the eighth clock signal φ8 is inverted from the low level to the high-low level, the third integration capacitor C3 is maintained in the reset state. That is, when the eighth clock signal φ8 is at a low level, charging of the third integrating capacitor C3 is prohibited. Similarly, the fourth integration capacitor C4 is prohibited from being charged and discharged when the ninth clock signal φ9 is at a low level.

  In the signal output circuit 45, the seventh clock signal φ7, which is an inverted signal of the fifth clock signal φ5, is input to the first NAND circuit NA1, and the seventh clock signal φ7 is output as the pulse width modulation signal PWM-OUT. .

  As described above, the third and fourth integration capacitors C3 and C4 are forcibly reset by the eighth and ninth clock signals φ8, thereby reducing the charges of the capacitors C3 and C4 in the next period to zero. Can do. Therefore, it is possible to prevent charging in the next period with the charge remaining on the minus side as in the conventional configuration.

When the audio signal e _S is a positive excessive signal (G · e _S ≦ −Ib / 2), the audio signal e _S is used by using the seventh clock signal φ7 as the pulse width modulation signal PWM-OUT. The pulse width modulation signal PWM-OUT when is a positive excessive signal is forcibly generated. Thereby, the pulse width can be accurately modulated in the next period.

Note that, also in the pulse width modulation circuit 30 according to the second embodiment, an offset component, which is a problem in the pulse width modulation circuit 1 according to the first embodiment, is generated, so that the average voltage detection shown in the first embodiment is performed. The offset component may be removed by applying the circuit 27. The power supply voltage + E _B, by applying a voltage to current converter circuit 28 and a bias current generating circuit 29 and the like for proportional discharging bias current Ib2 in -E _B, the power supply voltage + E _B, effect on the variation of -E _B You may make it suppress.

  Of course, the scope of the present invention is not limited to the above-described embodiment, and the circuit configurations shown in the first and second embodiments are examples, and various circuits can be used as long as they have equivalent functions. Can be applied.

1 is a configuration diagram illustrating a switching amplifier to which a pulse width modulation circuit according to a first embodiment of the present invention is applied. FIG. 2 is a block circuit diagram illustrating an embodiment of the pulse width modulation circuit illustrated in FIG. 1. 6 is a timing chart of first to sixth clock signals. It is a figure which shows the circuit structure of a clock generation circuit. It is a timing chart which shows the relationship between a 2nd, 3rd, 5th, 6th clock signal and the voltage waveform in each point of a pulse width modulation circuit when a pulse width modulation circuit operates appropriately. It is a timing chart which shows the relationship between a 2nd, 3rd, 5th, 6th clock signal and the voltage waveform in each point of a pulse width modulation circuit when an audio signal is a positive excessive signal. It is a timing chart which shows the relationship between a 2nd, 3rd, 5th, 6th clock signal and the voltage waveform in each point of a pulse width modulation circuit when an audio signal is a negative excessive signal. It is a figure which shows an example of the circuit structure of the bias current source for charge, and the bias current source for charge. It is a block diagram which shows a switching amplifier. It is a detailed circuit diagram of an average voltage detection circuit, (a) shows a basic circuit, (b) shows a modified circuit in the case of inverting an output. It is a detailed circuit diagram which shows the modification of an average voltage detection circuit, (a) shows a basic circuit, (b) shows the modification circuit in the case of inverting an output. It is a detailed circuit diagram of a bias current source for charging and a bias current source for discharging. It is a detailed circuit diagram which shows the modification of the bias current source for charge, and the bias current source for discharge. It is a block diagram which shows the switching amplifier of a modification. It is a detailed circuit diagram showing an example of a voltage-current conversion circuit and a bias current generation circuit. It is a detailed circuit diagram which shows another example of a voltage current conversion circuit and a bias current generation circuit. It is a block circuit diagram showing an example of the pulse width modulation circuit according to the second embodiment of the present invention. 10 is a timing chart of first to ninth clock signals. It is a figure which shows the circuit structure of a clock generation circuit. 10 is a timing chart showing a relationship between second to seventh clock signals and voltage waveforms at respective points of the pulse width modulation circuit when the pulse width modulation circuit operates properly. 10 is a timing chart showing the relationship between the second to seventh clock signals and the voltage waveform at each point of the pulse width modulation circuit when the audio signal is a negative excessive signal. 10 is a timing chart showing a relationship between second to seventh clock signals and voltage waveforms at respective points of the pulse width modulation circuit when the audio signal is a positive excessive signal. It is a block diagram which shows the switching amplifier with which the conventional pulse width modulation circuit is applied. It is a circuit diagram which shows the conventional pulse width modulation circuit. It is a figure which shows the output waveform in each point of the conventional pulse width modulation circuit. It is a circuit diagram which shows the other conventional pulse width modulation circuit. It is a figure which shows the output waveform in each point of the other conventional pulse width modulation circuit. It is a figure which shows the voltage waveform in each point of a pulse width modulation circuit in case the audio signal is a positive excessive signal in the conventional pulse width modulation circuit. It is a figure which shows the voltage waveform in each point of a pulse width modulation circuit in case the audio signal is a negative excessive signal in the conventional pulse width modulation circuit. It is a figure which shows the voltage waveform in each point of a pulse width modulation circuit in case the audio signal is a negative excessive signal in the other conventional pulse width modulation circuit. It is a figure which shows the voltage waveform in each point of a pulse width modulation circuit in case the audio signal is a positive excessive signal in the other conventional pulse width modulation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pulse width modulation circuit 2 Switching circuit 3 Low pass filter circuit 4 1st power supply 5 2nd power supply 11 Audio signal conversion circuit 12 Charging bias current source 13 Current addition circuit 14 Switch circuit 15 Clock generation circuit 16 Discharge bias current source 17 1 integration circuit 18 second integration circuit 19 first comparison circuit 20 second comparison circuit 21 first reset circuit 22 second reset circuit 23 signal output circuit 30 pulse width modulation circuit 31 first charging bias current source 32 second charging Bias current source 33 Audio signal conversion circuit 34 Clock generation circuit 35 Switch circuit 37 Third integration circuit 38 Fourth integration circuit 39 Third comparison circuit 40 Fourth comparison circuit 41 Third reset circuit 42 Fourth reset circuit 43 First RS flip-flop Circuit 44 Second RS flip-flop circuit 45 Signal output Circuit C1 First integration capacitor C2 Second integration capacitor AU Audio generation source e _S Audio signal Ib Bias current T1 First period T2 Second period T3 Third period Vref Reference voltage φ1 First clock signal φ2 Second clock signal φ3 Third clock signal φ4 Fourth clock signal φ5 Fifth clock signal φ6 Sixth clock signal φ7 Seventh clock signal φ8 Eighth clock signal φ9 Ninth clock signal

Claims (7)

In a first period that is a half cycle of a predetermined clock signal, the first integration circuit is charged based on a current based on an input signal, and in a second period following the first period that is shifted from the first period by a half cycle. The charging voltage accumulated in the first integrating circuit is changed based on a constant bias current, and a second integrating circuit different from the first integrating circuit is changed based on the current based on the input signal in the second period. An integration control circuit for charging and changing a charging voltage accumulated in the second integration circuit based on a constant bias current in a third period following the second period;
A first detection circuit for detecting a time from when the second period starts until the voltage in the first integration circuit reaches a predetermined reference voltage;
A second detection circuit that detects a time from when the third period starts until the voltage in the second integration circuit reaches a predetermined reference voltage;
A pulse based on the time detected by the first detection circuit and the time detected by the second detection circuit, which the first detection circuit and the second detection circuit repeatedly output alternately every half cycle of the clock signal. A pulse width modulation circuit comprising a pulse width generation circuit for generating a width,
A pulse generation circuit that generates a first pulse signal that is output immediately before each period is switched;
When the input signal is excessive and the voltage in the first integration circuit does not reach a predetermined reference voltage in the second period, the input signal is generated based on the first pulse signal generated by the pulse generation circuit. When the voltage charged in the first integration circuit is forcibly discharged and the input signal is excessive, and the voltage in the second integration circuit does not reach a predetermined reference voltage in the third period, A discharge control circuit for forcibly discharging the voltage charged in the second integration circuit based on the first pulse signal generated by the pulse generation circuit;
A pulse width modulation circuit comprising: The pulse generation circuit includes:
A second pulse signal that is output immediately after each period is switched,
The pulse width generation circuit includes:
When the input signal is excessive and the voltage in the first integration circuit does not reach a predetermined reference voltage in the second period, the second pulse signal generated by the pulse generation circuit is subjected to pulse width modulation. The second signal generated by the pulse generation circuit when the input signal is excessive and the voltage in the second integration circuit does not reach a predetermined reference voltage in the third period. The pulse width modulation circuit according to claim 1, wherein the pulse signal is output as a pulse width modulation signal. The first detection circuit includes:
A first comparison circuit that compares the charging voltage accumulated in the first integration circuit in the second period with a predetermined reference voltage;
The second detection circuit includes:
A second comparison circuit that compares the charging voltage accumulated in the second integration circuit in the third period with a predetermined reference voltage;
The discharge control circuit includes:
A first discharge circuit for forcibly discharging a charge voltage accumulated in the first integration circuit based on an output of the first comparison circuit or the first pulse signal;
A second discharge circuit for forcibly discharging the charge voltage accumulated in the second integration circuit based on the output of the second comparison circuit or the first pulse signal;
The pulse width modulation circuit according to claim 1, further comprising: The integration control circuit includes:
A first discharge circuit for discharging with a constant discharge amount based on a constant bias current in the second period;
A second discharge circuit for discharging with a constant discharge amount based on a constant bias current in the third period;
The pulse width modulation circuit according to claim 1, comprising: The integration control circuit includes:
A first charging circuit for charging the first integrating circuit at a constant rate based on a constant bias current in the second period;
A second charging circuit for charging the second integrating circuit at a constant rate based on a constant bias current in the third period;
The pulse width modulation circuit according to claim 1, comprising: A pulse width modulation circuit according to any one of claims 1 to 5,
A voltage source that outputs a predetermined power supply voltage;
A switching circuit for switching a predetermined power supply voltage supplied from the voltage source based on a modulation signal output from the pulse width modulation circuit,
The integration control circuit includes:
A bias current generating circuit for generating a constant bias current to be supplied to the first integrating circuit and the second integrating circuit;
A switching amplifier, further comprising an average voltage detection circuit that detects an average voltage of an amplitude of a modulation signal output from the pulse width modulation circuit and outputs the average voltage to the bias current generation circuit. .   The switching amplifier according to claim 6, further comprising a current proportional circuit that causes a bias current generated by the bias current generation circuit to be proportional to the power supply voltage output from the voltage source.

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