JP5234032B2 - Pulse width modulation circuit and switching amplifier using the same - Google Patents

Description

  The present invention relates to a pulse width modulation circuit that outputs, for example, a pulse width modulation (PWM) of an audio signal and a switching amplifier using the pulse width modulation circuit.

  2. Description of the Related Art Conventionally, switching amplifiers used for audio amplifiers have been proposed that use a pulse width modulation circuit that modulates an audio signal as an input signal, for example, and outputs the modulated signal. In this switching amplifier, a predetermined power supply voltage is switched based on the modulation signal output from the pulse width modulation circuit, and the switched output signal is output to a load (for example, a speaker) through, for example, a low-pass filter.

FIG. 8 is a block diagram showing an example of a conventional switching amplifier. The switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, positive and negative power supply voltage + E _B, the first power supply 4 and supplies -E _B A second power source 5 is provided. A speaker as a load RL is connected to the low-pass filter circuit 3.

In the pulse width modulation circuit 1, the modulation signal PWMout is generated by performing pulse width modulation on the audio signal e _S as the input signal output from the audio signal generation source AU. In the switching circuit 2, a modulation signal PWMout ′ having a phase opposite to that of the modulation signal PWMout is generated.

Switching elements SW-A and the switching element series circuit of SW-B between the second power source 5 for supplying a first power source 4 and the negative supply voltage -E _B supplies positive In the switching circuit 2 supply voltage + E _B Is connected. In the switching circuit 2, the on / off operation of the switch elements SW-A and SW-B is controlled based on the modulation signal PWMout and the modulation signal PWMout ′, whereby the power supply voltages + E _B and −E _B are alternately switched to the low-pass filter circuit. 3 is output. This output has a high-frequency component removed by a low-pass filter circuit 3 composed of an L-type circuit of a coil L ₀ and a capacitor C ₀ , and the output (amplified audio signal) of the low-pass filter circuit 3 is supplied to a load RL (speaker). Is output as sound.

For example, Patent Document 1 proposes a pulse width modulation circuit that generates a PWM modulation signal based on the audio signal e _S. In this pulse width modulation circuit, a PWM modulation signal is generated based on the following principle.
(1) The level of the audio signal e _S (voltage signal) is sampled at a predetermined period T.
(2) The sampled voltage value is converted into a current value, and the capacitor is charged with the current value for a period of T / 2 (charging period).
(3) After the charging operation in the charging period of T / 2, the accumulated charge of the capacitor is discharged for a time of T / 2 with a constant current value.
(4) A pulse signal is generated with the discharge time of the capacitor as a high level period. In this case, when the charging voltage of the capacitor is high, the discharge time (time for discharging the accumulated charge) within the period for performing the discharge operation (T / 2 discharge period) becomes longer, and the pulse width becomes longer. On the other hand, when the charging voltage of the capacitor is low, the discharge time within the discharge period is shortened and the pulse width is shortened.
(5) The above charging / discharging operation is performed for two capacitors, and the respective pulse signals are generated by shifting these charging / discharging operations by a time of T / 2, and the PWM modulation signal is generated by synthesizing both. Generate.

  FIG. 9 is a functional block diagram of the pulse width modulation circuit proposed in Patent Document 1. In FIG.

  As shown in FIG. 1, the pulse width modulation circuit 1 includes a clock generation circuit 100, a voltage-current conversion circuit 101, first and second capacitors C1 and C2, a switch circuit 102, and a discharging constant current circuit 103. , First and second pulse generation circuits 104 and 105, and a pulse synthesis circuit 106. The switch circuit 102 includes first and second switch sections 102a and 102b each having two switches.

The voltage-current conversion circuit 101 converts the audio signal e _S (voltage signal) supplied from the audio signal generation source AU (see FIG. 8) into a current signal whose current value is proportional to the amplitude of the audio signal e _S. The clock generation circuit 100 generates a first control signal φ1 composed of a pulse signal with a period T and a duty ratio of 50%, and a second control signal φ2 in which a high level and a low level are opposite to the first control signal φ1. To do. The on / off operation of one switch (switch connected to the voltage-current conversion circuit 101) in the first switch unit 102a is controlled by the first control signal φ1, and one switch (voltage) in the second switch unit 102b. The on / off operation of the switch connected to the current conversion circuit 101 is controlled by the second control signal φ2.

  When one switch in the first switch unit 102a is turned on, the first capacitor C1 is charged by the current signal output from the voltage-current conversion circuit 101, and when one switch in the second switch unit 102b is turned on. The second capacitor C2 is charged by the current signal output from the voltage-current conversion circuit 101.

  The first pulse generation circuit 104 includes a pulse signal rsout1 whose pulse width is a discharge time until the first capacitor C1 changes from a level at the start of discharge to a predetermined reference level, and the other switch in the first switch unit 102a. A third control signal φ3 for controlling the on / off operation of the switch connected to the discharge constant current circuit 103 is generated. The second pulse generation circuit 105 includes a pulse signal rsout2 whose pulse width is a discharge time until the second capacitor C2 changes from the level at the start of discharge to the reference level, and the other switch in the second switch unit 102b. A fourth control signal φ4 for controlling the on / off operation of the switch connected to the discharge constant current circuit 103 is generated.

  The third control signal φ3 is a pulse signal in which a high level period occurs within the low level period of the first control signal φ1. When the other switch in the first switch section 102a is turned on, the electric charge accumulated in the first capacitor C1 is discharged with a constant current by the discharging constant current circuit 103. The fourth control signal φ4 is a pulse signal in which a high level period occurs within the low level period of the second control signal φ2. When the other switch in the second switch section 102b is turned on, the electric charge accumulated in the second capacitor C2 is discharged with a constant current by the discharging constant current circuit 103.

Therefore, the first capacitor C1 is charged during the low level period (T / 2) of the first control signal φ1, and during the subsequent high level period (T / 2), the third control signal φ3 becomes the low level. The accumulated charge is discharged. Similarly, the second capacitor C2 is charged during the low level period (T / 2) of the second control signal φ2, and the period during which the fourth control signal φ4 becomes high level during the subsequent high level period (T / 2). The accumulated charge is discharged.

  The first control signal φ1 and the second control signal φ2 have the high level period and the low level period opposite to each other, the charging period of the first capacitor C1 becomes the discharging period of the second capacitor C2, and the discharging of the first capacitor C1 Since the period is the charging period of the second capacitor C2, the first capacitor C1 and the second capacitor C2 are alternately charged and discharged.

The pulse signal rsout 1 output from the first pulse generation circuit 104 and the pulse signal rsout 2 output from the second pulse generation circuit 105 are combined by the pulse combining circuit 106. The pulse signal rsout1 output from the first pulse generation circuit 104 is a signal that becomes a high level only during the period T during which the first capacitor C1 discharges the accumulated charge, and the pulse signal output from the second pulse generation circuit 105. rsout2 is a signal that is shifted to the pulse signal rsout1 output from the first pulse generation circuit 104 by T / 2 and is at a high level only for a period of time during which the second capacitor C2 discharges the accumulated charge in the period T. Therefore, in the pulse synthesis circuit 106, the pulse signal rsout1 output from the first pulse generation circuit 104 and the pulse signal rsout2 output from the second pulse generation circuit 105 at T / 2 are alternately synthesized (the modulation signal PWMout). Equivalent) is output.

In the above configuration, the first and second switch portions 102a and 102b for controlling the charging and discharging operations of the first capacitor C1 and the second capacitor C2 are required for the capacitors C1 and C2, respectively. On the other hand, the voltage-current conversion circuit 101 and the discharge constant current circuit 103 are charged and discharged with the first and second capacitors C1, C2 shifted by T / 2, so that the voltage-current conversion circuit 101 and the discharge constant current circuit 103 are charged. The current circuit 103 is shared.

  The block configuration diagram shown in FIG. 9 shows the necessary and sufficient block configuration as simplified as possible on the principle of generation of the PWM modulation signal, but the PWM modulation circuit is based on the block configuration shown in FIG. A specific circuit for realizing the circuit is as shown in FIG. 10, for example.

In FIG. 10, the operational amplifier 101a to which the audio signal e _S is input, the pnp transistor 101b connected to the output, the constant voltage diode 101c connected to the base terminal, and the like are voltage-current. This corresponds to the conversion circuit 101. Further, a portion constituted by two analog switch ICs corresponds to the switch circuit 102, an npn transistor 103a connected to the switches SW3 and SW4 of the analog switch, a constant voltage diode 103b connected to the base terminal, and the like. Corresponds to the discharge constant current circuit 103.

  The specific circuit shown in FIG. 10 has a disadvantage that the circuit configuration is complicated and various problems are likely to occur in terms of circuit space and manufacturing cost. For example, the specific circuit shown in FIG. 10 has the following problems.

(1) In order to make the voltage-current conversion circuit 101 common, a circuit configuration using an operational amplifier increases the number of parts constituting the voltage-current conversion circuit 101.
(2) By using the analog switch IC, the circuit space of the switch circuit 102 can be made more efficient, but the manufacturing cost increases.
(3) Since the voltage-current conversion circuit 101, the switch circuit 102, and the discharge constant current circuit 103 are configured in units of blocks and connected to each other, the power supply voltages of the respective circuits are different, and a plurality of types of power supplies (In FIG. 10, four types of + 14.6v, -14.6v, + 3v, and -3v) are required, and the circuit becomes complicated.

JP 2008-206128 A

  The present invention has been conceived under the circumstances described above, and is provided with a pulse generation circuit having the same configuration for generating two pulse signals, and voltage-current conversion constituting each pulse generation circuit. The present invention provides a pulse width modulation circuit capable of reducing the circuit space and manufacturing cost described above by simplifying a circuit, a switch circuit, and a constant current circuit for discharging, and a switching amplifier to which the pulse width modulation circuit is applied. Let it be an issue.

First pulse width modulation circuit that is provided by the aspect of the present invention includes a first control signal of order to execute the charging operation on one level period of the reference clock, on the other level period of the reference clock the second control signal and the charge control signal generator for generating a first time period of the other level following the period of one level the charging operation is executed by the control signals of the order to execute the charging operation, the the third control signal and said second control signal by one level period subsequent to the period of the other levels of the charging operation is executed in order to execute the discharging operation of the charge accumulated in the charging operation, the charging It is generated based on the level of the input signal in response to the discharge control signal generator for generating a fourth control signal in order to execute the discharging operation of the charge accumulated in the operation, the first control signal Charge current Ri and charging operation for charging the first capacitor, the charge accumulated in the first capacitor performs a discharge operation of discharging at a constant discharge current in response to said third control signal, it executes the discharge operation A first pulse signal generator for generating a first pulse signal having a pulse width as a discharge time until the first capacitor changes from a level at the start of discharge to a reference level during each period of time, A charging operation for charging the second capacitor with the charging current according to the control signal of 2, and a discharging operation for discharging the accumulated charge of the second capacitor with the discharge current according to the fourth control signal. run, the said second capacitor in each period running the discharging operation to generate a second pulse signal having a pulse width discharge time from the level at the start of the discharge until the changes to the reference level Of the pulse signal generating unit, combines the second pulse signal generated by said first pulse signal and the second pulse signal generator which is generated by the first pulse signal generator, of each pulse A pulse width modulation circuit comprising: a pulse signal synthesizer that outputs a pulse width modulation signal whose pulse width varies according to the level of the input signal, wherein the first pulse signal generation unit includes the input signal A differential amplifier circuit that amplifies the voltage of the first capacitor, a first control circuit that is connected between a pair of power supply terminals of the differential amplifier circuit, and controls a charge / discharge operation of the first capacitor; and the first capacitor A first pulse signal generation circuit that generates the first pulse signal based on a voltage between both ends of the first voltage signal, and the first control circuit generates a current corresponding to the voltage output from the differential amplifier circuit. First generated as the charging current And a first switch circuit for controlling the charging operation of the first capacitor by the charging current generated by the first charging current generating circuit by the first control signal. Circuit, a first constant current circuit for generating a constant current as the discharge current, and a discharge operation of the first capacitor by a discharge current generated by the first constant current circuit according to the third control signal The second switch circuit to be controlled is connected in series with a second series circuit, and the connection point is connected to the first capacitor, and the second pulse signal generator is configured to connect the difference between the second switch circuit and the second switch circuit. A second control circuit that shares a dynamic amplifier circuit with the first pulse signal generation unit, is connected between a pair of power supply terminals of the differential amplifier circuit, and controls a charge / discharge operation of the second capacitor; Of the second capacitor A second pulse signal generation circuit that generates the second pulse signal based on an end voltage, and the second control circuit supplies a current corresponding to a voltage output from the differential amplifier circuit. A second charging current generation circuit that generates a charging current, and a third switch that controls the charging operation of the second capacitor by the charging current generated by the second charging current generation circuit by the second control signal A third series circuit with the circuit, a second constant current circuit for generating a constant current as the discharge current, and a discharging operation of the second capacitor by the discharge current generated by the second constant current circuit. A fourth switch circuit controlled by the fourth control signal is connected in series with a fourth series circuit, and the second capacitor is connected to the connection point. ( Motomeko 1).

  In the pulse width modulation circuit of the present invention, the differential amplifier circuit comprises a transistor circuit in which the emitters of two transistors are connected to each other, and a constant voltage source is connected between the base and emitter at the connection point. The first constant current circuit and the second constant current circuit have the same circuit configuration as the constant current circuit, and the constant voltage source is shared with the constant current circuit. (Claim 2).

  In the pulse width modulation circuit of the present invention, the first to fourth switch circuits are composed of semiconductor switching elements, and the first and second charge current generation circuits are voltage-current conversions using one transistor. It is good to be comprised with a circuit (Claim 3).

  According to this configuration, the first control circuit that controls the charging / discharging operation of the first capacitor included in the first pulse signal generation unit and the charging / discharging of the second capacitor included in the second pulse signal generation unit. A second control circuit for controlling the operation, a series circuit of a charging current generation circuit and a switch circuit for controlling the charging operation of the capacitor by the charging current generated by the charging current generation circuit by a control signal for charging; Connected in series with a series circuit of a constant current circuit that generates a constant current as a current and a switch circuit that controls the discharge operation of the capacitor by the discharge current generated by this constant current circuit using a control signal for discharge. Since the same circuit configuration in which a capacitor is connected to the point and the control circuit is connected in parallel between a pair of power supply terminals of a differential amplifier circuit in which both control circuits are shared, the first First and second charging current generation circuits included in the second control circuit, first and second switch circuits for charge control, first and second constant current circuits for discharge, and discharge control The third and fourth switch circuits can be realized by simple circuits each using a semiconductor element such as a transistor, and the specific circuit of the pulse width modulation circuit can be simplified.

  For example, the differential amplifier circuit is a circuit in which the emitters of two transistors are connected to each other, and a constant current circuit composed of a transistor circuit in which a constant voltage source is connected between the base and emitter is connected to the connection point. The fourth switch circuit is constituted by a semiconductor switch element, the first and second charging current generation circuits are constituted by a voltage-current conversion circuit using one transistor, and the first constant current circuit and the second constant current circuit The constant current circuit is configured to have the same circuit configuration as that of the constant current circuit included in the differential amplifier circuit, and the constant voltage source of the constant current circuit is shared. It can be configured with a small number of parts, and low-priced parts can be used. As a result, it is possible to simplify the specific circuit of the pulse width modulation circuit and reduce the manufacturing cost.

  Further, the drive power supply for the first and second control circuits is shared with the drive power supply for the differential amplifier circuit, and the constant voltage sources of the first constant current circuit and the second constant current circuit are used as the differential amplifier circuit. By sharing the constant voltage source of the included constant current circuit, the types of power supply voltages can be reduced, and the power supply of the pulse width modulation circuit can be simplified.

  The switching amplifier provided by the second aspect of the present invention includes a pulse width modulation circuit provided by the first aspect of the present invention, a voltage source that outputs a predetermined power supply voltage, and an output from the pulse width modulation circuit. And a switching circuit for switching a predetermined power supply voltage supplied from the voltage source based on the modulated signal.

  According to this configuration, since this switching amplifier includes the pulse width modulation circuit provided by the first aspect of the present invention, the same effect as the pulse width modulation circuit provided by the first aspect can be obtained. Play.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a block circuit diagram showing an embodiment of a pulse width modulation circuit according to the present invention. It is a detailed circuit diagram of the circuit regarding the charge / discharge operation included in the pulse width modulation circuit. It is a figure which shows the waveform of each signal of a pulse width modulation circuit when an audio signal is a no signal. It is a figure which shows the specific circuit of a pulse generation circuit and a pulse synthetic | combination circuit. It is a figure for demonstrating the pulse width modulation operation | movement in a pulse width modulation circuit. In conventional pulse width modulation circuit is a time chart showing the pulse width modulation operation when the low-level and the low level of the second control signal of the first control signal is duplicated. In the pulse width modulation circuit according to the present invention, it is a time chart showing a pulse width modulation operation when the low-level and the low level of the second control signal of the first control signal is duplicated. It is a block diagram which shows the switching amplifier with which the conventional pulse width modulation circuit is applied. It is a block block diagram which shows the conventional pulse width modulation circuit. It is a detailed circuit diagram showing a conventional pulse width modulation circuit.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

  The switching amplifier to which the pulse width modulation (PWM) circuit according to the present invention is applied is the same as the switching amplifier shown in FIG. 8 described in the background art. Therefore, the description thereof is omitted here.

  FIG. 1 is a block diagram of the pulse width modulation circuit 10. FIG. 2 is a detailed circuit diagram of a circuit related to the charge / discharge operation included in the pulse width modulation circuit 10 (see the circuit surrounded by the one-dot chain line in FIG. 1). As shown in FIG. 1, the pulse width modulation circuit 10 includes a clock generation circuit 11, a differential amplifier circuit 12, first and second charging current generation circuits 13 and 14, and first to fourth switches SW1 to SW4. And first and second capacitors C1 and C2, first and second discharge constant current circuits 15 and 16, first and second pulse generation circuits 17 and 18, and a pulse synthesis circuit 19. Yes.

  In the following description, the timing chart of FIG. 3 showing the operation of the pulse width modulation circuit 10 is referred to as needed.

  The clock generation circuit 11 generates a reference clock signal MCLK (see FIG. 3A), and generates a first control signal φ1 and a second control signal φ2 from the reference clock signal MCLK. The reference clock signal MCLK is a clock signal having a duty ratio of about 50% and serves as a reference signal for the first and second control signals φ1 and φ2. The first and second control signals φ1 and φ2 are signals for controlling on / off operations of the first and second switches SW1 and SW2 in order to cause the first and second capacitors C1 and C2 to perform a charging operation. The second control signal φ2 has an antiphase relationship with the first control signal φ1. The clock generation circuit 11 outputs the first control signal φ1 to the first switch SW1, and outputs the second control signal φ2 to the second switch SW2.

The clock generation circuit 11 generates first and second set signals set1 and set2 from the first and second control signals φ1 and φ2. The first set signal set1, as shown in FIG. 3 (d), a signal detected on Ri edge standing when inverted from the low level of the first control signal φ to the high level, the second set signal set2 is as shown in FIG. 3 (e), a signal detected on Ri edge standing when inverted from the low level of the second control signal φ to the high level. The first set signal set1 is input as a set signal to the first pulse generation circuit 17 configured by an RS latch circuit, and the second set signal set2 is a second pulse generation circuit configured by an RS latch circuit. 18 is input as a set signal.

The differential amplifier circuit 12 amplifies and outputs the amplitude of the audio signal e _S supplied from the audio signal generation source AU (see FIG. 8) to the pulse width modulation circuit 10 with reference to the ground level (0 volts). It is. In the differential amplifier circuit 12, the emitters of the two transistors are connected to each other, and the collectors of both transistors are connected to a positive power supply (power supply voltage + V) through resistors, respectively, while the emitters of both transistors are connected to a constant current circuit. This is a well-known differential amplifier circuit connected to a negative power source (power source voltage -V). In the differential amplifier circuit 12, the audio signal e _S is input to the base of one transistor, and the base of the other transistor is grounded, so that 0 volt (ground level) of the audio signal e _{S is obtained} between the collectors of both transistors. A voltage obtained by amplifying the reference difference voltage (the amplitude of the audio signal e _S ) is output. This differential voltage is output to the first and second charging current generation circuits 13 and 14.

  The first and second charging current generation circuits 13 and 14 are circuits that convert the voltage output from the differential amplifier circuit 12 into a current that changes in proportion to the change in the voltage. The first charging current generation circuit 13 and the second charging current generation circuit 14 have the same circuit configuration. The first charging current generation circuit 13 is connected to the first capacitor C1, and charges the first capacitor C1 by supplying voltage-current converted current to the first capacitor C1. Accordingly, the first charging current generation circuit 13 generates a charging current for charging the first capacitor C1. On the other hand, the second charging current generation circuit 14 is connected to the second capacitor C2, and charges the second capacitor C2 by supplying a voltage-current converted current to the second capacitor C2. Therefore, the second charging current generation circuit 14 generates a charging current for charging the second capacitor C2.

When the conversion conductance in the first and second charging current generation circuits 13 and 14 is Gm, the current Δi converted from the audio signal e _S by the first and second charging current generation circuits 13 and 14 is Δi = Gm · e. _S can be represented. If the bias current in the first and second charging current generation circuits 13 and 14 is Ic, the charging currents of the first and second capacitors C1 and C2 can be expressed as Ic + Gm · e _S = Ic + Δi.

The first switch SW1 controls whether to supply the power supply voltage + V to the first charging current generation circuit 13, that is, whether to operate the first charging current generation circuit 13 to charge the first capacitor C1. The second switch SW2 is configured to supply the power supply voltage + V to the second charging current generation circuit 14, that is, whether the second charging current generation circuit 14 is operated to charge the second capacitor C2. This is a circuit for controlling the above. The first switch SW1 and the second switch W2 have the same circuit configuration. The first and second switches SW1 and SW2 are turned on and off based on the first and second control signals φ1 and φ2 output from the clock generation circuit 11. The first switch SW1 is turned on when the first control signal φ1 is at a low level, and is turned off when the first control signal φ1 is at a high level. The second switch SW2 is turned on when the second control signal φ2 is at a low level, and is turned off when the second control signal φ2 is at a high level.

The first discharging constant current circuit 15 is a circuit for discharging the accumulated charge of the first capacitor C1 charged with the charging current (Ic + Δi), and the second discharging constant current circuit 16 is the charging current (Ic + Δi). This is a circuit for discharging the accumulated charge of the second capacitor C2 charged in step. The first discharging constant current circuit 15 is connected to the first capacitor C1, and discharges the accumulated charge of the first capacitor C1 by drawing the charge accumulated in the first capacitor C1 with a constant discharge current Id. . On the other hand, the second discharge constant current circuit 16 is connected to the second capacitor C2, and draws the charge accumulated in the second capacitor C2 by the constant discharge current Id, thereby obtaining the accumulated charge in the second capacitor C2. Discharge.

  The third switch SW3 determines whether or not to supply the power supply voltage −V to the first discharging constant current circuit 15, that is, whether or not the first discharging constant current circuit 15 is operated to discharge the first capacitor C1. The fourth switch SW4 controls whether or not to supply the power supply voltage −V to the second discharging constant current circuit 16, that is, operates the second discharging constant current circuit 16 to operate the second capacitor. This circuit controls whether or not C2 is discharged. The third switch SW3 and the fourth switch W4 have the same circuit configuration. The third and fourth switches SW3 and SW4 are turned on and off based on the third and fourth control signals φ3 and φ4 output from the first and second pulse generation circuits 17 and 18, respectively. The third switch SW3 is turned on when the third control signal φ3 is at a high level, and is turned off when the third control signal φ3 is at a low level. The fourth switch SW4 is turned on when the fourth control signal φ4 is at a high level, and is turned off when the fourth control signal φ4 is at a low level.

The first and second capacitors C1 and C2 are elements for converting the amplitude of the audio signal e _S into time. The amplitude of the audio signal e _S is the charging current that is proportional to the first and second capacitors C1, C2 to the amplitude of the audio signal e _S (Ic + .DELTA.i) at a certain time (half the time of the period T of the reference clock signal MCLK) Then, the accumulated charge is discharged with a constant discharge current Id and converted into time by generating a pulse signal having the discharge time as a pulse width.

  The first pulse generation circuit 17 uses a first pulse signal rsout1 (FIG. 3 (j)) whose pulse width is the discharge time until the voltage across the first capacitor C1 changes from the voltage level at the start of discharge to the predetermined reference level Vth. )) And a third control signal φ3 (see FIG. 3F) for controlling the on / off operation of the third switch SW3. In the present embodiment, as will be described later, the first pulse generation circuit 17 and the second pulse generation circuit 18 are configured by an R-S latch circuit using a NAND circuit, so that the reference level Vth is the threshold of the NAND circuit. Hold level.

The first pulse signal rsout1 is output to the pulse synthesis circuit 19, and the third control signal φ3 is output to the third switch SW3. The second pulse generation circuit 18 uses the second pulse signal rsout2 (FIG. 3 (k) having a pulse width as the discharge time until the voltage across the second capacitor C2 changes from the voltage level at the start of discharge to the reference level Vth. )) And a fourth control signal φ4 (see FIG. 3G) for controlling the on / off operation of the fourth switch SW4. The second pulse signal rsout2 is output to the pulse synthesis circuit 19, and the fourth control signal φ4 is output to the fourth switch SW4.

  The pulse synthesizing circuit 19 synthesizes the first and second pulse signals rsout1 and rsout2 output from the first and second pulse generating circuits 17 and 18, and outputs them as a PWM modulation signal PWMout (see FIG. 3 (l)). Circuit.

  Next, the details of the circuit related to the charge / discharge operation (refer to the circuit surrounded by the one-dot chain line in FIG. 1) will be described with reference to FIG. The circuits having the same functions as those in FIG.

The differential amplifier circuit 12 connects the emitter of the npn-type first transistor Q1 and the emitter of the npn-type second transistor Q2 to the constant current circuit through the resistors R3 and R4, respectively, and the collector of the first transistor Q1. This is a known differential amplifier circuit in which the collector of the second transistor Q2 is connected to a positive power supply (power supply voltage + V) via a resistor R1 and a resistor R2, respectively.

The audio signal e _S is input to the base of the first transistor Q1 via the coupling capacitor Ca, and the base of the second transistor Q2 is grounded (0 volt level).

  In the constant current circuit, the emitter of the npn-type third transistor Q3 is connected to a negative power supply (power supply voltage -V) via a resistor R6, and the base is connected to a positive power supply (power supply voltage + V) via a resistor R11. In addition, this is a known constant current circuit in which a Zener diode (constant voltage diode) D1 is connected between the base and the negative power supply. The collector of the third transistor Q3 is connected to the resistors R3 and R4. In this circuit, since the base voltage of the third transistor Q3 becomes the Zener voltage Vz of the Zener diode D1, the collector of the third transistor Q3 is (Vz−Vbe) / R6 (Vbe is between the base and emitter of the third transistor Q3). Constant current Id flows.

The first charging current generating circuit 13 and the second charging current generating circuit 14 are configured by a circuit in which a current limiting resistor is connected to the emitter of a pnp transistor, and the first switch SW1 and the second switch SW2 are pnp transistors. It consists of The first switch SW1 and the first charging current generation circuit 13 are connected in series, and the second switch SW2 and the second charging current generation circuit 14 are connected in series. The emitters of the first switch SW1 and the second switch SW2 are both connected to a positive power supply (power supply voltage + V), and the fourth transistor Q4 and the second charging current generating circuit 14 constituting the first charging current generating circuit 13 are connected. The collector of the fifth transistor Q5 is connected to the first capacitor C1 and the second capacitor C2 , respectively.

A fourth transistor Q4 to the base of the 5 Track transistor Q5 is connected to the collector of the first transistor Q1 of the differential amplifier circuit 12, the amplitude relative to the ground level of the audio signal e _s from the differential amplifier circuit 12 Entered. The first control signal φ1 and the second control signal φ2 are input from the clock generation circuit 11 to the bases of the first switch SW1 and the second switch SW2, respectively.

  The first discharging constant current circuit 15 and the second discharging constant current circuit 16 are composed of the same circuit as the constant current circuit in the differential amplifier circuit 12, and the third switch SW3 and the fourth switch SW4 are npn type. It is composed of transistors. The first discharging constant current circuit 15 and the third switch SW3 are connected in series, and the second discharging constant current circuit 16 and the fourth switch SW4 are connected in series. The first discharge constant current circuit 15 and the second discharge constant current circuit 16 are constant current circuits using an npn transistor, an emitter resistor, and a Zener diode, but the first and second discharge constant current circuits 15, The Zener diode that provides the base voltage of the 16 npn-type transistors shares the Zener diode D1 of the constant current circuit in the differential amplifier circuit 12.

Accordingly, the collector of the sixth transistor Q6 constituting the first discharging constant current circuit 15 is connected to the first capacitor C1, and the emitter of the sixth transistor Q6 is connected to the collector of the third switch SW3 via the resistor R9. Yes. The collector of the seventh transistor Q7 constituting the second discharging constant current circuit 16 is connected to the second capacitor C2, and the emitter of the seventh transistor Q7 is connected to the collector of the fourth switch SW4 via the resistor R10. Yes. The bases of the sixth transistor Q6 and the seventh transistor Q7 are connected to the cathode of the Zener diode D1.

  The emitters of the third switch SW3 and the fourth switch SW4 are connected to a negative power supply (power supply voltage −V), and the third control signal φ3 output from the first pulse generation circuit 17 is connected to the base of the third switch SW3. The fourth control signal φ4 output from the second pulse generation circuit 18 is input to the base of the fourth switch SW4.

In the circuit of FIG. 2, when the first control signal φ1 becomes low level, the first switch SW1 is turned on, the positive power supply (+ V) is connected to the first charging current generation circuit 13, and the first charging current generation circuit The fourth transistor Q4 in 13 operates. Since the differential voltage of the audio signal e _S with respect to the ground level, that is, the amplitude value of the audio signal e _S is input from the differential amplifier circuit 12 to the base of the fourth transistor Q4, the audio signal is input to the collector of the fourth transistor Q4. A charging current (Ic + Δi) proportional to the amplitude value of e flows, and the first capacitor C1 is charged by this charging current (Ic + Δi) during the low level period of the first control signal φ1 (FIG. 3B, (h) (Refer to the waveform of T1, T3 period).

Similarly, when the second control signal φ2 becomes low level, the second switch SW2 is turned on, the positive power source (+ V) is connected to the second charging current generation circuit 14, and the second charging current generation circuit 14 The fifth transistor Q5 operates. Since the differential voltage of the audio signal e _S with respect to the ground level is also input from the differential amplifier circuit 12 to the base of the fifth transistor Q 5 , the charging current proportional to the amplitude value of the audio signal e is applied to the collector of the fifth transistor Q 5. (Ic + Δi) flows, and the second capacitor C2 is charged by this charging current (Ic + Δi) during the low level period of the second control signal φ2 (see waveforms in the periods T2 and T4 in FIGS. 3C and 3I). ).

  Further, when the third control signal φ3 becomes high level, the third switch SW3 is turned on, a negative power source (−V) is connected to the first discharging constant current circuit 15, and the first discharging constant current circuit 15 is turned on. An inner sixth transistor Q6 performs an operation of drawing a constant current Id. As a result, the electric charge accumulated in the first capacitor C1 is discharged with the constant current Id (see waveforms in the periods T2 and T4 in FIGS. 3 (f) and 3 (h)).

  Similarly, when the fourth control signal φ4 becomes high level, the fourth switch SW4 is turned on, a negative power source (−V) is connected to the second discharge constant current circuit 16, and the second discharge constant current circuit The seventh transistor Q7 in 16 performs an operation of drawing a constant current Id. As a result, the charge accumulated in the second capacitor C2 is discharged with the constant current Id (see waveforms in the periods T1 and T3 in FIGS. 3G and 3I).

  As shown in FIG. 4, the first pulse generation circuit 17 is configured by a well-known RS latch circuit using two NAND circuits. The input terminal of the second NAND circuit N2 of the first pulse generation circuit 17 is an input terminal for an S (set) signal, and the input terminal of the first NAND circuit N1 is an input terminal for an R (reset) signal. The output terminal of the first NAND circuit N1 is an output terminal for the / Q signal, and the output terminal of the second NAND circuit N2 is an output terminal for the Q signal.

  The voltage across the first capacitor C1 is input as the first reset signal res1 to the input terminal of the first NAND circuit N1 of the first pulse generation circuit 17, and the output from the clock generation circuit 11 is input to the input terminal of the second NAND circuit N2. The first set signal set1 is input. The pulse signal output from the output terminal of the first NAND circuit N1 is input to the pulse synthesis circuit 19 as the first pulse signal rsout1 for generating the PWM modulation signal PWMout, and is output from the output terminal of the second NAND circuit N2. The pulse signal is input to the base of the third switch SW3 as the third control signal φ3.

In the RS latch circuit shown in FIG. 4, the logic of (Q, / Q) = (high, low) is obtained when (S, R) = (high, low), and (S, R) = (low, high). Thus, the logic of (Q, / Q) = (low, high) is obtained. FIG. 3 (d), the as shown in (h), the first set of signals falling on wants timing first control signal φ1 is set1 goes momentarily to the low level, the voltage across the first capacitor C1 (first reset Since the signal res1) is at the high level, the first pulse signal rsout1 is at the low level, and the third control signal φ3 is at the high level (see FIGS. 3F and 3J). When the third control signal φ3 is at a high level, the first capacitor C1 starts to be discharged. However, the first pulse signal rsout1 is maintained while the voltage across the first capacitor C1 is higher than the threshold level Vth of the first NAND circuit N1. Is held at the low level and reaches the threshold level Vth, the first set signal set1 goes to the high level and the first reset signal res1 goes to the low level, so at this timing, the first pulse signal rsout1 goes to the high level. Thus, the third control signal φ3 becomes a low level (see FIGS. 3F and 3J).

Similarly to the first pulse generation circuit 17, the second pulse generation circuit 18 is configured by a well-known RS latch circuit using two NAND circuits. As shown in FIG. 4, the voltage across the second capacitor C2 is input as the second reset signal res2 to the input terminal of the third NAND circuit N3 of the second pulse generation circuit 18, and the clock is input to the input terminal of the fourth NAND circuit N4. The second set signal set2 output from the generation circuit 11 is input. The pulse signal output from the output terminal of the third NAND circuit N3 is input to the pulse synthesis circuit 19 as the second pulse signal rsout2 for generating the PWM modulation signal PWMout, and is output from the output terminal of the fourth NAND circuit N4. pulse signal is input to the base of the fourth switch SW 4 as a fourth control signal .phi.4.

FIG. 3 (e), the as shown in (i), the second control signal φ2 is the second set signal at a falling on wants timing set2 goes momentarily to the low level, the voltage across the second capacitor C2 (second reset Since the signal res 2 ) is at a high level, the second pulse signal rsout2 is at a low level, and the fourth control signal φ4 is at a high level (see FIGS. 3G and 3K). When the fourth control signal φ4 becomes high level, discharging of the second capacitor C2 is started. However, as long as the voltage across the second capacitor C2 is higher than the threshold level Vth of the third NAND circuit N3, the second pulse signal rsout2 Is held at the low level and reaches the threshold level Vth, the second set signal set2 goes to the high level and the second reset signal res2 goes to the low level, so the second pulse signal rsout2 goes to the high level at that timing. Thus, the fourth control signal φ4 becomes low level (see FIGS. 3G and 3K).

  As shown in FIG. 4, the pulse synthesizing circuit 19 includes a fifth NAND circuit N5. The first pulse signal rsout1 output from the first pulse generating circuit 17 and the second pulse output from the second pulse generating circuit 18 are included. A pulse width modulation signal PWMout is generated by calculating a negative logical product with the pulse signal rsout2 (see FIG. 3L).

  Next, the pulse width modulation operation in the pulse width modulation circuit 10 will be briefly described with reference to FIG. Since the same pulse width modulation operation is performed by the first capacitor C1 and the second capacitor C2, the pulse width modulation operation in the first capacitor C1 will be described here.

When the first control signal φ1 becomes low level, the first switch SW1 is turned on, and the first charging current generation circuit 13 performs the operation of generating the charging current (Ic + Δi). Since the third control signal φ3 is at the low level during the period in which the first control signal φ1 is at the low level, the third switch SW3 is in the OFF state (see FIGS. 3B and 3F), and the first discharge signal The constant current circuit 15 is not operating. Therefore, only the charging current (Ic + Δi) generated by the first charging current generation circuit 13 flows into the first capacitor C1, and the first capacitor C1 is charged thereby. This charging operation is performed during a period in which the first control signal φ1 is at a low level (period T1 in FIG. 5).

The voltage across the first capacitor C1 during the period T1 (the voltage at the point A in FIG. 2) rises from the reference level Vth with a slope proportional to the magnitude of the charging current (Ic + G · e _S ). The charging current (Ic + G · e _S ) depends on the positive and negative directions and the amplitude of the audio signal e _S. The larger the amplitude | e _S | at e _S > 0, the higher the charging voltage at the end of the period T1. Thus, the larger the amplitude | e _S | at e _S <0, the lower the charging voltage at the end of the period T1. In FIG. 5, the period T1 is the audio signal e very short relative to the amplitude variation of _S, substantially linear charging voltage of the first capacitor C1 as the amplitude variation of the period an audio signal in T1 e _S is almost no constant Is rising.

The voltage waveform S0 in FIG. 5 shows a waveform when e _S = 0 (when the audio signal e _S is no signal), the voltage waveform S1 shows a waveform when e _S > 0, and the voltage waveform S2 is , E _S <0.

When the capacitance of the first capacitor C1 is “C” and the charging voltage of the first capacitor C1 at the end of the period T1 is “Vj”, in the charging operation of the first capacitor C1 in the period T1, (Ic + G · e _S ) The relationship of × T1 = C × (Vj−Vth) is established. From this relational expression, Vj = G · e _S × T1 / C + Ic × T1 / C + Vth. Therefore, when A = G × T1 / C and B = Ic × T1 / C + Vth are arranged, Vj = A × e _S + B Become. According to FIG. 5, since Vj = V0 at e _S = 0, B = V0, so that the charging voltage Vj of the first capacitor C1 is expressed as Vj = A × e _S + V0. That is, the charging voltage Vj of the first capacitor C1 is the amplitude of e _S> 0 In the audio signal e _S around the V0 | increases in proportion to, e _S <0 the amplitude of the audio signal e _S | | e _S e Decreases in proportion to _S |.

When the first control signal φ1 becomes high level and the third control signal φ3 becomes high level, the first switch SW1 is turned off and the third switch SW3 is turned on at the same time, and the first charging current generation circuit 13 stops operating. Then, the first discharging constant current circuit 15 performs the operation of drawing the constant current Id. Accordingly, the electric charge accumulated in the first capacitor C1 is drawn into the first discharging constant current circuit 15 by the constant current Id, and thereby the electric charge accumulated in the first capacitor C1 is discharged. This discharge operation is performed until the voltage of the first capacitor C1 drops to the reference level Vth.

When the voltage of the first capacitor C1 drops to the reference level Vth, the third control signal φ3 is inverted to the low level and the third switch SW3 is turned off, so that the first discharge constant current circuit 15 is pulled in by the constant current Id. Operation stops. That is, during the period from when the voltage of the first capacitor C1 drops to the reference level Vth until the first control signal φ1 goes to the low level next, neither charging current nor discharging current flows through the first capacitor C1. . Accordingly, the voltage of the first capacitor C1 is held at the reference level Vth until the first control signal φ1 becomes low level (see times t1k, t0k, and t2k in FIG. 5).

Assuming that the charging voltage of the first capacitor C1 is “Vj” and the discharging time is “Th”, the relationship of Id × Th = C × (Vj−Vth) is established, so Th = C × Vj / id−Vth / Id. Thus, the discharge time Th is proportional to the charging voltage Vj. That is, the higher the charging voltage Vj, the longer the discharge time Th. In FIG. 5, time t1 indicates the discharge time when the audio signal e _S > 0, time t0 indicates the discharge time when the audio signal e _S = 0, and time t2 indicates the audio signal e _S <0. The discharge time at this time is shown, and the relationship is t2 <t0 <t1.

The height of the charging voltage Vj, the amplitude of the audio signal e _S | proportional to, the discharge time Th the amplitude of the audio signal e _S | | e _S will be proportional to | e _S. That is, the discharge time Th of the first capacitor C1 indicates a time modulated by the amplitude | e _S | of the audio signal e _S. The above-described pulse width modulation operation is the same for the second capacitor C2.

In the pulse width modulation circuit 10 according to the present embodiment, as shown in FIG. 3, a pulse obtained by performing pulse width modulation of the audio signal e _S by the second capacitor C2 in the high level period of the period T of the reference clock signal MCLK is generated. In the subsequent low level period, the first capacitor C1 generates a pulse obtained by pulse-width modulating the audio signal e _S , so that both pulses are synthesized by the pulse synthesizing circuit 19 so that the pulse width modulation having the period T of the reference clock signal MCLK is performed. The signal PWMout is generated.

Next, the operation of the pulse width modulation circuit 10 will be described with reference to the timing chart shown in FIG. FIG. 3 shows a case where the audio signal e _S is no signal (Gm · e _S = 0). In FIG. 3, the first period T1, the second period T2, the third period T3, and the fourth period with respect to the high level and low level periods for two cycles from the period when the reference clock signal MCLK first becomes the high level, respectively. Let's say T4.

In the first period T1, since the first control signal φ1 from the clock generation circuit 11 is at a low level (the second control signal φ2 is at a high level) (see FIG. 3B), the first switch SW1 is in an on state ( The second switch SW2 is turned off), and the first charging current generation circuit 13 is connected to the first capacitor C1. Accordingly, in the first period T1, the charging current (Ic + Δi) flows from the first charging current generation circuit 13 to the first capacitor C1, thereby charging the first capacitor C1 (see FIG. 3 (h)). This charging operation is performed until the first period T1 ends.

When the first period T1 ends and the first control signal φ1 is inverted from the low level to the high level, the first switch SW1 is turned off. The OFF state of the first switch SW1 continues during the second period T2. The clock generation circuit 11 detects the Ri when reversing the above standing of the first control signal .phi.1, instant the first pulse generation circuit 17 to output a first set signal set1 is changed to a low level (FIG. 3 (d ) See first low level change).

  In the first pulse generation circuit 17, when the first set signal set1 (low level) is input at the start of the second period T2, the output of the second NAND circuit N2 is inverted from the low level to the high level (FIG. 3 (f )reference). Since the output of the second NAND circuit N2 is input to the third switch SW3 as the third control signal φ3, the third switch SW3 is turned on, and the first discharging constant current circuit 15 is connected to the first capacitor C1, As a result, the first capacitor C1 is discharged with the constant current Id (see FIG. 3 (h)).

  Further, in the first pulse generation circuit 17, when the first set signal set1 (low level) is input at the start of the second period T2, the output of the first NAND circuit N1 is inverted from the high level to the low level (FIG. 3). (See (j)). The output of the first NAND circuit N1 is input to the pulse synthesis circuit 19 as the first pulse signal rsout1.

  When the low level output of the first NAND circuit N1 is input to the pulse synthesizing circuit 19, the second pulse signal rsout2 input from the second pulse generating circuit 18 to the fifth NAND circuit N5 of the pulse synthesizing circuit 19 is high level. The synthesis circuit 19 outputs a pulse (high level pulse) obtained by inverting the level of the first pulse signal rsout1 (see the second pulse in FIG. 3L).

In the second period T2, since the first capacitor C1 is discharged with the constant current Id, the voltage across the first capacitor C1 decreases. In the first pulse generation circuit 17, the voltage across the first capacitor C1 is input to the first NAND circuit N1, but when the voltage across the first capacitor C1 drops to the reference level Vth, the voltage at that time is the low level first. The reset signal res1 is input to the first pulse generation circuit 17. When the first reset signal res1 is input to the first pulse generation circuit 17, the first pulse signal rsout1 is inverted from the low level to the high level (see FIG. 3 (j)).

On the other hand, in the second period T2, since the second control signal φ2 from the clock generation circuit 11 is at a low level (the first control signal φ1 is at a high level) (see FIG. 3C), the second switch SW2 is turned on. The state (the first switch SW1 is turned off) is entered, and the second charging current generation circuit 14 is connected to the second capacitor C2. Therefore, in the second period T2, the charging current (Ic + Δi) flows from the second charging current generation circuit 14 to the second capacitor C2, thereby charging the second capacitor C2 (see FIG. 3 (i)). This charging operation is performed until the second period T2 ends.

When the second period T2 ends and the second control signal φ2 is inverted from the low level to the high level, the second switch SW2 is turned off. The OFF state of the second switch SW2 continues during the third period T3. The clock generation circuit 11, the Ri when reversing upper stand of the second control signal φ2 is detected, instantaneously the second pulse generating circuit 18 outputs the second set signal set2 which changes to the low level (FIG. 3 (e )reference).

  In the second pulse generation circuit 18, when the second set signal set2 (low level) is input at the start of the third period T3, the output of the fourth NAND circuit N4 is inverted from the low level to the high level (FIG. 3 (g )reference). Since the output of the fourth NAND circuit N4 is input to the fourth switch SW4 as the fourth control signal φ4, the fourth switch SW4 is turned on, and the second discharge constant current circuit 16 is connected to the second capacitor C2. As a result, the second capacitor C2 is discharged with the constant current Id (see FIG. 3 (i)).

  In the second pulse generation circuit 18, when the second set signal set2 (low level) is input at the start of the third period T3, the output of the third NAND circuit N3 is inverted from the high level to the low level (FIG. 3). (See (k)). The output of the third NAND circuit N3 is input to the pulse synthesis circuit 19 as the second pulse signal rsout2.

  When the low level output of the third NAND circuit N3 is inputted to the pulse synthesis circuit 19, the first pulse signal rsout1 inputted from the first pulse generation circuit 17 to the fifth NAND circuit N5 of the pulse synthesis circuit 19 is high level, so that the pulse The synthesizer 19 outputs a pulse (high level pulse) obtained by inverting the level of the second pulse signal rsout2 (see the third pulse in FIG. 3 (l)).

  Thereafter, after the third period, operations similar to those in the first period T1 and the second period T2 are repeated. Accordingly, the pulse synthesizing circuit 19 alternately outputs pulses obtained by inverting the levels of the first pulse signal rsout1 and the second pulse signal rout2 every half cycle of the reference clock signal MCLK.

  As described above, in the pulse width modulation circuit 10, as shown in FIG. 1, the circuit that controls the charging operation of the first capacitor C1 and the circuit that controls the charging operation of the second capacitor C2 have the same circuit configuration (switch circuit). And a circuit for controlling the discharging operation of the first capacitor C1 and a circuit for controlling the discharging operation of the second capacitor C2 (switch circuit and constant current circuit for discharging). As shown in FIG. 2, the first switch SW1 and the second switch SW2 that control the charging operation can be realized by the same transistor, and the third switch SW3 that controls the discharging operation, as shown in FIG. The fourth switch SW4 can be realized by the same transistor.

  Further, the first charging current generation circuit 13 and the second charging current generation circuit 14 share a differential amplifier circuit 12, and a voltage-current conversion circuit having the same circuit configuration using a transistor is connected to the differential amplifier circuit 12. This can be realized. Furthermore, the first discharging constant current circuit 15 and the second discharging constant current circuit 16 can be realized by a constant current circuit having the same circuit configuration using a transistor and a Zener diode.

  In addition, since this constant current circuit can have the same circuit configuration as the constant current circuit in the differential amplifier circuit 12, the Zener diode D1 in the differential amplifier circuit 12 is connected to the first constant current circuit 15 for discharge and the first current circuit. The zener diode of the two-discharge constant current circuit 16 can be shared. Furthermore, since the drive power source of the pulse width modulation circuit 10 may be two types, a positive power source (+ V) and a negative power source (−V), the power source circuit can be simplified.

  Therefore, the pulse width modulation circuit 10 can be realized with a small number of parts, and the circuit can be simplified and downsized. Further, since the pulse width modulation circuit 10 can be realized using a low-cost semiconductor element such as a transistor or a Zener diode, the manufacturing cost can be reduced.

  Further, in the conventional pulse width modulation circuit 1, as shown in FIG. 9, the switch is controlled by the first control signal φ1 in the first switch section 102a and the second control signal φ2 in the second switch section 102b. Since the switches to be connected are connected in series between the first capacitor C1 and the second capacitor C2, when both switches are simultaneously turned on, the voltage-current conversion circuit 101 includes the first capacitor C1 and the second capacitor. C2 is connected in parallel, and there arises a problem that the charging operation of the first capacitor C1 and the second charging operation are not properly performed.

In particular, in the specific circuit shown in FIG. 10, the four switches in the first switch unit 102a and the second switch unit 102b are configured by analog switch ICs having bidirectional characteristics, so that the first control signal φ1 rises. without the dead time between the upper Ri timing and timing Ri falling of the second control signal .phi.2, first in the analog switch controlled by the first control signal φ1 in the first switch unit 102a second switch 102b 2 There is a possibility that the analog switches controlled by the control signal φ2 may be turned on at the same time. When such a state occurs, an abnormal PWM modulation signal PWMout is output from the pulse width modulation circuit 1. , the pulse width modulation circuit 10 according to the present embodiment, no such inconvenience arise that. Hereinafter, this effect will be described.

6, in the conventional pulse width modulation circuit 1 is a time chart showing the pulse width modulation operation when the low-level and the low level of the second control signal φ2 of the first control signal φ1 is duplicated.

  The waveforms of “φ1” and “φ2” in FIG. 6 are the waveforms of the first control signal φ1 and the second control signal φ2 input to the first switch unit 102a and the second switch unit 102b in FIG. The waveforms of “C1” and “C2” are voltage waveforms input to the first pulse generation circuit 104 and the second pulse generation circuit 105 in FIG. 9, and are “rsout1”, “rsout2”, and “PWMout”. The waveforms are voltage waveforms output from the first pulse generation circuit 104, the second pulse generation circuit 105, and the pulse synthesis circuit 106 in FIG.

As shown in the figure, the second control signal φ2 is set to the timing Ri falling of the second control signal φ2 is advanced by a minute time td for standing on Ri timing of the first control signal .phi.1, standing on Ri minute time from the timing td just before the period the first control signal φ1 second control signal φ2 of the first control signal φ1 becomes both the low level (FIG. 6 (a), (b) see) .

In the first period T1, a period of from I under stood first control signal φ1 is low until just before the second control signal φ1 is Ru under standing to a low level, a voltage - current conversion circuit 101, only the first capacitor C1 Are connected, and the first capacitor C1 is charged by the charging current (Ic + Δi) from the voltage-current conversion circuit 101, so that the voltage across the first capacitor C1 rises almost linearly. However, the second control signal φ2 is the Ru under stood low level, the second capacitor C2 is connected in parallel with the first capacitor C1, so that the voltage across the first capacitor C1 is to sharply discontinuously.

When the charging voltage of the first capacitor C1 in the falling Ri timing of the second control signal φ2 is "Vj", in at that time accumulated charge of the second capacitor C2 is zero, because the voltage across is "Vth", the When the second capacitor C2 is connected in parallel to the one capacitor C1, the combined capacitance is doubled, so that the voltage across the first capacitor C1 and the second capacitor C2 is (Vj + Vth) / 2. As shown in FIG. 6, when the difference voltage between the charging voltage Vj of the first capacitor C1 and the reference level Vth of the first capacitor C1 is “Cv”, (Vj + Vth) / 2 = Vth + Cv / 2 from Vj = Vth + Cv. That is, in the falling Ri timing of the second control signal .phi.2, the voltage across the first capacitor C1 is rapidly decreased by half the difference voltage Cv of the second capacitor C2 from the charging voltage Vj, the voltage across the second capacitor C2 Increases rapidly from the reference level Vth by ½ of the difference voltage Cv from the first capacitor C1 (see FIGS. 6C and 6D).

Then, in the standing upper Ri timing of the first control signal .phi.1, voltage - current conversion circuit 101 and the state in which the first capacitor C1 and the second capacitor C2 are connected in parallel becomes a connection state of only the second capacitor C2, The second capacitor C2 is charged from the voltage (Vth + Cv / 2). On the other hand, the first capacitor C1, the third control signal φ3 above Ri timing standing of the first control signal φ1 becomes high level, since the discharging constant current circuit 103 is connected, is discharged from the voltage (Vth + Cv / 2) Will be.

As a result, when the first capacitor C1 is discharged from the charging voltage (Vth + Cv) in the normal state, the first capacitor C1 is discharged from the charging voltage (Vth + Cv / 2) to the reference level Vth. It becomes shorter than the time (see FIGS. 6C and 6E). On the other hand, the second capacitor C 2 is at the normal time where charge from the reference level Vth is performed, since it is charged by 1/2 of the period T of the reference clock signal MCLK from the voltage (Vth + Cv / 2), the charge voltage It becomes higher than the normal charging voltage. Therefore, in the discharging period of the charging period, the discharging time is longer than the discharging time in the normal state (see FIGS. 6D and 6F). As a result, a significant imbalance occurs between the pulse width modulated using the first capacitor C1 and the pulse width modulated using the second capacitor C2, and as shown in FIG. 6 (g), the PWM modulation signal PWMout The waveform becomes an abnormal waveform.

In the conventional pulse width modulation circuit 1, a dead time generation circuit is always provided after the clock generation circuit 100 shown in FIG. 9 in order to eliminate the above inconvenience, and the first control signal φ1 is changed from the low level to the high level. Standing on wants some second control signal φ2 is delayed by a predetermined time is necessary to provide a dead time so want under falls from the high level to the low level from the timing.

  On the other hand, in the pulse width modulation circuit 10 according to the present embodiment, as shown in FIG. 2, the first charging current generation circuit 13 is interposed between the first switch SW1 and the first capacitor C1, and the second switch Since the second charging current generation circuit 14 is interposed between the SW2 and the second capacitor C2, even if the first switch SW1 and the second switch SW2 are turned on at the same time, as in the conventional pulse width modulation circuit 1 In addition, the first capacitor C1 and the second capacitor C2 are not connected in parallel to the same charging current generation circuit.

  That is, in the pulse width modulation circuit 10 according to the present embodiment, the first capacitor C1 is connected to the first charging current generation circuit 13 when the first switch SW1 is turned on regardless of the on / off operation of the second switch SW2. The second capacitor C2 is connected and charged by the charging current from the first charging current generation circuit 13, and the second capacitor C2 performs the second charging when the second switch SW2 is turned on regardless of the on / off operation of the first switch SW1. It is connected to the current generation circuit 14 and is charged by the charging current from the second charging current generation circuit 14.

FIG. 7 is a time chart showing a pulse width modulation operation when the low level of the first control signal φ1 and the low level of the second control signal φ2 overlap in the pulse width modulation circuit 10 according to the present embodiment.

  The waveforms of the first control signal φ1 and the second control signal φ2 in FIG. 7 are the same as the waveforms of the first control signal φ1 and the second control signal φ2 in FIG.

In the first period T1, a period of from I under stood first control signal φ1 is low until just before the second control signal φ1 is Ru under standing to a low level, the first charging current generation circuit 13 to the first capacitor C1 Are connected, and the first capacitor C1 is charged by the charging current (Ic + Δi) output from the first charging current generation circuit 13, so that the voltage across the first capacitor C1 rises substantially linearly. Also, I under stood second control signal φ2 is at a low level, since the first capacitor C1 is not that the second capacitor C2 are connected in parallel, the voltage across the first capacitor C1 is the first control signal standing on rising timing of .phi.1, Nachi Suwa will rise until the end of the first period T1.

  Therefore, in the second period T2, the first discharging constant current circuit 15 is connected to the first capacitor C1, and the first capacitor C1 is discharged by the constant current Id output from the first discharging constant current circuit 15. The

On the other hand, the second capacitor C2, the second control signal φ2 just before the end of the first period T1 is a period from the timing Ru under stood low until the next falling on Ri timing, the second charging current generation circuit 14 is connected Since charging is performed by the charging current (Ic + Δi) output from the second charging current generation circuit 14, the voltage across the second capacitor C2 also rises almost linearly. Furthermore, since during that period the first control signal φ1 not falling Rukoto to the low level, the voltage across the second capacitor C2 rises to the timing wants the trailing second control signal .phi.2, its voltage It is held until the end of the second period T2. The second discharging constant current circuit 16 is connected to the second capacitor C2 just before the start of the third period T3, and the second capacitor C2 is discharged by the constant current Id output from the second discharging constant current circuit 16. Is done.

  As described above, since the charging / discharging operation of the first capacitor C1 and the charging / discharging operation of the second capacitor C2 are independent from each other, there is no imbalance between the charging operation and the discharging operation of both the capacitors C1 and C2. Instead, as shown in FIGS. 7E to 7G, the waveform of the PWM modulation signal PWMout is a normal waveform.

  Therefore, in the pulse width modulation circuit 10 according to the present embodiment, it is not necessary to provide a dead time generation circuit as in the conventional pulse width modulation circuit 1, and accordingly, the circuit is simplified, the circuit space is reduced, and the components Cost can be reduced.

  Of course, the scope of the present invention is not limited to the above-described embodiment, and the circuit configuration shown in the above embodiment is an example, and various circuits can be applied as long as they have equivalent functions. Can do. For example, in the above-described embodiment, the first and second capacitors C1 and C2 are once charged in the positive direction and then discharged in the negative direction. Instead, the first and second capacitors C1 and C2 are replaced. May be once charged in the minus direction and then discharged in the plus direction to generate the pulse width modulation signal PWMout.

  The first to fourth switches SW1 to SW4 are not limited to bipolar transistors, and other types of semiconductor switching elements such as FETs can be used.

  Further, a comparison circuit made of, for example, an operational amplifier may be provided between the first capacitor C1 and the first pulse generation circuit 17, or between the second capacitor C2 and the second pulse generation circuit 18. By this comparison circuit, it is possible to accurately detect that the voltage at one end of the first capacitor C1 reaches the reference voltage.

DESCRIPTION OF SYMBOLS 1,10 Pulse width modulation circuit 2 Switching circuit 3 Low pass filter circuit 4 1st power supply 5 2nd power supply 11 Clock generation circuit 12 Differential amplifier circuit 13 1st charging current generation circuit 14 2nd charging current generation circuit 15 For 1st discharge Constant current circuit 16 Second discharge constant current circuit 17 First pulse generation circuit 18 Second pulse generation circuit 19 Pulse synthesis circuit AU Audio generation source C1 First capacitor C2 Second capacitor e _S Audio signal SW1 First switch SW2 Second Switch SW3 Third switch SW4 Fourth switch T1 First period T2 Second period T3 Third period T4 Third period φ1 First control signal φ2 Second control signal φ3 Third control signal φ4 Fourth control signal

Claims (4)

Generating a second control signal. Used to perform a first control signal. Used to perform one level charging operation in the period of reference clock, the charging operation to the other level period of the reference clock A charge control signal generator;
Said first control signal by a period of the other levels following a period of one level the charging operation is performed, the third control signal order to execute the discharging operation of the charging operation by accumulated charge and the the second control signal by the period of the charging operation while levels following the period of the other level is performed to generate a fourth control signal in order to execute the discharging operation of the charging operation by accumulated charge A discharge control signal generator;
A charging operation for charging the first capacitor with a charging current generated based on the level of the input signal in accordance with the first control signal, and an accumulated charge in the first capacitor in accordance with the third control signal the running and discharge operations for discharging at a constant discharge current, the discharge the operation each time running first capacitor discharge time the pulse width to change from the level at the start of discharging to the reference level A first pulse signal generator for generating a first pulse signal,
A charging operation for charging the second capacitor with the charging current according to the second control signal, and a discharging operation for discharging the accumulated charge of the second capacitor with the discharge current according to the fourth control signal. run the door, generates the second pulse signal the second capacitor each time running the discharge operation is the pulse width discharge time from the level at the start of the discharge until the changes to the reference level A second pulse signal generator that
The first pulse signal generated by the first pulse signal generation unit and the second pulse signal generated by the second pulse signal generation unit are synthesized, and the pulse width of each pulse is equal to the input signal. A pulse signal synthesizer that outputs a pulse width modulation signal that changes according to the level;
A pulse width modulation circuit comprising:
The first pulse signal generation unit includes:
A differential amplifier for amplifying the voltage of the input signal;
A first control circuit that is connected between a pair of power supply terminals of the differential amplifier circuit and controls a charge / discharge operation of the first capacitor;
A first pulse signal generation circuit that generates the first pulse signal based on a voltage across the first capacitor;
The first control circuit generates a current corresponding to a voltage output from the differential amplifier circuit as the charging current, and a charge generated by the first charging current generation circuit. A first series circuit with a first switch circuit that controls the charging operation of the first capacitor by a current using the first control signal, and a first constant current circuit that generates a constant current as the discharge current And a second series circuit connected in series with the second switch circuit for controlling the discharge operation of the first capacitor by the discharge current generated by the first constant current circuit by the third control signal. And a circuit in which the first capacitor is connected to the connection point.
The second pulse signal generator is
Sharing the differential amplifier circuit with the first pulse signal generator;
A second control circuit that is connected between a pair of power supply terminals of the differential amplifier circuit and controls a charge / discharge operation of the second capacitor;
A second pulse signal generation circuit that generates the second pulse signal based on a voltage across the second capacitor,
The second control circuit includes a second charging current generation circuit that generates a current corresponding to a voltage output from the differential amplifier circuit as the charging current, and a charge generated by the second charging current generation circuit. A third series circuit with a third switch circuit for controlling the charging operation of the second capacitor by the current by the second control signal, and a second constant current circuit for generating a constant current as the discharge current And a fourth series circuit with a fourth switch circuit for controlling the discharge operation of the second capacitor by the discharge current generated by the second constant current circuit by the fourth control signal. The pulse width modulation circuit is constituted by a circuit in which the second capacitor is connected to the connection point. The differential amplifier circuit includes a circuit in which emitters of two transistors are connected to each other, and a constant current circuit including a transistor circuit in which a constant voltage source is connected between a base and an emitter is connected to the connection point.
The first constant current circuit and the second constant current circuit have the same circuit configuration as the constant current circuit, and share the constant voltage source with the constant current circuit.
The pulse width modulation circuit according to claim 1, wherein: The first to fourth switch circuits are composed of semiconductor switching elements,
The first and second charging current generation circuits are configured by a voltage-current conversion circuit using one transistor,
The pulse width modulation circuit according to claim 2, wherein: A pulse width modulation circuit according to claim 1;
A voltage source that outputs a predetermined power supply voltage;
A switching circuit for switching a predetermined power supply voltage supplied from the voltage source based on a pulse width modulation signal output from the pulse width modulation circuit;
A switching amplifier characterized by comprising:

Images