JP2012217118A - Pulse-width modulation circuit and switching amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the response of a pulse-width modulation signal when an amplitude of an audio signal becomes excessive at a negative side.SOLUTION: A pulse-width modulation circuit 10 comprises: a clock generation circuit 11; a differential amplifier circuit 12; a first charge-current generation circuit 13; a second charge-current generation circuit 14; switches SW1 to SW4; capacitors C1 and C2; a first discharge constant-current circuit 15; a second discharge constant-current circuit 16; a first pulse generation circuit 17; a second pulse generation circuit 18; a pulse synthesis circuit 19; and a charge start voltage maintaining circuit 20. The charge start voltage maintaining circuit 20 prevents that charge start voltages of the capacitors C1 and C2 are lower than a voltage Va by supplying a power supply voltage to the capacitors C1 and C2 when the voltages of the capacitors C1 and C2 are almost lower than the voltage Va due to discharge operation by a constant current Id.

Description

  The present invention relates to a pulse width modulation circuit and a switching amplifier.

  There has been proposed a pulse width modulation circuit that converts an audio signal into a pulse width modulation signal whose duty ratio changes according to its amplitude. FIG. 14 is a circuit diagram showing a pulse width modulation circuit, and FIGS. 15 and 16 are timing charts showing voltage waveforms of signals of the pulse width modulation circuit.

  The pulse width modulation circuit 51 includes a reference clock generation circuit 54, a dead time generation circuit 55, a falling edge detection circuit 56, a charging current generation circuit 57, a constant current source 58 for discharge, a current bypass circuit 59, , Switches SW11 to SW14, capacitors C11 and C12, first and second RS flip-flop circuits 60 and 61, and a signal output circuit 62 including a NAND circuit.

  In the pulse width modulation circuit 51, a current signal Ij (hereinafter referred to as “charging current Ij”) for charging the capacitors C 11 and C 12 is generated from the audio signal eS by the charging current generation circuit 57. A reference clock MCLK is generated.

  The charging current Ij is expressed by Ij = Ic ± Δi. The bias voltage of the output terminal of the operational amplifier 63 is determined by −Vcc and the resistors R11 and R12, and Ic (> 0) is determined by the bias voltage, the resistor R14, the transistor Q11, and the voltage 64. Further, ± Δi is a current component obtained by voltage-current conversion of the audio signal eS (AC voltage signal).

  Based on the reference clock MCLK, the dead time generation circuit 55 generates a first switching signal φ1 for controlling the charging operation of the capacitor C11 and a second switching signal φ2 for controlling the charging operation of the second capacitor C12 (FIG. 15 ( b) and (c)). The first RS flip-flop circuit 60 generates a third switching signal φ3 that controls the discharging operation of the capacitor C11 (see FIG. 15F), and the second RS flip-flop circuit 61 controls the discharging operation of the second capacitor C12. A four-switch signal φ4 is generated.

  The capacitor C11 is charged by supplying the charging current Ij (= Ic ± Δi) from the charging current generating circuit 57 only during the ON period (high level period) of the first switching signal φ1 by the switch SW11. Due to this charging, the capacitor C11 rises from the voltage Va to a voltage Vc corresponding to the amplitude E of the audio signal eS (hereinafter referred to as “charging end voltage Vc”) during the ON period of the first switching signal φ1 (FIG. 15B). ), (E)). In FIG. 15E, the charging end voltage Vc is Vm in the voltage waveform L1, and the charging end voltage Vc is Vcc in the voltage waveforms L2 and L3.

  In the off period (low level period) of the first switching signal φ1, the first set signal set1 (falling to the low level for a moment) is detected when the falling edge detection circuit 56 detects the falling (low level inversion) of the first switching signal φ1. Signal) is input to the set terminal of the first RS flip-flop circuit 60, the third switching signal φ3 output from one output terminal of the first RS flip-flop circuit 60 is inverted to a high level, and a constant current is supplied by the switch SW13. A constant current Id (hereinafter referred to as “discharge current Id”) from the source 58 is supplied to the capacitor C11, thereby starting the discharge of the capacitor C11 (FIGS. 15D, 15E, 15F). reference).

  When the voltage of the capacitor C11 drops from the charging end voltage Vc to a predetermined threshold voltage Vth (threshold voltage that divides the high level and the low level in the first RS flip-flop circuit 60) after the discharge starts, the voltage becomes the first reset signal res1. The 1RS flip-flop circuit 60 is input, the third switching signal φ3 is inverted to the low level, and the constant current source 58 is electrically disconnected by the switch SW13. Even if the third switching signal φ3 is inverted to a low level, there is a slight time lag until the switch SW13 actually turns off. During this time lag, the voltage of the capacitor C11 becomes a voltage Va slightly lower than the threshold voltage Vth. descend. This voltage Va is maintained until the OFF period (discharge period) of the first switching signal φ1 ends (see FIGS. 15E and 15F), and becomes the voltage at the start of charging in the next charging period.

  Therefore, the voltage Va becomes a voltage at the start of charging in each ON period (charging period) of the first switching signal φ1 (hereinafter, referred to as “charging start voltage Va”), and the capacitor C11 is set in accordance with the amplitude E of the audio signal eS. This is the reference voltage for increasing the charging end voltage Vc.

  The output rsout1 output from the other output terminal of the first RS flip-flop circuit 60 is inverted to a low level when the first set signal set1 is input, and then high when the first reset signal res1 is input. Invert to level. That is, from the other output terminal of the first RS flip-flop circuit 60, a pulse signal having the same pulse width as the discharge time of the capacitor C11 (time until the charge end voltage Vc decreases to the threshold voltage Vth) for each discharge period. Is output (see FIG. 15G).

  The capacitor C12 is charged and discharged in the same manner as the capacitor C11, and from the other output terminal of the second RS flip-flop circuit 61, the discharge time of the capacitor C12 decreases from the charge end voltage Vc to the threshold voltage Vth every discharge period. The output rsout2 composed of a pulse signal having the same pulse width as the time until () is output.

  Since the charging / discharging operation of the capacitor C12 is controlled based on the second switching signal φ2, the charging / discharging period is shifted by a half cycle of the reference clock MCLK with respect to the charging / discharging period of the capacitor C11. Therefore, the pulse signal of the output rsout1 and the pulse signal of the output rsout2 are alternately generated every half cycle of the reference clock MCLK.

  A pulse width modulation signal PWMout obtained by synthesizing the output rsout1 and the output rsout2 is output from the signal output circuit 62 (see FIG. 15 (h)).

  A solid line L1 shown in FIG. 15 (e) shows a waveform when the audio signal eS is a no-signal (Δi = 0), which is a charge / discharge waveform of the capacitor C11. When the audio signal eS is no signal (Δi = 0), the capacitor C11 is charged by the DC bias current Ic. The DC bias current Ic has the charge end voltage Vc of the power supply voltage Vcc of the first RS flip-flop circuit 60. And the potential Vm of the middle point of the threshold voltage Vth (≈ (Vcc−Vth) / 2, hereinafter referred to as “middle point voltage Vm”).

  When the amplitude E of the audio signal eS is positive (Ij = Ic + Δi), the slope of the charging waveform becomes steeper than the solid line L1 depending on the magnitude of the amplitude E, and the amplitude E of the audio signal eS is a predetermined value. If the level becomes excessively higher than this level (this level is assumed to be “+ Es”), the charging end voltage Vc is substantially equal to the power supply voltage + Vcc (exactly Is continuously clipped to the power supply voltage + Vcc + the forward voltage of the protection diode incorporated in the input terminal of the NAND circuit, and is thus fixed. Therefore, when the positive amplitude E of the audio signal eS is excessive, the pulse width of the pulse width modulation signal PWMout is fixed regardless of the magnitude of the amplitude E.

  On the other hand, when the amplitude E of the audio signal eS is negative (Ij = Ic−Δi), the slope of the charging waveform becomes gentler than the solid line L1 depending on the magnitude of the amplitude E, and the amplitude of the audio signal eS. When E becomes larger than a predetermined level (this level is set to “−Es”), the charging current Ij is clipped to “0”, and the charge / discharge waveform thereof is shown in FIG. It becomes like this.

  In this case, since the voltage of the capacitor C11 and the second capacitor C12 does not rise above the threshold voltage Vth in each charging period, an output rsout1 and an output rsout2 having a pulse signal having a pulse width corresponding to the discharging time are generated in each discharging period. Instead, the pulse width modulation signal PWMout is not a pulse signal, but is fixed at a low level as shown in FIG.

JP 2008-206128 A JP 2009-141408 A JP 2010-273326 A

  In the method of generating the pulse width modulation signal PWMout in the pulse width modulation circuit 51, the discharge time of the capacitors C11 and C12 in each discharge period is basically made to correspond to the amplitude E of the audio signal eS. Since it is determined by the charge end voltage Vc with reference to the charge start voltage Va of C11 and C12, the charge start voltage Va in each charge period is the amplitude E of the audio signal eS including the case where the amplitude E is clipped. It is important to be stable even if it changes.

  However, when the amplitude E of the audio signal eS becomes excessively negative in the range of E <−Es, the charging current Ij decreases to almost 0. Therefore, when such a state continues, (e ), The capacitor C11 and the capacitor C12 are not charged from the charging start voltage Va to the threshold voltage Vth or higher in each charging period. For this reason, as described above, the discharge time does not occur in the discharge period following each charge period, and the level of the pulse width modulation signal PWMout remains low and does not change ((h) in FIG. 16). (Refer to the waveform of).

  In a state where the level of the pulse width modulation signal PWMout is fixed at a low level, distortion occurs in the sound reproduced from the pulse width modulation signal PWMout, but the waveform E of the pulse width modulation signal PWMout itself has an amplitude E of −Es. This phenomenon is not a problem peculiar to the method of generating the pulse width modulation signal PWMout, but the voltage of the capacitors C11 and C12 is changed to the threshold voltage Vth during each charging period. Since the charging start voltage Va becomes unstable when it does not increase more than this, it is an important problem in the method of generating the pulse width modulation signal PWMout.

  That is, in the period T1 in FIG. 16, when the audio signal eS is excessively negative (the state where eS <−Es) and the charging current Ij is almost 0, the capacitor C11 is not charged, and until the end of charging. The charging start voltage Va is held. Then, since the third switching signal φ3 is instantaneously turned on by the first set signal set1 at the falling timing of the first switching signal φ1, the switch SW3 is turned on only during the ON period, and the accumulated charge in the capacitor C11 is discharged. As a result, the voltage of the capacitor C11 is slightly lower than the charging start voltage Va.

  In the period T2 and the period T3 following the period T1, the discharging operation and the charging operation are substantially not performed, so the voltage of the capacitor C11 is held at the voltage Va ′ slightly lower than the charging start voltage Va, and this voltage Va ′. Becomes the charging start voltage in the period T4 following the period T3. In the period T4, the operation similar to that in the period T1 is reproduced, so that the voltage of the capacitor C11 is lowered to a voltage slightly lower than the voltage Va ′. Thereafter, the same phenomenon is repeated and charging of the capacitor C11 is started. The voltage gradually decreases from the initial charging start voltage Va. The above phenomenon is the same for the capacitor C12, and the charging start voltage of the capacitor C12 also decreases stepwise from the initial charging start voltage Va.

  Since the charging start voltage Va of the capacitors C11 and C12 decreases step by step for each cycle of the first switching signal φ1 and the second switching signal φ2, the amplitude E of the audio signal eS is excessively negative (E < -Es state) continues for several cycles to several tens of cycles, the amount of decrease from the charging start voltage Va of the capacitors C11 and C12 increases, and the amplitude E of the audio signal eS is excessively negative (E Even if the state returns to the normal state (the state of −Es <E <0) from the state of <−Es), depending on the charging current Ij (= Ic−Δi) at that time, the capacitors C11 and C12 may The voltage may not rise above the threshold voltage Vth from the charging start voltage (<Va).

  For example, as shown in FIG. 17, the capacitor when the audio signal eS is returned to the normal state (the state of −Es <E <0) from the amplitude E (the state of E <−Es) that is excessively negative on the negative side. When the charging start voltage of C11 is reduced to Va1 (<Va), if the capacitor C11 is charged with the charging current Ij from the charging start voltage Va in the charging period TA, the charging is performed as shown by the dashed line waveform. Although the end voltage Vc is higher than the threshold voltage Vth, as shown by the solid line, the charge start is charged from the voltage Va1, and therefore, when the charge end voltage Vc does not reach the threshold voltage Vth, it is discharged in the discharge period TB. The time t cannot be obtained, and the pulse width modulation signal PWMout remains held at the low level.

  The charging start voltage Va of the capacitor C11 changes from Va1 to Va2 (Va1 <Va2 <Vth) during the discharging period TB, and the capacitor C11 is charged with the charging current Ij from the voltage Va2 during the next charging period TC, and the charging ends. Even if the voltage Vc exceeds the threshold voltage Vth, the discharge time t ′ detected in the discharge period TD is shorter than the correct discharge time t ″, and the pulse width modulation signal PWMout generated based on the discharge time t ′ The pulse does not correspond to the amplitude E of the audio signal eS.

  That is, as the charging start voltage Va decreases stepwise, the amplitude E of the audio signal eS is excessive from the negative side (state of E <−Es) to the normal state (state of −Es <E <0). The responsiveness of the pulse width modulation signal PWMout at the timing of returning to is delayed at least during the period TA to TD (two periods of the reference clock MCLK), and the distorted state of the reproduced sound continues until the time lag period. Arise.

  In order to solve this problem, the present applicant disclosed in Japanese Patent Application Laid-Open No. 2009-141408 a current Ij obtained by adding an auxiliary current Imin to a current (Ic ± Δi) obtained by voltage-to-current conversion of an audio signal eS in a charging current generation circuit. When the amplitude of the audio signal becomes excessive on the negative side, a pulse width modulation circuit is proposed that limits the current Ij so that it does not fall below Imin. However, according to this pulse width modulation circuit, a signal current always flows through a non-linear element such as the diode D1, and high-precision pulse width modulation cannot be performed (as a result, sound quality of the audio signal is deteriorated). There's a problem.

  The present invention has been made to solve the above-described conventional problems, and its purpose is to immediately perform normal pulse width modulation when the input signal returns to a normal state even when the input signal becomes excessively negative. To provide a pulse width modulation circuit that can output a signal and does not need to insert a non-linear element in series in the signal path.

  A pulse width modulation circuit according to a preferred embodiment of the present invention is configured to execute a charging operation during a period of one level of the reference clock and a period of the other level of the reference clock. A charge control signal generating unit for generating the second control signal, and the charge accumulated in the charging operation during the other level period following the one level period during which the charging operation is performed by the first control signal. A discharge operation of the charge accumulated in the charging operation in a period of one level following a third control signal for executing the discharging operation of the second level and a period of the other level in which the charging operation is executed by the second control signal A discharge control signal generation unit that generates a fourth control signal for executing the first control signal, and a charging current generated based on the level of the input signal in accordance with the first control signal. In each period during which the discharge operation is performed, a charge operation for charging the capacitor and a discharge operation for discharging the accumulated charge of the first capacitor with a constant discharge current according to the third control signal. A first pulse signal generation unit for generating a first pulse signal having a pulse width as a discharge time until the first capacitor changes from a level at the start of discharge to a reference level; and according to the second control signal A charging operation for charging the second capacitor with the charging current, and a discharging operation for discharging the accumulated charge of the second capacitor with the discharging current according to the fourth control signal, and executing the discharging operation. A second pulse signal generator for generating a second pulse signal having a pulse width that is a discharge time until the second capacitor changes from the level at the start of discharge to the reference level during each period The first pulse signal generated by the first pulse signal generation unit and the second pulse signal generated by the second pulse signal generation unit are synthesized, and the pulse width of each pulse is equal to the input signal. A pulse signal synthesizer that outputs a pulse width modulation signal that changes according to the level, and supplies a voltage to the first capacitor and the second capacitor when the negative amplitude of the input signal exceeds a predetermined level Thus, a voltage maintaining unit that maintains the voltages of the first capacitor and the second capacitor at a predetermined voltage is provided.

  In a preferred embodiment, the voltage maintaining unit includes a voltage source that supplies the voltage, a cathode connected to the first capacitor, an anode connected to the voltage source, and a cathode connected to the second capacitor. A second diode connected to the capacitor and having an anode connected to the voltage source.

  In a preferred embodiment, the voltage source has one end connected to the first power source, the other end connected to the anode of the first diode and the anode of the second diode, and one end connected to the first power source. Connected to two power sources, the other end connected to the anode of the first diode and the anode of the second diode, and one end connected to the connection point of the first resistor and the second resistor And a third capacitor having the other end connected to the second power source.

  In a preferred embodiment, the voltage obtained by subtracting the voltage across the first diode from the voltage of the voltage source is set to the predetermined voltage, and the voltage obtained by subtracting the voltage across the second diode from the voltage of the voltage source is The predetermined voltage is set.

  In a preferred embodiment, the voltage maintaining unit includes a voltage source that supplies the voltage, a first terminal connected to the first capacitor, and a second terminal and a control terminal connected to the voltage source. A transistor; and a second transistor having a first terminal connected to the second capacitor and a second terminal and a control terminal connected to the voltage source.

  In a preferred embodiment, the voltage source includes a first resistor having one end connected to the first power supply and the other end connected to the control terminal of the first transistor and the control terminal of the second transistor, and one end Is connected to the second power source, the other end is connected to the control terminal of the first transistor and the control terminal of the second transistor, and one end of the first resistor and the second resistor. A third capacitor connected to the connection point and having the other end connected to the second power source.

  In a preferred embodiment, a voltage obtained by subtracting a voltage between the control terminal and the first terminal of the first transistor from the voltage of the voltage source is set to the predetermined voltage, and the second transistor is determined from the voltage of the voltage source. A voltage obtained by subtracting the voltage between the control terminal and the first terminal is set to the predetermined voltage.

  In a preferred embodiment, the voltage maintaining unit supplies a voltage to the first capacitor and the second capacitor when the amplitude of the negative side of the input signal exceeds a predetermined level, and the negative side of the input signal When the amplitude of the voltage source does not exceed a predetermined level, the voltage value of the voltage source is changed so that the voltage is not supplied to the first capacitor and the second capacitor.

  In a preferred embodiment, the voltage source is supplied with the first pulse signal generated by the first pulse signal generation unit, and the first pulse signal when the first pulse signal is at a high level. A third capacitor that is charged by the voltage of the signal and that discharges the voltage charged by the voltage of the first pulse signal when the first pulse signal is at a low level; The voltage value of the voltage source is changed by adding the charging voltage of the third capacitor charged by the voltage of the first pulse signal.

  In a preferred embodiment, the voltage source has one end connected to a predetermined potential, the other end connected to the anode of the first diode and the anode of the second diode, and one end connected to the first resistor. A third capacitor connected to the other end of one resistor, the other end connected to the predetermined potential, a second resistor connected to one end of the first capacitor, and a cathode connected to the other end of the second resistor The anode includes a third diode to which the first pulse signal is supplied.

  In a preferred embodiment, the voltage source includes a first resistor having one end connected to a predetermined potential and the other end connected to the control terminal of the first transistor and the control terminal of the second transistor, and one end A third capacitor connected to the other end of the first resistor, the other end connected to the predetermined potential, a second resistor connected to one end of the first capacitor, and a cathode connected to the second resistor. A third diode connected to the other end and supplied with the first pulse signal is included in the anode.

  By having the above configuration, the present invention can output a normal pulse width modulation signal immediately after returning to a normal state even when the input signal becomes excessive on the negative side, and in the signal path. A pulse width modulation circuit that does not require insertion of a nonlinear element can be provided.

It is a block diagram which shows the switching amplifier of this invention. It is a block diagram which shows the pulse width modulation circuit of this invention. It is a circuit diagram which shows the principal part of the pulse width modulation circuit of this invention. It is a time chart in case the amplitude of an audio signal is fluctuating in a normal range. It is a figure which shows the relationship between an audio signal (alternating voltage signal) and an output current. 3 is a circuit diagram showing a charging start voltage maintaining circuit 20. FIG. 3 is a circuit diagram showing a charging start voltage maintaining circuit 20. FIG. It is a circuit diagram which shows a pulse generation circuit and a pulse synthesis circuit. It is a figure which shows pulse width modulation operation | movement. It is a time chart in case the amplitude of an audio signal is fluctuating in an excessive range on the positive side. It is a time chart in case the amplitude of an audio signal is fluctuating in an excessive range on the negative side. It is a circuit diagram which shows the charging start voltage maintenance circuit 20 '. It is a circuit diagram which shows the charging start voltage maintenance circuit 20 '. It is a time chart for demonstrating operation | movement of the charge start voltage maintenance circuit 20 '. It is a wave form diagram which shows the charge voltage of the capacitor | condenser C51. It is a circuit diagram which shows the conventional pulse width modulation circuit. It is a timing chart which shows the voltage waveform of each signal in the pulse width modulation circuit shown in FIG. It is a timing chart which shows the voltage waveform of each signal in the pulse width modulation circuit shown in FIG. It is a figure which shows the change of the voltage of a capacitor | condenser when an audio signal returns to a normal state from an excessive state to the negative side.

  FIG. 1 is a block diagram showing a switching amplifier to which a pulse width modulation circuit of the present invention is applied. The switching amplifier includes a pulse width modulation circuit 1 connected to the audio signal generation source AU, a switching circuit 2, a low-pass filter 3, a first power supply 4 and a second power supply 5 for supplying positive and negative power supply voltages + EB and -EB. And. A speaker as a load RL is connected to the output of the low-pass filter 3.

  The pulse width modulation circuit 1 converts the audio signal eS as an input signal output from the audio signal generation source AU into a pulse width modulation signal PWMout and outputs the pulse width modulation signal PWMout. The pulse width modulation signal PWMout output from the pulse width modulation circuit 1 is input to the switching circuit 2.

  The switching circuit 2 includes a switching element SW-A whose on / off operation is controlled by the pulse width modulation signal PWMout, an inverter 2a for inverting the phase of the pulse width modulation signal PWMout, and a phase output from the inverter 2a. The switch element SW-B whose on / off operation is controlled by the pulse width modulation signal PWMout ′ and the reverse current prevention diodes DA, D- connected to both ends of the switch elements SW-A, SW-B, respectively. B.

  In the switching circuit 2, positive and negative power supply voltages + EB and -EB are supplied from the first power supply 4 and the second power supply 5 to the load RL via the switch element SW-A and the switch element SW-B, respectively. Since the SW-A and the switch element SW-B are alternately turned on and off by the pulse width modulation signal PWMout and the pulse width modulation signal PWMout ′, respectively, the power supply voltage + EB and the power supply are supplied to the low pass filter 3 and the load RL. Voltage -EB is supplied alternately. That is, the load RL is supplied with a rectangular wave voltage having the same duty ratio as that of the pulse width modulation signal PWMout, with the level changing between + EB and -EB via the low-pass filter 3.

  The low-pass filter 3 is configured by an LC circuit including a coil L0 and a capacitor C0. The low pass filter 3 removes a high frequency component of the rectangular wave voltage input from the switching circuit 2. The low-pass filter 3 outputs an AC voltage signal (AC voltage signal having substantially the same waveform as the audio signal eS) obtained by demodulating the pulse width modulation signal PWMout, and this AC voltage signal is supplied to the load RL. Output as audio.

  FIG. 2 is a block diagram of the pulse width modulation circuit 10. FIG. 3 is a circuit diagram of a circuit related to the charge / discharge operation included in the pulse width modulation circuit 10 (see the circuit surrounded by the one-dot chain line in FIG. 2).

  As shown in FIG. 2, the pulse width modulation circuit 10 includes a clock generation circuit 11, a differential amplification circuit 12, a first charging current generation circuit 13, a second charging current generation circuit 14, and switches SW1 to SW4. , Capacitors C1, C2, first discharge constant current circuit 15, second discharge constant current circuit 16, first pulse generation circuit 17, second pulse generation circuit 18, pulse synthesis circuit 19, and charging And a start voltage maintaining circuit 20. Note that the timing chart of FIG. 4 showing the operation of the pulse width modulation circuit 10 is referred to as needed.

  The clock generation circuit 11 generates a reference clock signal MCLK (see FIG. 4A), and generates a first control signal φ1 and a second control signal φ2 from the reference clock signal MCLK. The reference clock signal MCLK is a clock signal having a duty ratio of about 50% and serves as a reference signal for the first and second control signals φ1 and φ2. The first and second control signals φ1 and φ2 are signals for controlling the on / off operations of the switches SW1 and SW2 in order to cause the capacitors C1 and C2 to perform the charging operation. The second control signal φ2 has an antiphase relationship with the first control signal φ1. The clock generation circuit 11 outputs the first control signal φ1 to the switch SW1, and outputs the second control signal φ2 to the switch SW2.

  The clock generation circuit 11 generates first and second set signals set1, set2 from the first and second control signals φ1, φ2. As shown in FIG. 4D, the first set signal set1 is a signal that detects a rising edge when the first control signal φ1 is inverted from a low level to a high level, and the second set signal set2 As shown in FIG. 4 (e), this is a signal that detects a rising edge when the second control signal φ2 is inverted from a low level to a high level. The first set signal set1 is input as a set signal to the first pulse generation circuit 17 configured by an RS latch circuit, and the second set signal set2 is a second pulse generation circuit configured by an RS latch circuit. 18 is input as a set signal.

  The differential amplifier circuit 12 is a circuit that amplifies and outputs the amplitude of the audio signal eS supplied from the audio signal generation source AU to the pulse width modulation circuit 10 with reference to the ground potential. In the differential amplifier circuit 12, the emitters of the two transistors are connected to each other, the collectors of both transistors are connected to a positive power supply (power supply voltage + V) via resistors, and the emitters of both transistors are connected via a constant current circuit. And a circuit connected to a negative power supply (power supply voltage -V). In the differential amplifier circuit 12, the audio signal eS is input to the base of one transistor and the base of the other transistor is connected to the ground potential, so that the ground potential of the audio signal eS is used as a reference between the collectors of both transistors. A voltage obtained by amplifying the difference voltage (the amplitude of the audio signal eS) is output. This differential voltage is output to the first and second charging current generation circuits 13 and 14.

  The first and second charging current generation circuits 13 and 14 are circuits that convert the voltage output from the differential amplifier circuit 12 into a current that changes in proportion to the change in the voltage. The first charging current generation circuit 13 and the second charging current generation circuit 14 have the same circuit configuration. The first charging current generation circuit 13 is connected to the capacitor C1, and charges the capacitor C1 by supplying the voltage-current converted current to the capacitor C1. Accordingly, the first charging current generation circuit 13 generates a charging current for charging the capacitor C1. The second charging current generating circuit 14 is connected to the capacitor C2, and charges the capacitor C2 by supplying the voltage-current converted current to the capacitor C2. Therefore, the second charging current generation circuit 14 generates a charging current for charging the capacitor C2.

  When the conversion conductance in the first and second charging current generation circuits 13 and 14 is Gm, the current Δi converted from the audio signal eS by the first and second charging current generation circuits 13 and 14 is Δi = Gm · eS. Can be represented. If the bias current in the first and second charging current generation circuits 13 and 14 is Ic, the charging current of the two capacitors C1 and C2 can be expressed as Ic + Gm · eS = Ic + Δi.

  The switch SW1 is a circuit that controls whether to supply the power supply voltage + V to the first charging current generation circuit 13, that is, whether to operate the first charging current generation circuit 13 to charge the capacitor C1. The switch SW2 is a circuit that controls whether or not the power supply voltage + V is supplied to the second charging current generation circuit 14, that is, whether or not the second charging current generation circuit 14 is operated to charge the capacitor C2. The switch SW1 and the switch W2 have the same circuit configuration. The switches SW1 and SW2 are turned on and off based on the first and second control signals φ1 and φ2 output from the clock generation circuit 11. The switch SW1 is turned on when the first control signal φ1 is at a low level, and is turned off when the first control signal φ1 is at a high level. The switch SW2 is turned on when the second control signal φ2 is at a low level, and is turned off when the second control signal φ2 is at a high level.

  The first discharging constant current circuit 15 is a circuit for discharging the accumulated charge of the capacitor C1 charged with the charging current (Ic + Δi), and the second discharging constant current circuit 15 is charged with the charging current (Ic + Δi). This is a circuit for discharging the stored charge of the capacitor C2. The first constant current circuit for discharging 15 is connected to the capacitor C1, and discharges the accumulated charge of the capacitor C1 by drawing the charge accumulated in the capacitor C1 with a constant discharge current Id. On the other hand, the second constant current circuit 16 for discharge is connected to the capacitor C2, and discharges the accumulated charge of the capacitor C2 by drawing the charge accumulated in the capacitor C2 by a constant discharge current Id.

  The switch SW3 is a circuit that controls whether or not the power supply voltage −V is supplied to the first discharging constant current circuit 15, that is, whether or not the capacitor C1 is discharged by operating the first discharging constant current circuit 15. The switch SW4 determines whether or not to supply the power supply voltage −V to the second discharge constant current circuit 16, that is, whether or not the second discharge constant current circuit 16 is operated to discharge the capacitor C2. It is a circuit to control. The switch SW3 and the switch W4 have the same circuit configuration. The switches SW3 and SW4 are turned on and off based on the third and fourth control signals φ3 and φ4 output from the first and second pulse generation circuits 17 and 18, respectively. The switch SW3 is turned on when the third control signal φ3 is at a high level, and is turned off when the third control signal φ3 is at a low level. The switch SW4 is turned on when the fourth control signal φ4 is at a high level, and is turned off when the fourth control signal φ4 is at a low level.

  The capacitors C1 and C2 are elements for converting the amplitude of the audio signal eS into time. The amplitude of the audio signal eS is obtained by charging the capacitors C1 and C2 with a charging current (Ic + Δi) proportional to the amplitude of the audio signal eS for a certain period of time (half the period T of the reference clock signal MCLK). Is discharged with a constant discharge current Id, and converted into time by generating a pulse having the discharge time as a pulse width.

  The first pulse generation circuit 17 uses a first pulse signal rsout1 (see FIG. 4) having a pulse width as a discharge time until the voltage across the capacitor C1 changes from the voltage level at the start of discharge to a predetermined threshold voltage (reference level) Vth. (J)) and a third control signal φ3 (see FIG. 4H) for controlling the on / off operation of the switch SW3. In the present embodiment, as will be described later, the first pulse generation circuit 17 and the second pulse generation circuit 18 are configured by an RS latch circuit using a NAND circuit, so that the threshold voltage Vth is the threshold voltage of the NAND circuit. It becomes.

  The first pulse signal rsout1 is output to the pulse synthesis circuit 19, and the third control signal φ3 is output to the switch SW3. The second pulse generation circuit 18 uses the second pulse signal rsout2 (see FIG. 4 (k)) to make the discharge time until the voltage across the capacitor C2 changes from the voltage level at the start of discharge to the threshold voltage Vth described above. ) And a fourth control signal φ4 (see FIG. 4I) for controlling the on / off operation of the switch SW4. The second pulse signal rsout2 is output to the pulse synthesizing circuit 19, and the fourth control signal φ4 is output to the switch SW4.

  The pulse synthesis circuit 19 synthesizes the first and second pulse signals rsout1 and rsout2 output from the first and second pulse generation circuits 17 and 18, and outputs them as a PWM modulation signal PWMout (see FIG. 4 (l)). Circuit.

  When the amplitude of the audio signal eS fluctuates in an excessive range on the negative side (a range of −Es or less), the charging start voltage maintaining circuit 20 performs a discharging operation in which the charging start voltage of the capacitors C1 and C2 is constant current Id. Therefore, the charging start voltage of the capacitors C1 and C2 is maintained at Va. The reason why the charging start voltage maintaining circuit 20 is provided will be described. FIG. 5 is a diagram showing the relationship between the input audio signal eS and the output current IS (charging current) from the charging current generating circuit.

  As shown in FIG. 5B, the current Is output from the charging current generation circuit varies in the range of 0 or more according to the amplitude ± E of the audio signal eS. Even if the positive amplitude + E of the audio signal eS is excessive (refer to the portion of + E ≧ + Es in FIG. 5A), the current IS is changed to the amplitude + E of the audio signal eS as shown in FIG. 5B. The current Ic + Δi = Ic + Gm · E changes accordingly. However, when the amplitude −E on the negative side of the audio signal eS is excessive (see the portion −E ≦ −Es in FIG. 5A), the current IS is “0. (See the part (a)).

  Therefore, when the amplitude ± E of the audio signal eS fluctuates in the voltage range A (range of −Es or more) in FIG. 5A, the current IS (= Ic ± Δi = Ic ± Gm · E) is output. On the other hand, when the amplitude -E of the audio signal eS varies within the voltage range B (a range equal to or less than -Es) in FIG. 5A, no current is output regardless of the variation.

  Even if the positive amplitude + E of the audio signal eS is excessive and the charging current Ij of the capacitors C1 and C2 becomes equal to or higher than IP, the charging waveform of the capacitors C1 and C2 is almost equal to the charging end voltage Vc of the capacitor C1. Clipped to the power supply voltage + Vcc of the second RS flip-flop circuits 17 and 18.

  When the amplitude −E on the negative side of the audio signal eS varies in the range of −E <−Es, the charging current Ij becomes “0”. Even if connected to C1, charging is not substantially performed, and the voltage of the capacitor C1 does not rise from the charging start voltage Va. When this state continues for several cycles to several tens of cycles of the reference clock MCLK, there arises a problem that the charging start voltage of the capacitor C1 decreases stepwise. The same applies to the capacitor C2.

  The reason why the charging start voltage Va decreases stepwise is, for example, that the following operation is performed in the case of the capacitor C1. That is, since the charge current Ij in each charging period becomes “0”, the capacitor C1 does not substantially accumulate charges in each charging period (the voltage of the capacitor C1 does not increase), and the charging end voltage Vc is The charging start voltage Va is the same. Since the charging start voltage is smaller than the threshold voltage Vth, the input terminal to which a first reset signal res1 of the first RS flip-flop circuit 17 described later is input is at a low level. In this state, when the first set signal set1 is input to the first RS flip-flop circuit 17 at the end of the charging period (at the start of discharging), both input terminals of the first RS flip-flop circuit 17 are simultaneously at a low level (indefinite state). ), And the third switching signal φ3 output from the first flip-flop circuit 17 instantaneously becomes a high level. This is because the accumulated charge of the capacitor C1 is instantaneously discharged by the discharge current Id, and the voltage of the capacitor C1 is reduced while being minute. The same applies to the capacitor C2.

  In order to solve this problem, the charging start voltage maintaining circuit 20 supplies the power supply voltage to the capacitors C1 and C2 when the voltages of the capacitors C1 and C2 are about to be lower than the voltage Va by the discharging operation with the constant current Id. By doing so, the charging start voltage of the capacitors C1 and C2 is prevented from lowering than Va. As shown in FIGS. 2 and 3, the charging start voltage maintaining circuit 20 includes diodes D51 and D52 and a voltage source Vx.

  A detailed circuit of the charging start voltage maintaining circuit 20 is shown in FIG. 6A. The charge start voltage maintaining circuit 20 includes diodes D51 and D52, resistors R51 and R52, a capacitor C51, and power supplies + Vcc and −Vcc. The resistors R51 and R52, the capacitor C51, and the power sources + Vcc and -Vcc constitute a voltage source Vx. The cathode of the diode D51 is connected to the capacitor C1, and its anode is connected to the connection point between the resistors R51 and R52 and the capacitor C51. The cathode of the diode D52 is connected to the capacitor C2, and the anode thereof is connected to the connection point between the resistors R51 and R52 and the capacitor C51. The resistor R51 is connected to the power source + Vcc, and the resistor R52 and the capacitor C51 are connected to the power source -Vcc.

  With the above configuration, when the voltage of the capacitor C1 is reduced by the constant current Id to be lower than the voltage value obtained by subtracting the voltage Vd51 across the diode D51 from the voltage V1 at the connection point of the resistor R51, the resistor R52, and the capacitor C51, the voltage source A voltage is supplied from Vx to the capacitor C1 (current flows), thereby preventing a decrease in the voltage of the capacitor C1. Similarly, if the voltage of the capacitor C2 is reduced by a constant current Id to lower than the voltage value obtained by subtracting the voltage Vd52 across the diode D52 from the voltage V1 at the connection point of the resistor R51, the resistor R52 and the capacitor C51, the voltage source Vx Is supplied to the capacitor C2 (current flows), thereby preventing the voltage of the capacitor C2 from decreasing. That is, each element (resistor, capacitor, diode, etc.) of the charging start voltage maintaining circuit 20 is set such that the voltage value obtained by subtracting the voltage Vd51 across the diode D51 (or the voltage Vd52 across the diode D52) from the voltage V1 is Va. Value is set.

  FIG. 6B shows a detailed circuit of the charging start voltage maintaining circuit 20 according to another embodiment. In FIG. 6B, transistors Q51 and Q52 are provided instead of the diodes D51 and D52. The transistor Q51 has an emitter connected to the capacitor C1, a base connected to a connection point between the resistor R51, the resistor R52, and the capacitor C51, and a collector connected between the resistor R51 and the power source + Vcc. The transistor Q52 has an emitter connected to the capacitor C2, a base connected to a connection point between the resistor R51, the resistor R52, and the capacitor C51, and a collector connected between the resistor R51 and the power source + Vcc.

  With the above configuration, when the voltage of the capacitor C1 is to be lowered by the constant current Id than the voltage value obtained by subtracting the base-emitter voltage Vbe51 of the transistor Q51 from the voltage V1 at the connection point of the resistor R51, the resistor R52 and the capacitor C51. By supplying a voltage from the voltage source Vx to the capacitor C1 (current flows), a decrease in the voltage of the capacitor C1 is prevented. Similarly, when the voltage of the capacitor C2 is to be lowered by a constant current Id from a voltage value obtained by subtracting the base-emitter voltage Vbe52 of the transistor Q52 from the voltage V1 at the connection point of the resistors R51, R52 and the capacitor C51. By supplying a voltage from the voltage source Vx to the capacitor C2 (current flows), a decrease in the voltage of the capacitor C2 is prevented. That is, each element (resistor, resistance, and voltage) of the charging start voltage maintaining circuit 20 is set such that a voltage value obtained by subtracting the base-emitter voltage Vbe51 of the transistor Q51 (or the base-emitter voltage Vbe52 of the transistor Q52) from the voltage V1 is Va. Capacitor, transistor, etc.) are set.

  Next, the details of the circuit related to the charge / discharge operation (refer to the circuit surrounded by the one-dot chain line in FIG. 2) will be described with reference to FIG. The circuits having the same functions as those in FIG.

  The differential amplifier circuit 12 includes an npn transistor Q1 and an npn transistor Q2. The emitter of transistor Q1 and the emitter of transistor Q2 are connected to a constant current circuit via resistors R3 and R4, respectively, and the collector of transistor Q1 and the collector of transistor Q2 are positive via resistors R1 and R2, respectively. Connected to a power source (power voltage + V).

  The audio signal eS is input to the base of the transistor Q1 via the coupling capacitor Ca, and the base of the transistor Q2 is connected to the ground potential.

  The constant current circuit includes an npn transistor Q3, a resistor R6, and a Zener diode (constant voltage diode) D1. The transistor Q3 has an emitter connected to a negative power supply (power supply voltage −V) via a resistor R6, a base connected to a positive power supply (power supply voltage + V) via a resistor R11, and a collector connected to the resistors R3 and R4. It is connected to the. Zener diode D1 is connected between the base of transistor Q3 and a negative power supply. Since the base voltage of the transistor Q3 becomes the Zener voltage Vz of the Zener diode D1, a constant current Id of (Vz−Vbe) / R6 (Vbe is a voltage between the base and emitter of the transistor Q3) flows through the collector of the transistor Q3.

  The first charging current generation circuit 13 includes a pnp transistor Q4 and a current limiting resistor R7 connected to the emitter of the transistor Q4. The second charging current generation circuit 14 includes a pnp transistor Q5 and a current limiting resistor R8 connected to the emitter of the transistor Q5. Each of the switches SW1 and SW2 includes a pnp type transistor. The switch SW1 and the first charging current generation circuit 13 are connected in series, and the switch SW2 and the second charging current generation circuit 14 are connected in series. The emitter of the switch SW1 and the emitter of the switch SW2 are both connected to a positive power supply (power supply voltage + V). The collector of the transistor Q4 is connected to the capacitor C1, and the collector of the transistor Q5 is connected to the capacitor C2.

  The collector of the transistor Q1 is connected to the bases of the transistors Q4 and Q5, and the amplitude based on the ground potential of the audio signal es is input from the differential amplifier circuit 12. The first control signal φ1 is input from the clock generation circuit 11 to the base of the switch SW1, and the second control signal φ2 is input from the clock generation circuit 11 to the base of the switch SW2.

  The first discharging constant current circuit 15 and the second discharging constant current circuit 16 are composed of the same circuit as the constant current circuit in the differential amplifier circuit 12. Switch SW3 and switch SW4 include npn transistors. The first discharging constant current circuit 15 and the third switch SW3 are connected in series, and the second discharging constant current circuit 16 and the fourth switch SW4 are connected in series. The first discharge constant current circuit 15 and the second discharge constant current circuit 16 are constant current circuits using an npn transistor, an emitter resistor, and a Zener diode, but the first and second discharge constant current circuits 15. , 16 Zener diodes for providing base voltages of npn transistors share the constant current circuit Zener diode D1 in the differential amplifier circuit 12.

  Accordingly, the collector of the transistor Q6 constituting the first discharging constant current circuit 15 is connected to the capacitor C1, and the emitter of the transistor Q6 is connected to the collector of the switch SW3 via the resistor R9. The collector of the transistor Q7 constituting the second discharging constant current circuit 16 is connected to the capacitor C2, and the emitter of the transistor Q7 is connected to the collector of the switch SW4 via the resistor R10. The bases of the transistors Q6 and Q7 are connected to the cathode of the Zener diode D1.

  The emitters of the switch SW3 and the switch SW4 are connected to a negative power supply (power supply voltage −V), and the third control signal φ3 output from the first pulse generation circuit 17 is input to the base of the switch SW3. A fourth control signal φ4 output from the second pulse generation circuit 18 is input to the base of the switch SW4.

  In the circuit of FIG. 3, when the first control signal φ <b> 1 becomes low level, the switch SW <b> 1 is turned on, the positive power supply (+ V) is connected to the first charging current generation circuit 13, and the first charging current generation circuit 13 The transistor Q4 operates. Since the differential voltage of the audio signal eS with respect to the ground potential, that is, the amplitude value of the audio signal eS is input from the differential amplifier circuit 12 to the base of the transistor Q4, the collector of the transistor Q4 is proportional to the amplitude value of the audio signal e. The charging current (Ic + Δi) flows, and the capacitor C1 is charged by this charging current (Ic + Δi) during the low level period of the first control signal φ1 (waveforms in the periods T1 and T3 in FIGS. 4B and 4F). reference).

  Similarly, when the second control signal φ2 becomes low level, the switch SW2 is turned on, the positive power supply (+ V) is connected to the second charging current generation circuit 14, and the transistor Q5 in the second charging current generation circuit 14 is connected. Works. Since the differential voltage of the audio signal eS with respect to the ground potential is also input from the differential amplifier circuit 12 to the base of the transistor Q5, a charging current (Ic + Δi) proportional to the amplitude value of the audio signal e flows through the collector of the transistor Q5. The capacitor C2 is charged by this charging current (Ic + Δi) during the low level period of the second control signal φ2 (see the waveforms in the periods T2 and T4 in FIGS. 4C and 4G).

  Further, when the third control signal φ3 becomes high level, the switch SW3 is turned on, a negative power source (−V) is connected to the first discharge constant current circuit 15, and the first discharge constant current circuit 15 Transistor Q6 operates to draw a constant current Id. As a result, the electric charge accumulated in the capacitor C1 is discharged with the constant current Id (see the waveforms in the periods T2 and T4 in FIGS. 4F and 4H).

  Similarly, when the fourth control signal φ4 becomes high level, the switch SW4 is turned on, the negative power source (−V) is connected to the second discharge constant current circuit 16, and the second discharge constant current circuit 16 Transistor Q7 operates to draw a constant current Id. As a result, the electric charge accumulated in the capacitor C2 is discharged with the constant current Id (see waveforms in the periods T1 and T3 in FIGS.

  As shown in FIG. 7, the first pulse generation circuit 17 includes a well-known RS latch circuit using two NAND circuits. The input terminal of the second NAND circuit N2 of the first pulse generation circuit 17 is an input terminal for an S (set) signal, and the input terminal of the first NAND circuit N1 is an input terminal for an R (reset) signal. The output terminal of the first NAND circuit N1 is an output terminal for the / Q signal, and the output terminal of the second NAND circuit N2 is an output terminal for the Q signal.

  The voltage across the capacitor C1 is input as the first reset signal res1 to the input terminal of the first NAND circuit N1 of the first pulse generation circuit 17, and the first output from the clock generation circuit 11 is input to the input terminal of the second NAND circuit N2. A set signal set1 is input. The pulse signal output from the output terminal of the first NAND circuit N1 is input to the pulse synthesis circuit 19 as the first pulse signal rsout1 for generating the PWM modulation signal PWMout, and is output from the output terminal of the second NAND circuit N2. The pulse signal is input to the base of the switch SW3 as the third control signal φ3.

  In the RS latch circuit shown in FIG. 7, (S, R) = (high, low) and (Q, / Q) = (high, low) logic, and (S, R) = (low, high). Thus, the logic of (Q, / Q) = (low, high) is obtained. As shown in FIGS. 4D and 4H, at the timing when the first control signal φ1 rises, the first set signal set1 becomes a low level momentarily, and the voltage across the capacitor C1 (the first reset signal res1) is high. Therefore, the first pulse signal rsout1 becomes a low level, and the third control signal φ3 becomes a high level (see FIGS. 4F and 4J). When the third control signal φ3 becomes high level, discharging of the capacitor C1 is started, but the first pulse signal rsout1 is held at low level while the voltage across the capacitor C1 is higher than the threshold voltage Vth of the first NAND circuit N1. When the threshold voltage Vth is reached, the first set signal set1 becomes high level, and the first reset signal res1 becomes low level. Therefore, at this timing, the first pulse signal rsout1 becomes high level, and the third control signal φ3 is It becomes a low level (see FIGS. 4F and 4J).

  Similarly to the first pulse generation circuit 17, the second pulse generation circuit 18 is configured by a well-known RS latch circuit using two NAND circuits. As shown in FIG. 7, the voltage across the capacitor C2 is input as the second reset signal res2 to the input terminal of the third NAND circuit N3 of the second pulse generation circuit 18, and the clock generation circuit is input to the input terminal of the fourth NAND circuit N4. The second set signal set2 output from 11 is input. The pulse signal output from the output terminal of the third NAND circuit N3 is input to the pulse synthesis circuit 19 as the second pulse signal rsout2 for generating the PWM modulation signal PWMout, and is output from the output terminal of the fourth NAND circuit N4. The pulse signal is input to the base of the switch SW3 as the fourth control signal φ4.

  As shown in FIGS. 4E and 4I, at the timing when the second control signal φ2 rises, the second set signal set2 instantaneously becomes a low level, and the voltage across the capacitor C2 (second reset signal res2) is high. Therefore, the second pulse signal rsout2 becomes low level, and the fourth control signal φ4 becomes high level (see FIGS. 4G and 4K). When the fourth control signal φ4 becomes high level, discharging of the capacitor C2 is started, but the second pulse signal rsout2 is held at low level while the voltage across the capacitor C2 is higher than the threshold voltage Vth of the third NAND circuit N3. When the threshold voltage Vth is reached, the second set signal set2 becomes high level, and the second reset signal res2 becomes low level, so that the second pulse signal rsout2 becomes high level at that timing, and the fourth control signal φ4 is It becomes a low level (see FIGS. 4G and 4K).

  As shown in FIG. 7, the pulse synthesizing circuit 19 includes a fifth NAND circuit N5. The pulse synthesizing circuit 19 outputs a first pulse signal rsout1 output from the first pulse generating circuit 17 and a second pulse output from the second pulse generating circuit 18. A pulse width modulation signal PWMout is generated by calculating a negative logical product with the pulse signal rsout2 (see FIG. 4L).

  Next, the pulse width modulation operation in the pulse width modulation circuit 10 will be described with reference to FIG. Since the same pulse width modulation operation is performed by the capacitor C1 and the capacitor C2, the pulse width modulation operation in the capacitor C1 will be described here.

  When the first control signal φ1 becomes low level, the switch SW1 is turned on, and the first charging current generation circuit 13 performs the generation operation of the charging current (Ic + Δi). Since the third control signal φ3 is at the low level during the period in which the first control signal φ1 is at the low level, the switch SW3 is in the OFF state (see FIGS. 4B and 4H), and the first constant current for discharge Circuit 15 is not operating. Accordingly, only the charging current (Ic + Δi) generated by the first charging current generation circuit 13 flows into the capacitor C1, and the capacitor C1 is thereby charged. This charging operation is performed during a period during which the first control signal φ1 is low (period T1 in FIG. 8).

  The voltage across the capacitor C1 during the period T1 (the voltage at point A in FIG. 3) rises from the charging start voltage Va with a slope proportional to the magnitude of the charging current (Ic + G · eS). The charging current (Ic + G · eS) depends on the positive and negative directions and the amplitude of the audio signal eS. The larger the amplitude | eS | at eS> 0, the higher the charging voltage at the end of the period T1, and eS < The larger the amplitude | eS | at 0, the lower the charging voltage at the end of the period T1. In FIG. 8, the period T1 is very short with respect to the amplitude fluctuation of the audio signal eS, and in the period T1, the amplitude fluctuation of the audio signal eS is almost constant and the charging voltage of the capacitor C1 is increased almost linearly. ing.

  The voltage waveform S0 of FIG. 8 shows a waveform when eS = 0 (when the audio signal eS is no signal), the voltage waveform S1 shows a waveform when eS> 0, and the voltage waveform S2 shows eS < The waveform at 0 is shown.

  When the first control signal φ1 becomes high level and the third control signal φ3 becomes high level, the switch SW1 is turned off and the switch SW3 is turned on at the same time, and the first charging current generation circuit 13 stops operating, The discharging constant current circuit 15 performs an operation of drawing the constant current Id. Therefore, the electric charge accumulated in the capacitor C1 is drawn into the first discharging constant current circuit 15 by the constant current Id, and thereby the electric charge accumulated in the capacitor C1 is discharged. This discharging operation is performed until the voltage of the capacitor C1 drops to the charging start voltage Va.

  When the voltage of the capacitor C1 drops to the threshold voltage Vth, the third control signal φ3 is inverted to a low level and the switch SW3 is turned off, so that the pulling operation by the constant current Id of the first discharging constant current circuit 15 is stopped. . However, even if the third control signal φ3 is inverted to a low level, there is a slight time lag until the switch SW3 is actually turned off. During this time lag, the voltage of the capacitor C1 drops to Va. During the period from when the voltage of the capacitor C1 drops to Va and until the next first control signal φ1 becomes low level, neither charging current nor discharging current flows through the capacitor C1. Therefore, the voltage of the capacitor C1 is held at Va until the first control signal φ1 becomes low level (see times t1k, t0k, and t2k in FIG. 8).

  The discharge time Th is proportional to the charging voltage Vj. That is, the higher the charging voltage Vj, the longer the discharge time Th. In FIG. 8, time t1 indicates the discharge time when the audio signal eS> 0, time t0 indicates the discharge time when the audio signal eS = 0, and time t2 indicates the time when the audio signal eS <0. It shows the discharge time, and has a relationship of t2 <t0 <t1.

  Since the height of the charging voltage Vj is proportional to the amplitude | eS | of the audio signal eS, the discharge time Th is also proportional to the amplitude | eS | of the audio signal eS. That is, the discharge time Th of the capacitor C1 indicates a time modulated by the amplitude | eS | of the audio signal eS. The above pulse width modulation operation is the same for the capacitor C2.

  In the pulse width modulation circuit 10 of the present embodiment, as shown in FIG. 4, a pulse obtained by performing pulse width modulation of the audio signal eS by the capacitor C2 during the high level period of the period T of the reference clock signal MCLK is generated, and the subsequent low level is generated. Since the capacitor C1 generates a pulse obtained by performing pulse width modulation on the audio signal eS during the period, the pulse synthesizing circuit 19 combines the two pulses to generate the pulse width modulation signal PWMout having the period T of the reference clock signal MCLK. .

  Next, the operation of the pulse width modulation circuit 10 will be described with reference to FIG. FIG. 4 is a time chart when the audio signal eS fluctuates within a normal range (−Es to + Es). The first period T1, the second period T2, the third period T3, and the fourth period T4 for the two periods of the high level and the low level from the period when the reference clock signal MCLK first becomes the high level, respectively. To.

  In the first period T1, since the first control signal φ1 from the clock generation circuit 11 is at the low level (the second control signal φ2 is at the high level) (see FIG. 4B), the switch SW1 is in the on state (the switch SW2 Is turned off), and the first charging current generation circuit 13 is connected to the capacitor C1. Therefore, in the first period T1, the charging current (Ic + Δi) flows from the first charging current generation circuit 13 to the capacitor C1, thereby charging the capacitor C1 (see FIG. 4F). This charging operation is performed until the first period T1 ends.

  When the first period T1 ends and the first control signal φ1 is inverted from the low level to the high level, the switch SW1 is turned off. The OFF state of the switch SW1 continues during the second period T2. The clock generation circuit 11 detects the rising edge at the time of inversion of the first control signal φ1, and outputs the first set signal set1 that instantaneously changes to the low level to the first pulse generation circuit 17 (in FIG. 4D). See first low level change).

  In the first pulse generation circuit 17, when the first set signal set1 (low level) is input at the start of the second period T2, the output of the second NAND circuit N2 is inverted from the low level to the high level (FIG. 4 (h) )reference). Since the output of the second NAND circuit N2 is input to the switch SW3 as the third control signal φ3, the switch SW3 is turned on, and the first constant current circuit 15 for discharging is connected to the capacitor C1, thereby the capacitor C1 It is discharged with a constant current Id (see FIG. 4 (f)).

  Further, in the first pulse generation circuit 17, when the first set signal set1 (low level) is input at the start of the second period T2, the output of the first NAND circuit N1 is inverted from the high level to the low level (FIG. 4). (See (j)). The output of the first NAND circuit N1 is input to the pulse synthesis circuit 19 as the first pulse signal rsout1.

  When the low level output of the first NAND circuit N1 is input to the pulse synthesizing circuit 19, the second pulse signal rsout2 input from the second pulse generating circuit 18 to the fifth NAND circuit N5 of the pulse synthesizing circuit 19 is high level. The synthesis circuit 19 outputs a pulse (high level pulse) obtained by inverting the level of the first pulse signal rsout1 (see the second pulse in FIG. 4L).

  In the second period T2, since the capacitor C1 is discharged with the constant current Id, the voltage across the capacitor C1 decreases. In the first pulse generation circuit 17, the voltage across the capacitor C1 is input to the first NAND circuit N1, but when the voltage across the capacitor C1 drops to the threshold voltage Vth, the voltage at that time is set to the low level first reset signal res1. This is input to the first pulse generation circuit 17. When the first reset signal res1 is input to the first pulse generation circuit 17, the first pulse signal rsout1 is inverted from the low level to the high level (see FIG. 4 (j)).

  On the other hand, in the second period T2, since the second control signal φ2 from the clock generation circuit 11 is at a low level (the first control signal φ1 is at a high level) (see FIG. 4C), the switch SW2 is in an on state ( The switch SW1 is turned off), and the second charging current generation circuit 14 is connected to the capacitor C2. Therefore, in the second period T2, the charging current (Ic + Δi) flows from the second charging current generation circuit 14 to the capacitor C2, thereby charging the capacitor C2 (see FIG. 4G). This charging operation is performed until the second period T2 ends.

  When the second period T2 ends and the second control signal φ2 is inverted from the low level to the high level, the switch SW2 is turned off. The OFF state of the switch SW2 continues during the third period T3. The clock generation circuit 11 detects the rising edge at the time of inversion of the second control signal φ2, and outputs the second set signal set2 that instantaneously changes to the low level to the second pulse generation circuit 18 (see FIG. 4E). ).

  In the second pulse generation circuit 18, when the second set signal set2 (low level) is input at the start of the third period T3, the output of the fourth NAND circuit N4 is inverted from the low level to the high level (FIG. 4 (i )reference). Since the output of the fourth NAND circuit N4 is input to the switch SW4 as the fourth control signal φ4, the switch SW4 is turned on, and the second discharging constant current circuit 16 is connected to the capacitor C2, whereby the capacitor C2 The battery is discharged with a constant current Id (see FIG. 4G).

  In the second pulse generation circuit 18, when the second set signal set2 (low level) is input at the start of the third period T3, the output of the third NAND circuit N3 is inverted from the high level to the low level (FIG. 4). (See (k)). The output of the third NAND circuit N3 is input to the pulse synthesis circuit 19 as the second pulse signal rsout2.

  When the low level output of the third NAND circuit N3 is inputted to the pulse synthesis circuit 19, the first pulse signal rsout1 inputted from the first pulse generation circuit 17 to the fifth NAND circuit N5 of the pulse synthesis circuit 19 is high level, so that the pulse The synthesis circuit 19 outputs a pulse (high level pulse) obtained by inverting the level of the second pulse signal rsout2 (see the third pulse in FIG. 4L).

  Thereafter, after the third period, operations similar to those in the first period T1 and the second period T2 are repeated. Accordingly, the pulse synthesizing circuit 19 alternately outputs pulses obtained by inverting the levels of the first pulse signal rsout1 and the second pulse signal rout2 every half cycle of the reference clock signal MCLK.

  When the amplitude of the audio signal eS fluctuates in the normal range (a range of -Es to + Es), the capacitors C1 and C2 always rise to the charging end voltage Vc higher than the threshold voltage Vth during the charging period. Therefore, even after the transition to the discharge period, the voltages of the capacitors C1 and C2 normally become the charging start voltage Va, and the voltages of the capacitors C1 and C2 after the discharge stop are always held at the charging start voltage Va. The charging start voltage of the capacitors C1 and C2 is stabilized at Va (see (f) and (g) in FIG. 4).

  FIG. 9 shows a time chart when the amplitude of the audio signal eS fluctuates in an excessive range on the positive side (range of + Es or more). The generation process of the pulse width modulation signal PWMout when the amplitude of the audio signal eS fluctuates in an excessive range on the positive side (range of + Es or more) is basically that the amplitude of the audio signal eS is in the normal range (− Therefore, the detailed description is omitted and only the differences are described.

  When the amplitude of the audio signal eS fluctuates in the normal range (in the range of -Es to + Es), the charging current Ij changes according to the amplitude of the audio signal eS. Therefore, (f) and (g) in FIG. The voltage waveforms of the capacitors C1 and C2 shown in FIG. 4 change according to the amplitude of the audio signal eS. Specifically, the charging end voltage Vc at which the capacitors C1 and C2 rise during the charging period changes in the range of Vth (> 0) to Vcc according to the amplitude of the audio signal eS. For example, the voltage waveform of the capacitor C1 Changes within a range between the voltage waveform indicated by the alternate long and short dash line N1 and the waveform indicated by the dotted line N2. The same applies to the voltage waveform of the capacitor C2.

  On the other hand, when the amplitude of the audio signal eS fluctuates in an excessive range on the positive side (a range of + Es or more), the charging end voltage Vc of the capacitors C1 and C2 is changed between the first and second RS flip-flop circuits 17 and 18. Since it is clipped to the power supply voltage + Vcc, the waveforms at the time of discharging of the capacitors C1 and C2 are as shown by (f) and (g) in FIG. The voltage waveform shown is the same as the waveform during discharge.

  The case where the amplitude of the audio signal eS fluctuates in an excessive range on the positive side (range of + Es or more) is the same as the case where the amplitude of the audio signal eS fluctuates in a normal range (range of −Es to + Es). In addition, the capacitors C1 and C2 always rise to the charging end voltage Vc higher than the threshold voltage Vth during the charging period, and the voltage of the capacitors C1 and C2 normally becomes the charging start voltage Va even after the transition to the discharging period. Accordingly, since the voltage of the capacitors C1 and C2 after the discharge is stopped is always held at the charging start voltage Va, the charging start voltage of the capacitors C1 and C2 during the charging period is stabilized at Va ((f), (g )reference).

  FIG. 10 shows a time chart in the case where the amplitude of the audio signal eS fluctuates in an excessive range on the negative side (range of −Es or less). The generation process of the pulse width modulation signal PWMout when the amplitude of the audio signal eS fluctuates in an excessive range on the negative side (a range of −Es or less) is basically basically the same as that of the audio signal eS described above. (The range of -Es to + Es) is the same as the case of fluctuation, and detailed description is omitted, and only the difference will be described.

  When the amplitude of the audio signal eS fluctuates in an excessive range on the negative side (a range of −Es or less), the charging current is clipped to 0, so that the voltage of the capacitor C1 does not increase even during the charging period. In the subsequent discharge period, the first discharging constant current circuit 15 is connected to the capacitor C1, so that the capacitor C1 tends to be discharged with the constant current Id. However, if the voltage of the capacitor C1 is to be lowered below Va by the discharging operation, the voltage from the voltage source Vx of the charging start voltage maintaining circuit 20 is immediately supplied to the capacitor 1, so that the first constant current for discharging is supplied to the capacitor C1. Despite the circuit 15 being connected, the voltage of the capacitor C1 does not drop below Va. That is, when the amplitude of the audio signal eS fluctuates in an excessive range on the negative side (a range of −Es or less), the voltage of the capacitor C1 continues to maintain the charging start voltage Va. The same applies to the capacitor C2. (See (f) and (g) in FIG. 10).

  Accordingly, when the amplitude of the audio signal eS as in the circuit of FIG. 14 fluctuates in an excessive range on the negative side (a range of −Es or less), the voltage of the capacitor gradually decreases to a voltage lower than Va. As a result, when the amplitude of the audio signal eS returns to the normal range, the problem that it takes time to output a normal pulse width modulation signal is solved. That is, by maintaining the charging start voltage at Va, a normal pulse width modulation signal can be output immediately when the amplitude of the audio signal eS returns to the normal range.

  As described above, according to the present embodiment, even when the input signal becomes excessive on the negative side, a normal pulse width modulation signal can be output immediately when the normal state is restored. Furthermore, according to the present embodiment, since non-linear elements such as the diodes D51 and D52 are not connected in series with the signal path, the audio signal does not always perform a non-linear operation, and the signal quality (for example, sound quality) is deteriorated. Can be prevented. Note that the polarity of each transistor, power supply voltage, reference clock, control signal, pulse width modulation signal, and the like can be changed as appropriate for the convenience of design, and is not limited to the above configuration.

  Next, another preferred embodiment of the present invention will be described. The charging start voltage maintaining circuit 20 shown in FIGS. 6A and 6B has the following problems. The voltage of the capacitor C1 subtracts the voltage Vd51 across the diode D51 (in FIG. 6B, the voltage across the diode component between the base and emitter of the transistor Q51) from the voltage V1 at the connection point of the resistor R51, the resistor R52 and the capacitor C51. If the voltage is lower than the voltage (ie, voltage Va), the voltage is supplied from the voltage source Vx to the capacitor C1 (current flows). However, the diode (or the diode existing between the base and emitter of the transistor) has a predetermined voltage without any current flowing until the anode potential with respect to the cathode potential reaches a predetermined voltage (for example, 0.6 V). The current does not flow for the first time, but some current flows from the anode toward the cathode until the anode potential with respect to the cathode potential reaches a predetermined voltage (for example, 0.6 V).

  Therefore, when the voltage of the capacitor C1 (same for C2) is supposed to be lower than the voltage Va, the current should flow from the voltage source Vx to the capacitor C1 for the first time. Even when it is large, a current flows from the voltage source Vx to the capacitor C1, and the capacitor C1 is charged. In other words, the capacitor C1 is charged by the voltage source Vx even when the input signal is not excessively negative but in a normal state, and as a result, the output PWM signal is obtained by accurately pulse-width modulating the audio signal. Therefore, the output signal is distorted. This is because a current irrelevant to the audio signal is supplied to the capacitor C1, so that the charging end voltage of the capacitor C1 increases more than usual. The voltage until the voltage of the capacitor C1 reaches the threshold voltage Vth during discharging. This is because the time is longer than usual.

  In order to solve this problem, the charge start voltage maintaining circuit of the present embodiment is configured such that when the input signal is excessive on the negative side (that is, when the negative side amplitude exceeds a predetermined level), the capacitor C1, A voltage source is provided so that a voltage is supplied to C2 and no voltage is supplied from the voltage source Vx to the capacitors C1 and C2 when the input signal is not excessively negative (ie, the amplitude of the negative side does not exceed a predetermined level). The voltage value of Vx is switched as appropriate. Specifically, when the first pulse signal rsout1 is excessively large on the negative side, the high level period is very long and the low level period is very short, and the input signal is not excessively negative. Since the high level period is not so long and the low level period is not so short, the first pulse signal rsout1 is used. Actually, the first pulse signal rsout1 is supplied to the capacitor C51 of the voltage source Vx, and when the first pulse signal rsout1 is at a high level, the capacitor C51 is charged by the voltage of the first pulse signal rsout1, and the first pulse signal rsout1 Is low level, the capacitor C51 is discharged, and the charging voltage of the capacitor C51 charged by the voltage of the first pulse signal rsout1 is added to the voltage value of the voltage source Vx. That is, the voltage of the voltage source Vx is switched (increase / decrease) by charging / discharging of the capacitor C51 by the first pulse signal rsout1.

  11A and 11B show the charge start voltage maintaining circuit 20 'of this example. Compared with the charging start voltage maintaining circuit 20 of FIG. 6A, the charging start voltage maintaining circuit 20 'of FIG. 11A further includes a resistor R53 and a diode D53. Compared with the charging start voltage maintaining circuit 20 of FIG. 6B, the charging start voltage maintaining circuit 20 'of FIG. 11B further includes a resistor R53 and a diode D53. Hereinafter, FIG. 11A will be described as an example, but the same applies to FIG. 11B.

  The resistor R53 and the diode D53 constitute a part of the voltage source Vx. One end of the resistor R53 is connected to the connection point of the resistors R51 and R52 and the capacitor C51, and the other end is connected to the cathode of the diode D53. The anode of the diode D53 is connected to the output of the first NAND circuit N1 of FIG. 7, and the first pulse signal rsout1 is supplied.

  The voltage V1 at the connection point of the resistor R51, the resistor R52, and the capacitor C51 is set to a voltage that does not supply a voltage to the capacitor C1 when the voltage of the first pulse signal rsout1 is not added to the voltage V1, that is, The voltage value is smaller than the voltage Va. Note that the voltage V1 at the connection point of the resistor R51, the resistor R52, and the capacitor C51 may be set to −Vcc (for example, 0 V) when the voltage of the first pulse signal rsout1 is not added to the voltage V1, and in that case The resistor R51 is deleted (opened).

  The operation of this example will be described below. FIG. 13 is a waveform diagram showing the voltage change of the capacitor C51. As shown in FIG. 13, when the first pulse signal rsout1 is at a high level, the voltage of the first pulse signal rsout1 is supplied to the capacitor C51 via the diode D53 and the resistor R53, and charges the capacitor C51. When the first pulse signal rsout1 is at a low level, the voltage of the first pulse signal rsout1 is interrupted by the diode D53 and is not supplied to the capacitor C51. Accordingly, when the first pulse signal rsout1 is at the low level, the voltage of the capacitor C51 charged by the voltage of the first pulse signal rsout1 is discharged to the power source −Vcc through the resistor R52.

  For example, when the input signal is not excessively negative (and close to it) as shown by the solid line in FIG. 4 (f), the first pulse signal rsout1 is at the high level as shown in FIG. 4 (j). The period is not so long and there are enough low level periods. Therefore, when the first pulse signal rsout1 is at a high level, the capacitor C51 is charged by the voltage of the first pulse signal rsout1, and the voltage V1 of the power source Vx to which the charging voltage is added supplies the voltages to the capacitors C1 and C2. Until the first pulse signal rsout1 is inverted to a low level, the voltage of the capacitor C51 is discharged. As a result, even if the voltage of the first pulse signal rsout1 is added to the voltage V1 at the connection point of the resistor R51, the resistor R52, and the capacitor C51, the voltage of the voltage source Vx does not supply the voltage to the capacitors C1 and C2. . Accordingly, since no voltage is supplied from the voltage source Vx to the capacitors C1 and C2, no extra current other than the input signal flows into the capacitors C1 and C2, and distortion of the output signal is prevented.

  On the other hand, when the input signal is excessively negative (and close to it) as shown in FIG. 12 (e), the first pulse signal rsout1 has a high level period as shown in FIG. 12 (g). It becomes very long and the low level period becomes very short (or the low level period disappears). Accordingly, when the first pulse signal rsout1 is at a high level, the capacitor C51 is charged for a long period by the voltage of the first pulse signal rsout1, and the voltage V1 of the power source Vx to which the charging voltage is added supplies the voltage to the capacitors C1 and C2. To reach the voltage. Therefore, when the input signal is excessively negative (and close to it), a voltage is supplied from the voltage source Vx to the capacitor C1, and the voltage source is reduced when the voltage of the capacitor C1 is lowered from the voltage Va. The capacitor C1 can be charged by the voltage from Vx, and the voltage of the capacitor C1 can be prevented from dropping below Va, and can be maintained at the voltage Va.

  Note that the modulation factor (high level period / (high level period + low level period)) of the first pulse signal rsout1 is determined to be m (for example, 0.9), and the voltage source when the modulation factor is equal to or greater than m. The values of the resistors R52, R53, and the capacitor C51 may be set so that the voltage is supplied from the Vx to the capacitors C1 and C2 and the voltage is not supplied from the voltage source Vx to the capacitors C1 and C2 when the modulation degree is less than m. .

  The present invention can be suitably employed for an audio amplifier, for example.

DESCRIPTION OF SYMBOLS 1 Pulse width modulation circuit 2 Switching circuit 3 Low pass filter circuit 4 1st power supply 5 2nd power supply 11 Clock generation circuit 12 Differential amplifier circuit 13 1st charging current generation circuit 14 2nd charging current generation circuit 15 1st constant current for discharge Circuit 16 Second constant current circuit for discharge 17 First pulse generation circuit 18 Second pulse generation circuit 19 Pulse synthesis circuit 20 Charge start voltage maintenance circuit AU Audio generation source C1 Capacitor C2 Capacitor eS Audio signal SW1 Switch SW2 Switch SW3 Switch SW4 Switch T1 1st period T2 2nd period T3 3rd period T4 3rd period φ1 1st control signal φ2 2nd control signal φ3 3rd control signal φ4 4th control signal

Claims (12)

A charging control signal for generating a first control signal for executing a charging operation during a period of one level of the reference clock and a second control signal for executing a charging operation during a period of the other level of the reference clock A generator,
A third control signal for causing the charge accumulated in the charging operation to be discharged in a period of the other level following the period of the one level in which the charging operation is performed by the first control signal; A discharge control signal for generating a fourth control signal for executing a discharging operation of the charge accumulated in the charging operation in a period of one level following a period of the other level in which the charging operation is performed by the control signal of 2. A generator,
A charging operation for charging the first capacitor with a charging current generated based on the level of the input signal in accordance with the first control signal, and a charge accumulated in the first capacitor in accordance with the third control signal is constant. The discharge operation is performed with a discharge current of a first current, and the discharge time until the first capacitor changes from the level at the start of discharge to the reference level in each period during which the discharge operation is performed is a pulse width. A first pulse signal generation unit that generates one pulse signal;
A charging operation for charging the second capacitor with the charging current according to the second control signal, and a discharging operation for discharging the accumulated charge of the second capacitor with the discharge current according to the fourth control signal. And generating a second pulse signal having a pulse width as a discharge time until the second capacitor changes from the level at the start of discharge to the reference level in each period during which the discharge operation is performed. A pulse signal generator of
The first pulse signal generated by the first pulse signal generation unit and the second pulse signal generated by the second pulse signal generation unit are synthesized, and the pulse width of each pulse is equal to the input signal. A pulse signal synthesizer that outputs a pulse width modulation signal that changes according to the level;
When the negative amplitude of the input signal exceeds a predetermined level, the voltages of the first capacitor and the second capacitor are maintained at a predetermined voltage by supplying a voltage to the first capacitor and the second capacitor. A pulse width modulation circuit comprising a voltage maintaining unit. The voltage maintaining unit is
A voltage source for supplying the voltage;
A first diode having a cathode connected to the first capacitor and an anode connected to the voltage source;
The pulse width modulation circuit according to claim 1, further comprising: a second diode having a cathode connected to the second capacitor and an anode connected to the voltage source. The voltage source is
A first resistor having one end connected to the first power source and the other end connected to the anode of the first diode and the anode of the second diode;
A second resistor having one end connected to the second power source and the other end connected to the anode of the first diode and the anode of the second diode;
The pulse width modulation circuit according to claim 2, further comprising: a third capacitor having one end connected to a connection point between the first resistor and the second resistor and the other end connected to the second power source. A voltage obtained by subtracting the voltage across the first diode from the voltage of the voltage source is set to the predetermined voltage,
4. The pulse width modulation circuit according to claim 2, wherein a voltage obtained by subtracting a voltage across the second diode from a voltage of the voltage source is set to the predetermined voltage. 5. The voltage maintaining unit is
A voltage source for supplying the voltage;
A first transistor having a first terminal connected to the first capacitor and a second terminal and a control terminal connected to the voltage source;
2. The pulse width modulation circuit according to claim 1, further comprising: a second transistor having a first terminal connected to the second capacitor and a second terminal and a control terminal connected to the voltage source. The voltage source is
A first resistor having one end connected to a first power supply and the other end connected to a control terminal of the first transistor and a control terminal of the second transistor;
A second resistor having one end connected to the second power supply and the other end connected to the control terminal of the first transistor and the control terminal of the second transistor;
The pulse width modulation circuit according to claim 5, further comprising: a third capacitor having one end connected to a connection point between the first resistor and the second resistor and the other end connected to the second power source. A voltage obtained by subtracting the voltage between the control terminal and the first terminal of the first transistor from the voltage of the voltage source is set to the predetermined voltage,
The pulse width modulation circuit according to claim 5 or 6, wherein a voltage obtained by subtracting a voltage between the control terminal and the first terminal of the second transistor from the voltage of the voltage source is set to the predetermined voltage.   When the negative amplitude of the input signal exceeds a predetermined level, the voltage maintaining unit supplies a voltage to the first capacitor and the second capacitor, and the negative amplitude of the input signal is a predetermined level. 6. The pulse width modulation circuit according to claim 2, wherein a voltage value of the voltage source is changed so that a voltage is not supplied to the first capacitor and the second capacitor when the voltage does not exceed.   The voltage source is supplied with the first pulse signal generated by the first pulse signal generation unit, and is charged by the voltage of the first pulse signal when the first pulse signal is at a high level. A third capacitor that discharges a voltage charged by the voltage of the first pulse signal when the first pulse signal is at a low level, and the voltage value of the voltage source includes the first pulse signal. The pulse width modulation circuit according to claim 8, wherein the voltage value of the voltage source is changed by adding the charging voltage of the third capacitor charged by the voltage of 10. The voltage source is
A first resistor having one end connected to a predetermined potential and the other end connected to an anode of the first diode and an anode of the second diode;
A third capacitor having one end connected to the other end of the first resistor and the other end connected to the predetermined potential;
A second resistor having one end connected to one end of the first capacitor;
3. The pulse width modulation circuit according to claim 2, wherein a cathode is connected to the other end of the second resistor, and an anode includes a third diode to which the first pulse signal is supplied. The voltage source is
A first resistor having one end connected to a predetermined potential and the other end connected to a control terminal of the first transistor and a control terminal of the second transistor;
A third capacitor having one end connected to the other end of the first resistor and the other end connected to the predetermined potential;
A second resistor having one end connected to one end of the first capacitor;
The pulse width modulation circuit according to claim 5, further comprising a third diode to which a cathode is connected to the other end of the second resistor and an anode is supplied with the first pulse signal.   A switching amplifier comprising the pulse width modulation circuit according to claim 1.

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