JP5187640B2 - Pulse width modulation circuit and switching amplifier - Google Patents

Description

  The present invention relates to a pulse width modulation circuit, and more particularly to a pulse width modulation circuit including a multivibrator.

  FIG. 4 is a circuit diagram showing a conventional pulse width modulation circuit 60. The pulse width modulation circuit 60 outputs pulses having two levels of high level or low level from the inverters INV1 and INV2 by charging and discharging the capacitors C1 and C2 with the collector currents of the transistors Q2 and Q1. Then, the audio signal in which is an input signal is input to the transistor Q1, the distribution ratio of the collector currents of the transistors Q1 and Q2 from the constant current is controlled, and the charging time of the capacitors C1 and C2 is controlled, so that the output pulse of Modulate the pulse width. As a result, the pulse width modulation circuit 60 outputs PWM (pulse width modulation) signals from the inverters INV1 and INV2, respectively (for example, Patent Documents 1 to 3).

  The pulse width modulation circuit 60 oscillates when one of the inputs of the inverters INV1 and INV2 is at a high level and the other is at a low level (when one outputs a high level, the other outputs a low level). (Referring to repeating the operation), and the PWM signal can be output. However, if both the capacitors C1 and C2 are charged and the inputs of the inverters INV1 and INV2 both become high level, there is a problem that the oscillation operation stops and the PWM signal cannot be output.

  Here, the operation when the pulse width modulation circuit 60 shifts from the power-on state to the power-off state will be described. When the power supply voltage VA is turned off, no current flows from the constant current circuit 62 to the capacitors C1 and C2 via the transistors Q1 and Q2. On the other hand, although the power supply voltage VB for the inverters INV1 and INV2 also gradually decreases, the leakage current from the power supply voltage VB to the capacitor C1 through the diode D1 until the power supply voltage VB becomes 0V completely. (Reverse current) flows and charges the capacitor C1. Further, a leakage current flows from the power supply voltage VB to the capacitor C2 via the diode D2, and charges the capacitor C2.

  When the temperature of the diodes D1 and D2 is low, the leakage current flowing through the capacitors C1 and C2 via the diodes D1 and D2 is as small as several nA (for example, about 3 nA), and the power supply VB is 0V Even if the capacitors C1 and C2 are charged by the leakage current, the inputs of the inverters INV1 and INV2 do not become high level, and the outputs do not become low level. Therefore, when shifting to the power-on state, the inputs of the inverters INV1 and INV2 are in a state where one is at a high level and the other is at a low level, and the pulse width modulation circuit 60 can normally start an oscillation operation. .

  On the other hand, when the temperature of the diodes D1 and D2 rises to about 100 degrees, for example, the leakage current flowing through the capacitors C1 and C2 via the diodes D1 and D2 rises to about 600 nA, which is 200 times. Therefore, the capacitors C1 and C2 are considerably charged by the leakage current until the power supply VB becomes 0V, so that the inverters INV1 and IN2 continue to oscillate and the power supply VB becomes 0V (that is, the inverter INV1 In a short period of time just before INV2 stops operating), the capacitors C1 and C2 are charged with such charges that the inputs of the inverters INV1 and INV2 are both high, and the outputs of the inverters INV1 and INV2 are both low. A period will occur. When a sufficient time elapses after the power is turned off and the power is turned on, the charging voltages of the capacitors C1 and C2 are discharged, or the inverters INV1 and INV2 stop operating. However, since both of them do not output a low level, the pulse width modulation circuit 60 can normally start an oscillation operation. However, the power supply VB is not yet 0V, the inverters INV1 and INV2 continue to operate, both the inputs are high level, and the outputs are both low level. When shifting to, the pulse width modulation circuit 60 cannot start the oscillation operation.

JP 2007-28455 A JP 2006-352269 A Japanese Patent No. 3591519

  The present invention has been made to solve the above-described conventional problems. The object of the present invention is to charge the storage means by a leakage current when shifting to a power-off state, so that both inputs of two output elements are at a high level. Then, the next object is to provide a pulse width modulation circuit that solves the problem that the oscillation operation cannot be started when the power supply is turned on.

  A pulse width modulation circuit according to a preferred embodiment of the present invention includes a first storage unit, a second storage unit, a first output element, and a second output element, and the first storage unit is charged by a first current. And, based on the input signal, pulse generation means for outputting a pulse from the first output element and the second output element by charging the second storage means with a second current, The distribution ratio between the first current and the second current from a constant current is controlled, the charging time of the first storage means by the first current, and the second storage by the second current By controlling the charging time of the means, the modulation means for controlling the pulse width of the pulse, and by shifting the leakage current to a predetermined location when shifting from the power-on state to the power-off state, the leakage current is reduced. Said And a blocking means for preventing the flow to the storage means and / or said second storage means.

  In a preferred embodiment, the pulse generation means has a first diode and a second diode, the leakage current flows to the first storage means via the first diode, and the second diode A first resistor that bypasses leakage current flowing from the first diode to the first storage means to the predetermined location, and / or A second resistor for bypassing leakage current flowing from the second diode to the second storage means to the predetermined location;

  In a preferred embodiment, the first resistor can flow the first current to the first storage means when the power is on, and the leakage current is reduced when the power is turned off. The resistance value is set so as not to flow to the first storage means, and the second resistor can flow the second current to the second storage means when the power is on; and The resistance value is set so that the leakage current does not flow to the second accumulating means when shifting to the power-off state.

  A pulse width modulation circuit according to a preferred embodiment of the present invention includes a first storage unit, a second storage unit, a first output element, and a second output element, and the first storage unit is charged by a first current. And, based on the input signal, pulse generation means for outputting a pulse from the first output element and the second output element by charging the second storage means with a second current, The distribution ratio between the first current and the second current from a constant current is controlled, the charging time of the first storage means by the first current, and the second storage by the second current Modulation means for controlling a pulse width of the pulse by controlling a charging time of the means, a power supply line for supplying a power supply voltage to the first output element and the second output element, and the first storage 1st die between means An anode is connected, a second diode is connected between the power supply line and the second storage means, a first resistor is connected between the first diode and a predetermined location, and / or A second resistor is connected between the second diode and a predetermined location.

  The blocking unit prevents the leakage current from flowing to the first storage unit and / or the second storage unit by bypassing the leakage current to a predetermined location when shifting from the power-on state to the power-off state. Therefore, the first storage means and / or the second storage means are charged by the leakage current, and both the inputs of the first output element and the second output element are prevented from going to a high level, and then the power is turned on. When shifting, the problem that the oscillation operation cannot be started can be solved.

1 is a schematic block diagram illustrating a switching amplifier according to a preferred embodiment of the present invention. 1 is a schematic circuit diagram illustrating a pulse width modulation circuit according to a preferred embodiment of the present invention. 3 is a time chart showing the operation of the pulse width modulation circuit of FIG. 2. It is a schematic circuit diagram which shows the conventional pulse width modulation circuit.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings. However, the present invention is not limited to these embodiments. First, the schematic configuration of a switching amplifier to which the pulse width modulation circuit 20 of the present invention is applied will be described with reference to FIG. The switching amplifier 10 includes a pulse width modulation circuit 20, a driver 11, a switching output circuit 12, and an LPF (Low Pass Filter) 13.

  The pulse width modulation circuit 20 performs pulse width modulation on the input signal to generate the first PWM signal OUT1 and the second PWM signal OUT2. The first PWM signal OUT1 and the second PWM signal OUT2 are usually low level signals when one is a high level signal. The driver 11 receives the first PWM signal OUT1 and the second PWM signal OUT2, and outputs drive signals DRV1 and DRV2 for driving a switch element described later based on the power supply voltage.

  The switching output circuit 12 is connected between a first power source (for example, a positive power source + VD) and a second power source (for example, a negative power source −VD), and responds to a drive signal with a positive power source + VD or a negative power source. Output power -VD. The switching output circuit 12 includes switch elements (for example, MOSFETs) 15 and 16.

  The LPF 13 is connected between the output end of the switching output circuit 12 and the output end of the switching amplifier 10, removes high frequency components, and outputs to a load such as a speaker. The LPF 13 has a coil 17 and a capacitor 18.

  FIG. 2 is a circuit diagram illustrating a schematic configuration of the pulse width modulation circuit 20. The pulse width modulation circuit 20 includes a pulse generation unit 21, a modulation unit 22, and a blocking unit 23. The pulse generating means 21 and the modulating means 22 constitute a PWM circuit using an astable multivibrator.

  The pulse generating means 21 charges the capacitors C1 and C2 with the currents I1 and I2, and outputs a pulse having two levels of high level or low level from the first output element and the second output element. . In this example, the first output element and the second output element are inverters INV1 and INV2. The inverters INV1 and INV2 output a low level signal when the input exceeds a predetermined threshold, and output a high level signal when the input falls below the predetermined threshold. The inverters INV1 and INV2 each output a pulse by executing an oscillation operation (which means that when one inverter outputs a high level, the other inverter repeats an operation that outputs a low level).

  The pulse generation means 21 includes inverters INV1 and INV2, capacitors C1 and C2, and diodes D1 and D2, and outputs a pulse having a width corresponding to the charging time of the capacitors C1 and C2. The inverters INV1 and INV2 are connected to a power supply VB substantially corresponding to the high level of the output pulse and a power supply (or ground potential, generically referred to as a predetermined location) VC substantially corresponding to the low level. The inverter INV1 has an output connected to one end of the capacitor C2, and an input connected to one end of the capacitor C1 and the collector of the transistor Q2. The inverter INV2 has an output connected to the other end of the capacitor C1, and an input connected to the other end of the capacitor C2 and the collector of the transistor Q1. The diode D1 is connected between the power supply voltage line VB and one end of the capacitor C1, and the diode D2 is connected between the power supply voltage line VB and the other end of the capacitor C2.

  The modulation means 22 changes the pulse width of the output pulses of the inverters INV1 and INV2 by controlling the distribution ratio between the currents I1 and I2 based on the input signal (for example, audio signal) in. The modulation means 22 includes a constant current circuit 25, transistors Q1 and Q2, and resistors R1 and R2. The constant current circuit 25 is connected to the power source VA and generates a constant current I. The current I1 is the collector current of the transistor Q1, the current I2 is the collector current of the transistor Q2, and the sum of the current I1 and the current I2 is equal to the constant current I generated by the constant current circuit 25. That is, the current I1 and the current I2 are distributed from the constant current I. By applying the input signal in to the base of the transistor Q1, the distribution ratio between the current I1 and the current I2 is controlled according to the input signal in. As a result, the charging time of the capacitors C1 and C2 is controlled, and the pulse widths of the output pulses of the inverters INV1 and INV2 can be changed.

  When the pulse width modulation circuit 20 shifts from the power-on state to the power-off state, the blocking unit 23 bypasses the leakage current to the power supply voltage line VC, which is a predetermined location, so that the leakage current is reduced to the capacitors C1 and / or C2. Stop flowing into. Specifically, the blocking unit 23 prevents a leakage current (reverse current) from flowing from the power supply voltage line VB to the capacitor C1 through the diode D1 and / or when the power supply is turned off. The leakage current (reverse current) is prevented from flowing from the voltage line VB to the capacitor C2 via the diode D2. This prevents the capacitors C1 and C2 from being charged by the leakage current when shifting to the power-off state, and prevents the power-off state when both the inputs of the inverters INV1 and INV2 are at a high level.

  The blocking means 23 has resistors R3 and R4. The resistor R3 is connected between the anode of the diode D1 and the power supply voltage line VC, and causes a leakage current from the diode D1 to flow (bypass or bypass) the power supply voltage line VC. The resistor R4 is connected between the anode of the diode D2 and the power supply voltage line VC, and causes a leakage current from the diode D2 to flow (bypass or bypass) the power supply voltage line VC. The resistance value of the resistor R3 is such that the current I2 can flow to the capacitor C1 when the pulse width modulation circuit 20 is in the power-on state, and the leakage current does not flow to the capacitor C1 when the power-off state is entered. It is set to such a value. Therefore, although not particularly limited, the resistance R3 is set to a large resistance value of about 1 megaΩ. Similarly, the resistance value of the resistor R4 is such that the current I1 can flow to the capacitor C2 when the pulse width modulation circuit 20 is in the power-on state, and the leakage current to the capacitor C2 when the power-off state is entered. It is set to a value that does not flow. Therefore, although not particularly limited, the resistance R4 is set to a large resistance value of about 1 megaΩ.

  With respect to the pulse width modulation circuit 20 having the above configuration, a basic operation for outputting a PWM signal will be described with reference to FIG. Each waveform in FIG. 3 corresponds to the waveform at each point in FIG.

  The current I2 flows to the power supply VB through the diode D1. On the other hand, the current I1 flows to the capacitor C2 and charges the capacitor C2. As the capacitor C2 is charged, the potential at the point A gradually increases (t1 to t2). At t2, when the input (point A) of the inverter INV2 becomes equal to or higher than the threshold value of the inverter INV2, the output (point D) of the inverter INV2 is inverted to a low level. When the output of the inverter INV2 becomes low level, the capacitor C1 is discharged, the input (point B) of the inverter INV1 connected to the output of the inverter INV2 via the capacitor C1 becomes low level, and the output of the inverter INV1 (C The point is reversed to high level. When the output of the inverter INV1 is inverted to a high level, the input (point A) of the inverter INV2 becomes a high level. Thereafter, the capacitor C1 is charged with the current I2, whereby the reverse operation is performed (t2 to t3). The time for the input of the inverter INV2 to reach the threshold value from the low level by charging the capacitor C2 is controlled by the magnitude of the current I1, and the time for the input of the inverter INV1 to reach the threshold value from the low level by charging the capacitor C1 Controlled by size. By repeating this operation, high-level or low-level pulses are alternately output from the inverters INV1 and INV2.

  Next, the operation when the pulse width modulation circuit 20 shifts from the power-on state to the power-off state will be described. The voltage is not supplied from the power supply voltage line VA, and the current I1 and the current I2 do not flow to the capacitors C1 and C2. On the other hand, the voltage from the power supply voltage line VB gradually decreases, but before the power supply voltage VB becomes 0 V, leakage current tends to flow from the power supply voltage line VB to the capacitor C1 via the diode D1. An attempt is made to flow from the power supply voltage line VB to the capacitor C2 via the diode D2. However, most of the leakage current flowing through the diode D1 is prevented from flowing to the capacitor C1 by being bypassed to the power supply voltage line VC via the resistor R3. Most of the leakage current flowing through the diode D2 is prevented from flowing to the capacitor C2 by being bypassed to the power supply voltage line VC via the resistor R4.

  As a result, when the pulse width modulation circuit 20 is turned off, there is no state in which the capacitors C1 and C2 are considerably charged due to the leakage current, and “the inverters INV1 and IN2 continue to oscillate and the power supply VB Charges such that the inputs of the inverters INV1 and INV2 both become high level are charged in the capacitors C1 and C2 in a short time immediately before reaching 0V (that is, the inverters INV1 and INV2 stop operating), and the inverters INV1 and INV2 There is no period during which both outputs are low level. Therefore, even when the power supply VB is not yet 0 V and the inverters INV1 and INV2 are still operating, the input of the inverters INV1 and INV2 is not changed even when the power is turned on again. Both are prevented from becoming high level, and the problem that the pulse width modulation circuit 20 does not start the oscillation operation can be solved.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment. For example, the first and second output elements may be switching elements such as transistors and MOSFETs. Furthermore, the present invention is also applied to a configuration in which oscillation stops when both the inputs of the first output element and the second output element are at a low level. That is, the present invention can also be applied when the high level and the low level of the present embodiment are interchanged. Further, only one of the resistor R3 and the resistor R4 may be provided. Further, the leakage current may be bypassed to the ground potential or the like.

  The present invention can be particularly suitably employed as a pulse width modulation circuit used in, for example, an audio switching amplifier.

20 Pulse width modulation circuit 21 Pulse generation means 22 Modulation means 23 Blocking means

Claims (3)

A first accumulator, a second accumulator, a first output element and a second output element , a first diode and a second diode , wherein the first accumulator is charged by a first current; and Pulse generating means for outputting a pulse from the first output element and the second output element by charging the second storage means with a current of 2;
Based on the input signal, the distribution ratio between the first current and the second current from a constant current is controlled, the charging time of the first storage means by the first current, and the second current Modulation means for controlling the pulse width of the pulse by controlling the charging time of the second storage means by current;
When transitioning from a power-on state to a power-off state, a leakage current flows to the first storage means via the first diode and / or flows to the second storage means via the second diode. A blocking means for preventing the leakage current from flowing to the first storage means and / or the second storage means by bypassing the leakage current to a predetermined location ;
The blocking means flows from the first diode to the first storage means to bypass the leakage current to the predetermined location and / or from the second diode to the second storage means. that having a second resistor to bypass the leakage current to the predetermined portion, a pulse width modulation circuit. The first resistor can pass the first current to the first storage means when the power is on, and the leakage current flows to the first storage means when the power is turned off. Is set to a resistance value that does not flow,
The second resistor can pass the second current to the second storage means when the power is on, and the leakage current flows to the second storage means when the power is turned off. The pulse width modulation circuit according to claim 1 , wherein the resistance value is set so as not to flow. Comprising a pulse width modulation circuit according to claim 1 or 2, switching amplifier.

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