TWI407688B - Pwm modulator for a class-d amplifier and class-d amplifier adaptive to analog and digital input by using the same - Google Patents
Pwm modulator for a class-d amplifier and class-d amplifier adaptive to analog and digital input by using the same Download PDFInfo
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- TWI407688B TWI407688B TW99116849A TW99116849A TWI407688B TW I407688 B TWI407688 B TW I407688B TW 99116849 A TW99116849 A TW 99116849A TW 99116849 A TW99116849 A TW 99116849A TW I407688 B TWI407688 B TW I407688B
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Abstract
Description
本發明係有關一種D類放大器,特別是關於一種能直接被類比及數位輸入信號驅動的D類放大器。This invention relates to a class D amplifier, and more particularly to a class D amplifier that can be directly driven by analog and digital input signals.
圖1係習知的類比差動輸入D類放大器,類比輸入信號32從一對差動輸入端10及12進入後,經輸入驅動電路13產生信號Cbr1及Cbr2,受脈寬調變器18調變產生脈寬調變(Pulse Width Modulation;PWM)信號SpwmP及SpwmN給功率級20及22,進而產生差動輸出信號VoP及VoN驅動負載24。為獲得更穩定的輸出,該D類放大器更包括回授網路14及16分別偵測信號VoP及VoN產生回授信號VfbP及VfbN給PWM調變器18。在PWM調變器18中,電阻R1、電容C1及運算放大器26組成積分器對信號Cbr1積分產生信號VinP,電阻R2、電容C2及運算放大器28組成積分器對信號Cbr2積分產生信號VinN,PWM產生器30根據信號VinP及VinN以及載波信號產生信號SpwmP及SpwmN。回授網路14及16、功率級20及22以及PWM產生器30都是成熟的技術,其電路及操作可在許多文獻中找到,例如美國專利號7,183,840及7,262,658。由於沒有路徑供運算放大器26及28的負輸入端洩放電荷,因此,為了避免運算放大器26及28的負輸入端因為不斷累積電荷造成其直流電壓準位持續上升,運算放大器26及28的正輸入端接收共模電壓Vcm以箝制其負輸入端的直流電壓準位。為了避免類比輸入信號32的直流偏壓與共模電壓Vcm不同造成PWM調變器18無法工作,輸入驅動電路13包括電容Cin1及Cin2濾除類比輸入信號32的直流偏壓。然而,直流限制電容Cin1及Cin2會阻擋數位信號,故此D類放大器無法被數位輸入信號驅動。1 is a conventional analog input differential class D amplifier. After the analog input signal 32 enters from a pair of differential input terminals 10 and 12, signals Cbr1 and Cbr2 are generated via the input drive circuit 13, and are modulated by the pulse width modulator 18. Pulse Width Modulation (PWM) signals SpwmP and SpwmN are generated for power stages 20 and 22, which in turn generate differential output signals VoP and VoN to drive load 24. In order to obtain a more stable output, the class D amplifier further includes feedback networks 14 and 16 respectively detecting signals VoP and VoN to generate feedback signals VfbP and VfbN to the PWM modulator 18. In the PWM modulator 18, the resistor R1, the capacitor C1 and the operational amplifier 26 form an integrator to integrate the signal Cbr1 to generate a signal VinP, the resistor R2, the capacitor C2 and the operational amplifier 28 form an integrator to integrate the signal Cbr2 to generate a signal VinN, PWM generation The device 30 generates signals SpwmP and SpwmN based on the signals VinP and VinN and the carrier signal. The feedback networks 14 and 16, the power stages 20 and 22, and the PWM generator 30 are all well-established techniques, and their circuits and operations can be found in many documents, such as U.S. Patent Nos. 7,183,840 and 7,262,658. Since there is no path for the negative input terminals of operational amplifiers 26 and 28 to bleed charge, in order to prevent the negative input terminals of operational amplifiers 26 and 28 from continuously accumulating charges, their DC voltage levels continue to rise, and operational amplifiers 26 and 28 are positive. The input receives the common mode voltage Vcm to clamp the DC voltage level at its negative input. In order to prevent the PWM modulator 18 from operating due to the difference between the DC bias of the analog input signal 32 and the common mode voltage Vcm, the input drive circuit 13 includes capacitors Cin1 and Cin2 that filter the DC bias of the analog input signal 32. However, the DC limiting capacitors Cin1 and Cin2 block the digital signal, so the Class D amplifier cannot be driven by the digital input signal.
圖2係習知的數位差動輸入D類放大器,除了輸入驅動電路13以外,其餘電路與圖1相同。由於數位信號的高低準位不一定相同,因此,輸入驅動電路13包括緩衝器36及38將數位輸入信號34轉換為高、低準位分別為VDD及0的信號Cbr1及Cbr2。因為緩衝器36及38的存在,故此D類放大器無法被類比輸入信號驅動。2 is a conventional digital differential input class D amplifier, except for the input drive circuit 13, the other circuits are the same as in FIG. Since the high and low levels of the digital signals are not necessarily the same, the input driving circuit 13 includes buffers 36 and 38 for converting the digital input signal 34 into signals Cbr1 and Cbr2 having high and low levels of VDD and 0, respectively. Because of the presence of buffers 36 and 38, this class D amplifier cannot be driven by analog input signals.
雖然也有D類放大器可被類比及數位輸入信號驅動,但是其輸入驅動電路除了圖1的直流限制電容Cin1及Cin2以及圖2的緩衝器36及38以外,還需要偵測器偵測輸入信號為類比或數位信號,以切換該D類放大器到類比輸入模式或數位輸入模式。Although there are also Class D amplifiers that can be driven by analog and digital input signals, the input driver circuit requires the detector to detect the input signal in addition to the DC limiting capacitors Cin1 and Cin2 of Figure 1 and the buffers 36 and 38 of Figure 2. An analog or digital signal to switch the Class D amplifier to an analog input mode or a digital input mode.
本發明的目的之一,在於提出一種不需要輸入驅動電路,即能被類比或數位輸入信號驅動的D類放大器。One of the objects of the present invention is to provide a class D amplifier that can be driven by an analog or digital input signal without requiring an input driver circuit.
本發明的目的之一,在於提出一種PWM調節器,可讓D類放大器直接被類比或數位輸入信號驅動。One of the objects of the present invention is to provide a PWM regulator that allows a Class D amplifier to be directly driven by an analog or digital input signal.
根據本發明,一種用於D類放大器的PWM調變器在其運算放大器的輸入端連接放電元件以建立放電路徑,使得該D類放大器無需輸入驅動電路,即能被類比或數位輸入信號驅動。In accordance with the present invention, a PWM modulator for a Class D amplifier is coupled to a discharge element at the input of its operational amplifier to establish a discharge path such that the Class D amplifier can be driven by an analog or digital input signal without the need for an input drive circuit.
在單端負載應用時,PWM調變器的運算放大器的另一輸入端浮接。In single-ended load applications, the other input of the op amp of the PWM modulator is floating.
在差動輸入應用時,PWM調變器使用雙輸出的運算放大器,或兩個具有另一輸入端浮接的運算放大器。For differential input applications, the PWM modulator uses a dual output op amp or two op amps with another input floating.
圖3係應用本發明的差動輸入D類放大器,其係以圖1及圖2的電路為基礎設計的實施例,PWM調變器18不需要輸入驅動電路13作為輸入介面,因此該D類放大器能直接被類比輸入信號32或數位輸入信號34驅動。在PWM調變器18中,運算放大器26及28的正輸入端皆浮接,負輸入端分別增加放電元件40及42以建立放電路徑供洩放電荷。在此實施例中,放電元件40包含電阻R3連接在運算放大器26的負輸入端及接地端GND之間,放電元件42包含電阻R4連接在運算放大器28的負輸入端及接地端GND之間。在其他實施例中,放電元件40及42可用其他電子元件或電路建立放電路徑。由於移除直流限制電容Cin1及Cin2以及緩衝器36及38,所以此D類放大器適應類比輸入信號32及數位輸入信號34。當類比輸入信號32或數位輸入信號34施加到此D類放大器時,電阻R1及R3將正輸入端10的電壓分壓為信號Sd1,電阻R2及R4將負輸入端12的電壓分壓為信號Sd2。由於運算放大器26及28的正輸入端皆浮接,因此運算放大器26及28的負輸入端的直流電壓準位分別由信號Sd1及Sd2決定。隨著類比輸入信號32或數位輸入信號34的直流電壓準位變化,運算放大器26及28的負輸入端的直流電壓準位自動跟著變化。3 is a differential input class D amplifier to which the present invention is applied, which is based on the circuit of FIGS. 1 and 2, and the PWM modulator 18 does not need to input the drive circuit 13 as an input interface, so the class D The amplifier can be directly driven by the analog input signal 32 or the digital input signal 34. In PWM modulator 18, the positive inputs of operational amplifiers 26 and 28 are both floating, and the negative inputs respectively add discharge elements 40 and 42 to establish a discharge path for discharging charge. In this embodiment, the discharge element 40 includes a resistor R3 connected between the negative input terminal of the operational amplifier 26 and the ground GND. The discharge element 42 includes a resistor R4 connected between the negative input terminal of the operational amplifier 28 and the ground GND. In other embodiments, discharge elements 40 and 42 may establish a discharge path with other electronic components or circuits. This class D amplifier accommodates the analog input signal 32 and the digital input signal 34 due to the removal of the DC limiting capacitors Cin1 and Cin2 and the buffers 36 and 38. When the analog input signal 32 or the digital input signal 34 is applied to the class D amplifier, the resistors R1 and R3 divide the voltage at the positive input terminal 10 into a signal Sd1, and the resistors R2 and R4 divide the voltage at the negative input terminal 12 into a signal. Sd2. Since the positive inputs of operational amplifiers 26 and 28 are both floating, the DC voltage levels at the negative inputs of operational amplifiers 26 and 28 are determined by signals Sd1 and Sd2, respectively. As the DC voltage level of the analog input signal 32 or the digital input signal 34 changes, the DC voltage level at the negative input of the operational amplifiers 26 and 28 automatically changes.
進一步地,如圖4所示,可用雙輸出的運算放大器44取代圖3中的運算放大器26及28。運算放大器44的正輸入端連接電阻R1及放電元件40,負輸入端連接電阻R2及放電元件42,正輸入端及負輸出端之間連接電容C1,負輸入端及正輸出端之間連接電容C2。運算放大器44的正輸出端及負輸出端分別提供信號VinN及VinP給PWM產生器30。Further, as shown in FIG. 4, the operational amplifiers 26 and 28 of FIG. 3 can be replaced with dual output operational amplifiers 44. The positive input terminal of the operational amplifier 44 is connected to the resistor R1 and the discharge element 40, the negative input terminal is connected to the resistor R2 and the discharge element 42, the capacitor C1 is connected between the positive input terminal and the negative output terminal, and the capacitor is connected between the negative input terminal and the positive output terminal. C2. The positive and negative outputs of operational amplifier 44 provide signals VinN and VinP to PWM generator 30, respectively.
圖5係圖3中的功率級20及22的實施例,其包括MOSFET M1及M2受控於PWM信號SpwmP或SpwmN,而使切換節點LX切換連接電源端VDD及接地端GND,切換節點LX的電壓經LC濾波器46濾波後產生輸出信號VoP或VoN。在某些實施例中,可以不使用LC濾波器46,而將信號VoP及VoN直接施加到負載。5 is an embodiment of the power stages 20 and 22 of FIG. 3, including the MOSFETs M1 and M2 being controlled by the PWM signal SpwmP or SpwmN, and switching the switching node LX to the power supply terminal VDD and the ground GND, switching the node LX The voltage is filtered by LC filter 46 to produce an output signal VoP or VoN. In some embodiments, the signals VoP and VoN may be applied directly to the load without the use of the LC filter 46.
圖6係應用在單端負載的實施例,其電路的操作原理與圖3的實施例相同,但是D類放大器的輸入端及輸出端都是單一的,不是差動對。Figure 6 is an embodiment applied to a single-ended load. The operation of the circuit is the same as that of the embodiment of Figure 3, but the input and output of the Class D amplifier are single, not differential.
以上對於本發明之較佳實施例所作的敘述係為闡明之目的,而無意限定本發明精確地為所揭露的形式,基於以上的教導或從本發明的實施例學習而作修改或變化是可能的,實施例係為解說本發明的原理以及讓熟習該項技術者以各種實施例利用本發明在實際應用上而選擇及敘述,本發明的技術思想企圖由以下的申請專利範圍及其均等來決定。The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention to the disclosed embodiments. It is possible to make modifications or variations based on the above teachings or learning from the embodiments of the present invention. The embodiments are described and illustrated in the practical application of the present invention in various embodiments, and the technical idea of the present invention is intended to be equivalent to the scope of the following claims. Decide.
10...正輸入端10. . . Positive input
12...負輸入端12. . . Negative input
13...輸入驅動電路13. . . Input drive circuit
14...回授網路14. . . Feedback network
16...回授網路16. . . Feedback network
18...PWM調變器18. . . PWM modulator
20...功率級20. . . Power level
22...功率級twenty two. . . Power level
24...負載twenty four. . . load
26...運算放大器26. . . Operational Amplifier
28...運算放大器28. . . Operational Amplifier
30...PWM產生器30. . . PWM generator
32...類比輸入信號32. . . Analog input signal
34...數位輸入信號34. . . Digital input signal
36...緩衝器36. . . buffer
38...緩衝器38. . . buffer
40...放電元件40. . . Discharge element
42...放電元件42. . . Discharge element
44...運算放大器44. . . Operational Amplifier
46...LC濾波器46. . . LC filter
圖1係習知的類比輸入D類放大器;Figure 1 is a conventional analog input class D amplifier;
圖2係習知的數位輸入D類放大器;Figure 2 is a conventional digital input class D amplifier;
圖3係應用本發明的差動輸入D類放大器;Figure 3 is a differential input class D amplifier to which the present invention is applied;
圖4係根據本發明的另一實施例;Figure 4 is another embodiment in accordance with the present invention;
圖5係圖3中的功率級的實施例;以及Figure 5 is an embodiment of the power stage of Figure 3;
圖6係本發明應用在單端負載的實施例。Figure 6 is an embodiment of the invention applied to a single ended load.
10...正輸入端10. . . Positive input
12...負輸入端12. . . Negative input
14...回授網路14. . . Feedback network
16...回授網路16. . . Feedback network
18...PWM調變器18. . . PWM modulator
20...功率級20. . . Power level
22...功率級twenty two. . . Power level
24...負載twenty four. . . load
26...運算放大器26. . . Operational Amplifier
28...運算放大器28. . . Operational Amplifier
30...PWM產生器30. . . PWM generator
32...類比輸入信號32. . . Analog input signal
34...數位輸入信號34. . . Digital input signal
40...放電元件40. . . Discharge element
42...放電元件42. . . Discharge element
Claims (10)
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Citations (4)
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---|---|---|---|---|
US7116136B2 (en) * | 2003-12-16 | 2006-10-03 | International Rectifier Corporation | Gate driver with level shift between static wells with no power supply |
US7417497B2 (en) * | 2006-05-13 | 2008-08-26 | Samsung Electronics Co., Ltd. | PWM modulator and class-D amplifier having the same |
US20080284508A1 (en) * | 2007-05-15 | 2008-11-20 | Walker Brett C | Output circuits with class d amplifier |
TWM365019U (en) * | 2009-04-08 | 2009-09-11 | Amazing Microelectronic Corp | Distortion-suppressed D-type power amplifier |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7116136B2 (en) * | 2003-12-16 | 2006-10-03 | International Rectifier Corporation | Gate driver with level shift between static wells with no power supply |
US7417497B2 (en) * | 2006-05-13 | 2008-08-26 | Samsung Electronics Co., Ltd. | PWM modulator and class-D amplifier having the same |
US20080284508A1 (en) * | 2007-05-15 | 2008-11-20 | Walker Brett C | Output circuits with class d amplifier |
TWM365019U (en) * | 2009-04-08 | 2009-09-11 | Amazing Microelectronic Corp | Distortion-suppressed D-type power amplifier |
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