TWM365019U - Distortion-suppressed D-type power amplifier - Google Patents

Distortion-suppressed D-type power amplifier Download PDF

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Publication number
TWM365019U
TWM365019U TW98205707U TW98205707U TWM365019U TW M365019 U TWM365019 U TW M365019U TW 98205707 U TW98205707 U TW 98205707U TW 98205707 U TW98205707 U TW 98205707U TW M365019 U TWM365019 U TW M365019U
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Taiwan
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output
signal
control unit
positive
class
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TW98205707U
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Chinese (zh)
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Ming-Hsiung Chen
Shang-Shu Chung
Tung-Sheng Ku
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Amazing Microelectronic Corp
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Publication of TWM365019U publication Critical patent/TWM365019U/en

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.M365019 五、新型說明: 【新型所屬之技術領域】 本創作係關於一種音頻放大器,尤指具有失真抑制功 能之D類音頻放大器。 【先前技術】 . 音頻放大器係為驅動揚聲器之重要裝置,常見之音頻 放大器有AB類音頻放大器及〇類音頻放大器,其中,D φ 類音頻放大器之效率又比AB類音頻放大器之效率,高了 二至五倍,且,相較於AB類音頻放大器,D類放大器所 需之電源與功率消耗明顯地減小。 D類放大器主要係利用pwm( Pulse Width Modulation) 調變技術將輸入音頻訊號調轉變成為開關控制訊號,藉以 控制電力電子元件之導通與關斷,而達到放大音頻訊號之 目的。然而,經由D類放大器所放大之輸出音頻訊號,亦 參 包含調變後之高頻諧波,故,於D類放大器之後段輸出端, 係需要以一低通濾波器來濾除高頻諧波成分,於還原音頻 訊號之波形後,再將訊號送至揚聲器播放,但是,由於該 低通濾波器常為一 LC濾波器,乃增加了 D類放大器之體 積大小與電路成本。 因此,無濾波電路D類功率放大器(filterless class 〇 Power amplifier )亦逐漸被研究開發,如第一圖所示,係為 習知技術之無渡波電路D類功率放大器之電路結構圖,/ M365019 種無濾波電路D類功率放大器500係具有一輸入放大器 5 02; —誤差放大單元5 03; —第一與第二參考波產生器 5 04、5 05 ; —第一與第二比較器506、507 ; —閘極驅動電 路5 08 ; —輸出級場效電晶體單元509 ;及一回授單元513。 • 一音頻訊號501經由一輸入電容CIN5輸入至該輸入放 • 大器502之負輸入端’輸入放大器502前置放大該音頻訊 號501,並將一前置放大音頻訊號透過一積分器電阻R51 φ 輸入該誤差放大單元5 03,即,一積分器5 03 1之負輸入端, 且’該積分器503 1係耦接該積分器電阻R5 1與一積分器電 容C51,誤差放大單元503於放大該前置放大音頻訊號之 後’將§fl號輸入至該第一比較器506與該第二比較器507 之正輸入端。第一比較器506與第二比較器507之負輸入 端係分別耦接該第一參考波產生器5〇4與該第二參考波產 生器5〇5,第一參考波產生器5〇4與第二參考波產生器5〇5 # 刀別產生一弟一參考波與一第二參考波,透過音頻訊號與 參考波之比較,第一比較器5〇6與第二比較器5〇7分別輸 出一脈衝調變訊號至該閘極驅動電路5〇8,透過閘極驅動 電路508可控制常為功率電晶體所組成之一輸出級場效電 曰曰體單元509之開關,以分別於放大器之正輸出端(Quip) 、與負輸出端(OUTN)輸出音頻訊號至一揚聲器5n,且藉由 回授放大器5131與回授電阻(RFB1、RFB2、RFB3),係可 回授控制音頻增益大小。 4 M365019 上述之該無濾波電路D類功率 丁从a崙雖可尚效率地輪 出音頻sfl號至揚聲器,亦藉 一 楮田口杈早疋回應輸入音頻訊 號,但是,仍具有許多缺點與不足: !.該回授單元缺少可控制增益大小之設計,雖可正面回庫 輸入音頻訊號,卻無法控制因為音頻增益過大,而導致 音頻失真之現象,如第二 , Μ | 丁 你為習知技術之無濾 波電路之D類功率放大哭之於 。。之輸出波形圖,圖中雙箭頭所 標示之處,係為正輸出端(〇υτρ)輸出高準位與負輸 出端(⑽ΤΝ)輸出低準位,或,負輸出端(謝ν)輸 出南準位與正輸出端(〇υτρ)輸出低準位,由於揚聲 所接收到之曰頻矾號係為正輸出端訊號相減負輸出 、訊遽之值’因此,於相對古隹 ' 於相對间準位音頻訊號減掉相對低 準位音頻訊號之狀離下敫 先 、下%聲益所接收之音頻訊號,極 可能因為增益過大而失真。 2.由輸入放大器與誤差放女a 差敌大早兀所組成兩段式放大音頻 訊號,係過為複雜’且,容易造成前級輸出訊號至後級 時’而造成閉延遲(GateDelay)現象,亦即有可能因 為閘延遲而造成音頻失真之現象。 因此’本案之創作人有鑑於該無遽波電路D類功率放 大器’仍具各項隱含之缺失,故極力加以改良創新,終於 研發完成本創作之一種失真抑制之〇類功率放大器。 M365019 【新型内容】 本創作之主要目的,在於提供一種失真抑制之D類功 =放大器’利用簡單邏輯間之應用’係可監控輸出音頻訊 〜並防止音頻訊號失真,以保持揚聲器高品質之輸出。 • 本創作之次要目的,在於提供一種失直扣 具抑制之D類功 •立器,結合差動放大器與可變電阻,係可有效率地放 大音頻訊號,並防止因為閘延遲現象而造成音頻失真之現 -種失真抑制之D類功率放 ^ . 匕牯增盈控制 早7C,一第—脈衝調變單 .— — 早兀,一第一脈衝調變單元;一 流控制單元;及—準位控 制早70,該準位控制單元係具有 型正反器及至少-反互斥或邏輯間,該D型二 器之輸出端係輪接於該增益控制單元,且,該〇型正反器 之R端係麵接於兮拓$ ☆上 ° … 斥或邏輯閘之輸出端,當該失真抑 丨制之D類功率放大哭— r〇 之正輸出端(〇ut)與負輸出端 (Outb ) ’同時分別輪古 M胡 輸出呵準位與底準位訊號至反互斥或邏 軻閘,反互斥或邏輯 飞璉 輸出咼準位之訊號予D型正;5 器,D型正反器則輪 反 出巧準位訊號回授至增益控制單元, 以控制增盈控制單 -真之效果。 ^周降音頻增益大小,達到抑制音頻失 【實施方式 為了能夠更清 4地描述本創作所提出之一種失真 抑制 6 M365019 之D類功率放大器,以下將配合圖示,詳盡說明之。 請參閱第三圖與第四圖,係本創作之一種失真抑制之 D類功率放大器之電路結構圖,與,本創作之一種失真抑 制之D類功率放大器之完全差動放大器之電路結構圖,一 種失真抑制之D類功率放大器1,係具有一正輸出端(〇ut) 與一負輪出端(Outb )以驅動一揚聲器512,包括:.M365019 V. New Description: [New Technology Area] This creation is about an audio amplifier, especially a Class D audio amplifier with distortion suppression. [Prior Art] Audio amplifier is an important device for driving speakers. Common audio amplifiers include Class AB audio amplifiers and 〇 class audio amplifiers. Among them, D φ class audio amplifiers are more efficient than Class AB audio amplifiers. Two to five times, and the power and power consumption required for Class D amplifiers is significantly reduced compared to Class AB audio amplifiers. Class D amplifiers mainly use pwm (Pulse Width Modulation) modulation technology to convert the input audio signal into a switching control signal, thereby controlling the conduction and shutdown of the power electronic components to achieve the purpose of amplifying the audio signal. However, the output audio signal amplified by the class D amplifier also includes the modulated high frequency harmonics. Therefore, at the output end of the class D amplifier, a low pass filter is required to filter out the high frequency harmonics. The wave component, after restoring the waveform of the audio signal, sends the signal to the speaker for playback. However, since the low-pass filter is often an LC filter, the size and circuit cost of the class D amplifier are increased. Therefore, the filterless class 〇 Power amplifier is also being researched and developed. As shown in the first figure, it is a circuit structure diagram of a D-type power amplifier without a wave-wave circuit of the prior art, / M365019 Filterless Circuit Class D Power Amplifier 500 has an input amplifier 502; - Error Amplifying Unit 503; - First and Second Reference Wave Generators 5 04, 505; - First and Second Comparators 506, 507 ; - gate drive circuit 5 08; - output stage field effect transistor unit 509; and a feedback unit 513. • An audio signal 501 is input to the negative input terminal of the input amplifier 502 via an input capacitor CIN5. The input amplifier 502 preamplifies the audio signal 501, and transmits a preamplified audio signal through an integrator resistor R51 φ. The error amplifying unit 503 is input, that is, the negative input terminal of an integrator 503 1 , and the integrator 503 1 is coupled to the integrator resistor R5 1 and an integrator capacitor C51, and the error amplifying unit 503 is amplified. After the preamplified audio signal, the §fl number is input to the positive input terminals of the first comparator 506 and the second comparator 507. The first comparator 506 and the negative input end of the second comparator 507 are respectively coupled to the first reference wave generator 5〇4 and the second reference wave generator 5〇5, and the first reference wave generator 5〇4 And the second reference wave generator 5〇5# generates a reference wave and a second reference wave, and compares the audio signal with the reference wave, the first comparator 5〇6 and the second comparator 5〇7 A pulse modulation signal is respectively outputted to the gate driving circuit 5〇8, and the gate driving circuit 508 can control the switch of the output stage field effect unit 509 which is usually composed of a power transistor, respectively. The positive output terminal (Quip) and the negative output terminal (OUTN) of the amplifier output audio signals to a speaker 5n, and the feedback audio gain is fed back by the feedback amplifier 5131 and the feedback resistors (RFB1, RFB2, RFB3). size. 4 M365019 The above-mentioned filterless circuit class D power can effectively turn the audio sfl number to the speaker from a lun, and also responds to the input audio signal by a 楮田口杈, but still has many shortcomings and shortcomings: The feedback unit lacks the design of controllable gain. Although it can input the audio signal back to the library, it can't control the audio distortion caused by the excessive audio gain. For example, second, you are a well-known technology. The class D power amplification of the filterless circuit is crying. . The output waveform diagram, where the double arrow is indicated in the figure, is the positive output (〇υτρ) output high level and negative output ((10)ΤΝ) output low level, or the negative output (Xie ν) output south The level and the positive output (〇υτρ) output a low level, because the frequency received by the speaker is the positive output signal minus the negative output, the value of the signal 'is therefore relative to the ancient one' The inter-level audio signal loses the relatively low-level audio signal and the audio signal received by the lower and lower % audio is very likely to be distorted due to excessive gain. 2. The two-stage amplified audio signal composed of the input amplifier and the error amplifier is a two-stage amplified audio signal, which is complicated and 'is easy to cause the front-end output signal to the latter stage' and causes the GateDelay phenomenon. That is, there is a possibility that the audio is distorted due to the delay of the gate. Therefore, the creators of this case, in view of the implied lack of the class C power amplifier of the chopper-free circuit, have made great efforts to improve and innovate, and finally developed a class of power amplifiers for distortion suppression of the present invention. M365019 [New Content] The main purpose of this creation is to provide a Class D function of distortion suppression = Amplifier 'Using Simple Logic Application' to monitor output audio and prevent audio signal distortion to maintain high quality output of the speaker . • The second objective of this creation is to provide a Class D power stand that is out of direct buckle suppression, combined with a differential amplifier and a variable resistor to efficiently amplify the audio signal and prevent the delay due to the brake delay. The current distortion of the audio distortion type D power amplifier ^ 匕牯 gain control early 7C, a first - pulse modulation single. - early, a first pulse modulation unit; first-class control unit; The level control is early 70, the level control unit has a type of flip-flop and at least - anti-mutual or logic, the output end of the D-type is connected to the gain control unit, and the type is positive The R end of the counter is connected to the output of the $ or Logic gate. When the distortion is suppressed, the Class D power amplification is crying — r 〇 positive output (〇 ut) and negative output End (Outb) 'At the same time, the turn of the ancient M Hu output level and the bottom level signal to the anti-mutation or logic gate, the anti-mutual or logical fly-out output level signal to the D-type positive; 5, The D-type flip-flop is then sent back to the gain control unit to control the gain control. Billing - the effect of the truth. ^Weigh down the audio gain to achieve the suppression of audio loss. [Embodiment In order to be able to describe the distortion suppression 6 M365019 class D power amplifier proposed in this creation, the following will be explained in detail with the diagram. Please refer to the third and fourth figures, which is a circuit structure diagram of a distortion-suppressed class D power amplifier of the present invention, and a circuit structure diagram of a fully differential amplifier of a distortion-suppressed class D power amplifier of the present invention. A distortion-inhibiting class D power amplifier 1 has a positive output terminal (〇ut) and a negative wheel output terminal (Outb) to drive a speaker 512, including:

一增益控制單元2,包括一完全差動運算放大器(FuUy differential OPA ) 21,該完全差動運算放大器以係具有一 正輸入端(vin+)與一負輸入端(Vin_),及’一正輸出端 (vout+)與一負輸出端(v〇ut_),完全差動運算放大器η 之該正輸入端與該負輸入端係耦接於一音頻訊號5〇1,且 於放大該音頻訊號501後,由該正輸出端與該負輸出端, 透過一電阻R16與一電阻R17將一放大音頻訊號輪出至下 一級之二脈衝調變單元4; 一第一可變電阻Rlv,係耦接 於 完全差動運算放大器21之正輸人端(Vin+)與負輸出端 (V0ut-)之間,猎由調整該第一可變電阻Rv丨之電阻值, 可調變完全差動運算放大器21之負輸出端所輸出之該放 大音頻訊號之增益大小;及一第二可變電阻RV2,係叙接 與正輪出端 之電阻值, 於完全差動運算放大器21之負輸入端(vin_) (Vout+ )之間,藉由調整該第二可變電阻 可調變完全差動運算放大器 音頻訊號之增益大小; 21之正輸出端所輸出之放大 .M365019 二脈衝調變單元4,請參閱第五圖,係本創作之一種 失真抑制之D類功率放大器之脈衝調變單元之電路結構 圖,係包括一參考波產生器41與一比較器42,該比較器 係八有正輸入端、一負輸入端、及一輸出端,比較器 42之該負輸入端係耦接該參考波產生器41,以接收參考波 產生器41所產生之一參考波訊號,於本實施例中,係使用 兩組脈衝調變單元4,其分別耗接該完全差動運算放大器 _之該負輸出端(V〇ut.)與該正輸出端(v〇ut+),因此,一組 脈衝調變單元4之比較器42之正輸入端係透過該電阻請 接於凡王差動運算放大器21之負輪出端(v_),而另 —組脈衝調變單元之比較器42之正輸入端係透過電阻R17 :接於完全差動運算放大器21之該正輸出端(v_+),以 :接收完全差動運算放大器21之正輸出端與負輸出端 •生二:該放大音頻訊號,另外,二參考波產生器41所產 算Γ 號係為反相,以利比較器42對於完全差動運 號,r 21之正輸出端與負輪出端所輸出之放大音頻訊 1:::較,當放大音頻訊號之準位高於參考波訊號, 42輪1:準輸出尚準位之脈衝調變訊號,反之,則比較器 • —準位之脈衝調變訊號; 變單 * 4 “I曰體驅動早凡6,係分別耦接於該脈衝調 輪出級場效電晶體組 7 ’係包括—耦接Vcc之N型 8 M365019 功率場效電晶體QN與一接地之p型功率場效電晶體Qp, 分別輕接於該場效電晶體驅動單& 6,場效電晶體驅動單 元6接收該脈衝調變單元4所輸出之脈衝調變㈣,並基 於此脈衝調變訊號以控制輸出級場效電晶體組7之導通與 關閉’以驅動揚聲器512 ; /、 -準位控制單元8,係包括至少一 D型正反㈣,該 D型正反器81係具有一〇端、_ck端、一 q端、— 端、及一 Μ—。’其中ID端與該《端係為輸 入端,且,該Q端與該Qb端係為輸出端,d型正反器Μ 之D端係搞接一 Vrr之真進Μ + 阿卓位直流訊號,且,其CK端係A gain control unit 2 includes a fully differential operational amplifier (FuUy differential OPA) 21 having a positive input terminal (vin+) and a negative input terminal (Vin_), and a positive output The terminal (vout+) and a negative output terminal (v〇ut_), the positive input terminal and the negative input terminal of the fully differential operational amplifier η are coupled to an audio signal 5〇1, and after the audio signal 501 is amplified From the positive output terminal and the negative output terminal, an amplified audio signal is rotated through a resistor R16 and a resistor R17 to the second pulse modulation unit 4 of the next stage; a first variable resistor Rlv is coupled to Between the positive input terminal (Vin+) and the negative output terminal (V0ut-) of the fully differential operational amplifier 21, the hunting is adjusted by the resistance value of the first variable resistor Rv丨, and the fully variable operational amplifier 21 can be adjusted. The gain of the amplified audio signal outputted by the negative output terminal; and a second variable resistor RV2, which is connected to the negative terminal of the positive terminal (vin_) of the fully differential operational amplifier 21 ( Between Vout+), by adjusting the second variable resistor The gain of the audio signal of the fully differential op amp; the amplification of the output of the positive output of 21. M365019 The two-pulse modulation unit 4, please refer to the fifth figure, which is the pulse modulation of a class D power amplifier with distortion suppression. The circuit structure diagram of the variable unit includes a reference wave generator 41 and a comparator 42 having a positive input terminal, a negative input terminal, and an output terminal, and the negative input terminal of the comparator 42 The reference wave generator 41 is coupled to receive a reference wave signal generated by the reference wave generator 41. In this embodiment, two sets of pulse modulation units 4 are used, which respectively consume the fully differential operational amplifier. The negative output terminal (V〇ut.) and the positive output terminal (v〇ut+), therefore, the positive input terminal of the comparator 42 of the group of pulse modulation unit 4 is transmitted through the resistor. The negative output terminal (v_) of the operational amplifier 21, and the positive input terminal of the comparator 42 of the other-group pulse modulation unit is transmitted through the resistor R17: connected to the positive output terminal of the fully differential operational amplifier 21 (v_+) ) to: receive the positive of the fully differential operational amplifier 21 Output terminal and negative output terminal • Raw two: the amplified audio signal, in addition, the second reference wave generator 41 generates an inversion phase to facilitate the comparator 42 for the fully differential carrier, the positive output of r 21 The amplified audio signal output from the end and the negative wheel output is 1::: When the level of the amplified audio signal is higher than the reference wave signal, the 42 round 1: the quasi-output is still the pulse modulation signal, and vice versa. The pulse modulation signal of the position of the device is changed to the position of the VCO. The type 8 M365019 power field effect transistor QN and a grounded p-type power field effect transistor Qp are respectively connected to the field effect transistor driving unit & 6, the field effect transistor driving unit 6 receives the pulse modulation unit 4 output pulse modulation (four), and based on the pulse modulation signal to control the on and off of the output stage field effect transistor group 7 to drive the speaker 512; /, - level control unit 8, including at least one D Type positive and negative (four), the D-type flip-flop 81 has a terminal, _ck terminal, a q terminal, - terminal, A Μ-. 'The ID end and the 'end end are the input end, and the Q end and the Qb end are the output end, and the D end of the d-type flip-flop Μ is connected to a real Vrr of the Vrr + Azhuo DC Signal, and its CK end

耦接一時脈訊號(Cl0ck),D 反态81之Q端係耦接於 增盤控制單元2…其Qb端係為浮接 及至少—反互斥或邏輯^Xn〇r)82 R) 82,该反互斥或邏輯閘 82係具有二輸入端與一 輪出^,反互斥或邏輯開82之該 一輸入端係分別耦接於 大具抑制之D類功率放大丨之 該正輸出端(〇ut)盥該負於+山 為之Coupled with a clock signal (Cl0ck), the Q terminal of the D inverse 81 is coupled to the add-on control unit 2... the Qb end is floating and at least - anti-mutual or logical ^Xn〇r) 82 R) 82 The anti-mutual or logic gate 82 has two input terminals and one round output, and the one of the input terminals of the anti-mutation or logic switch 82 is respectively coupled to the positive output terminal of the greatly suppressed class D power amplifier. (〇ut) 盥 It should be lost to + mountain

、别出鳊(Outb),反互斥或邏輯 問82之該輸出端則耦接於D 生正反窃81之該尺端 (Reset)’請參閱第六, Outb, Anti-mutual or Logic The output of the 82 is coupled to the D of the D-spoken 81. Please refer to the sixth.

, 係本創作之一種失真抑制之D 類功率放大器之準位控制單元 巾,# & 1 電路結構圖,於本實施例 中係串接兩組D型正反器, a level control unit for a distortion-suppressed Class D power amplifier, # & 1 circuit structure diagram, in this embodiment, two sets of D-type flip-flops are connected in series

$山接#丨 ° ’虽D型正反器81之CK 鳊接收到該糸統時脈訊號之逮>$山接#丨 ° ' Although the CK of the D-type flip-flop 81 receives the signal of the system clock >

類功率放大罙夕 又為,且失真抑制之D 大為之正輸出端(〇ut) )與負輸出端(Outb)分別 9 M365019 輸出n準位(High)與—低準位(L〇w)之音頻訊號予 该揚聲器512,若該高準位與該低準位之音頻訊號持續輸 出時間超過一’則揚聲器512所接收之音頻訊號係為失 真,此時’反互斥或邏輯閑82於接收失真抑制之D類功率 .放大器之正輸出端(0ut)與負輸出端(Μ)所輸出之高 •準位與低準位訊號後,依照反互斥或邏輯閑之反應特性, 反互斥或邏輯閘82將立即輸出高準位訊號至D型正反器 81之R端,由於第_ έθ η μ ^ 、、、、i正反器8 1之E)端係耦接該Vcc 之直流高準位訊號,故,依照D型正反器之反應特性,第 =組D型正反器81即輸出高準位訊號至第二組d型正反 m,第一組D型正反器81則會輸出高準位訊號回授至 單元2’以控制增益控制單元2調降音頻增益 閱第、1抑制日頻失真之效果,·及二比較器83,請表 閱第六圖B ’係本創作 " 之準位控制單元之Γ 失真抑制之D類功率放大器 电路結構圖,於本實施例中 器83係分別具有二輸入端及 -比較 X ,山〆、 输出端’比較器83之正輪 “別耦接於完全差動運算放大器之正輸出端與負輸 出端,比較器83之負 ’、、即 比較器83之輸出Μ _接-參考電塵VREF’且’ &係分別叙接第—可變電阻盥第-可變 電阻,比較“3之功能係對於完全差動運,丄了 k 出端與負輸出端所於山 -王差動運异放大器之正輸 確認,並將結果回… 、心"仃初步之失真 U第一可變電阻與第二可變電阻,以 10 M365019 調整音頻之增益。 另外’於本實施例中,亦包括了 一電流控制單_ 該電=控制單元3係輕接該兩組脈衝調變單元4,該電流 控制單元3可產生固定電流訊號,而與放大音頻、 11爾*形成 二流«訊號,利用調整該電流調變訊號,可控制减少功 率放大器之輸出消耗功率之大小;及 複數個電阻,該電阻R1 5、R1 8耦接於該失真抑制之〇 類功率放大器i之正輸出端(〇ut)及負輸出端⑺二: 脈衝調變單疋4之間,係為輸出之回授電阻,電阻幻6 ^ R17耦接於脈衝調變單元4與該增益控制單元2之間 為輸入之緩衝電阻。 係 ❿ 綜合上述,本創作係藉由於輸出端與增益控制單元之 入使用D型正反器與反互斥或邏輯閉,來監控輪 端之訊號,並利用回授功能來抑制音頻訊號之失真 本創作之失真抑制之D類功率放大器,相對於其它習 用技術,更具有下列之優點: I.本創:之失真抑制之D類功率放大器,藉由簡單 ^反:與反互斥或邏輯閘之配合,可即時監控音頻功率 大器之輸出音頻訊號是否失真 出之音頻訊號係已失直,可^旦發現輪出端所輪 頻之增益大小。 《方式凋整音Class power amplification is again, and the distortion suppression D is the positive output (〇ut) and the negative output (Outb) respectively. 9 M365019 Output n level (High) and - low level (L〇w The audio signal is given to the speaker 512. If the audio signal of the low level and the low level continues to output for more than one time, the audio signal received by the speaker 512 is distorted, and the anti-mutation or logic is 82. For the D-type power receiving distortion suppression, the high-level and low-level signals output by the positive output (0ut) and the negative output (Μ) of the amplifier are in accordance with the anti-mutation or logic idle response characteristics. The mutex or logic gate 82 will immediately output the high level signal to the R terminal of the D-type flip-flop 81, since the first _ έ θ η μ ^ , , , i the flip-flop 8 1 E) is coupled to the Vcc The DC high-level signal, therefore, according to the reaction characteristics of the D-type flip-flop, the first group D-type flip-flop 81 outputs the high-level signal to the second group d-type positive and negative m, the first group D-type positive The counter 81 outputs a high level signal to the unit 2' to control the gain control unit 2 to lower the audio gain, and to suppress the effect of the day frequency distortion. For the comparators and the second comparators 83, please refer to the circuit diagram of the class D power amplifier circuit of the distortion suppression of the level control unit of the sixth drawing B. In the present embodiment, the device 83 has The two inputs and the comparison X, the mountain, the output terminal 'the positive wheel of the comparator 83' are not coupled to the positive output and the negative output of the fully differential operational amplifier, the negative of the comparator 83, that is, the comparator 83 output Μ _ connection - reference electric dust VREF ' and ' & respectively, the first - variable resistance 盥 first - variable resistance, compare "3 function for the complete differential operation, 丄 k origin and The negative output is confirmed by the positive transmission of the mountain-king differential amplifier, and the result is returned to..., the heart "仃the initial distortion U first variable resistor and the second variable resistor, adjust the audio with 10 M365019 Gain. In addition, in the present embodiment, a current control unit is also included. The electric control unit 3 is connected to the two sets of pulse modulation units 4, and the current control unit 3 can generate a fixed current signal, and amplify the audio, 11 er * form a second-rate «signal, by adjusting the current modulation signal, the output power consumption of the power amplifier can be controlled to be reduced; and a plurality of resistors, the resistors R1 5, R1 8 are coupled to the power of the distortion suppression The positive output terminal (〇ut) and the negative output terminal (7) of the amplifier i are two: between the pulse modulation unit 疋4, which is the feedback resistor of the output, and the resistor phantom 6 ^ R17 is coupled to the pulse modulation unit 4 and the gain The control unit 2 is the input buffer resistor. System ❿ In summary, the author uses the D-type flip-flop and the anti-mutation or logic-closed to monitor the signal of the wheel end by using the output terminal and the gain control unit, and uses the feedback function to suppress the distortion of the audio signal. The distortion-suppressed Class D power amplifier of this creation has the following advantages over other conventional technologies: I. Innovative: Distortion-suppressed Class D power amplifier with simple anti-reverse: anti-mutation or logic gate The cooperation can instantly monitor whether the audio signal of the audio power amplifier is distorted or not, and the audio signal is out of straightness, and the gain of the round frequency of the wheel end can be found. Mode of sound

2·本創作之失真抑制之D 千孜大态,係使用整合型之 M365019 兀全差動放大器作為音頻訊號之前置放大,利用調變可 變電阻之電阻值’以調整音頻放大之増益大小,相較於 習知之功率放大器係使用兩段式之音頻放大,本創作僅 使用一μ整合型之完全差動放大器,係可避免前後級放 大器’於輸出、輸入之時,而造成閘延遲(Gate Delay) 現象之發生。 上列#細說明係針對本創作之一可行實施例之具體說 明,惟該實施例並非用以限制本創作之專利範圍,凡未脫 離本創作技藝精神所為之等效實施或變更,均應包含於本 案之專利範圍中。 【圖式簡單說明】 第一圖 為習知技術之無濾波之D類功率放 大器之電路結構圖; 第二圖 為習知技術之無濾波之D類功率放 大器之輸出波形圖; 第三圖 為本創作之—種失真抑制之D類功 率放大器之電路結構圖; 第四圖 為本創作之一種失真抑制之D類功 率放大器之完全差動運算放大器之 電路結構圖; 第五圖 為本創作之一種失真抑制之D類功 ;'大器之脈衝調變單元之電路結 12 M365019 構圖; 第六圖A、第六圖B 為本創作之一種失真抑制之D類功 率放大器之準位控制單元之電路結 構圖。 【主要元件符號說明】 1 失真抑制之D類功率放大器 2 增益控制單元 21 完全差動運算放大器 3 電流控制單元 4 脈衝調變單元 41 比較器 42 參考波產生器 6 閘極驅動單元 7 輸出級場效電晶體組 8 準位控制單元 81 D型正反器 82 反互斥或邏輯閘(XNOR) 83 比較器 500 無濾波電路之功率放大器 501 音頻訊號 502 輸入放大器 503 誤差放大單元 13 M3650192. The distortion suppression D of this creation is based on the integrated M365019 兀 full differential amplifier as the audio signal preamplifier, using the resistance value of the variable resistor to adjust the gain of audio amplification. Compared with the conventional power amplifier system, which uses two-stage audio amplification, this creation uses only a one-integration type fully differential amplifier, which can avoid the delay of the front-end amplifier's output and input. Gate Delay) The phenomenon occurs. The above description is a detailed description of one of the possible embodiments of the present invention, but the embodiment is not intended to limit the scope of the patent, and equivalent implementations or modifications that are not departing from the spirit of the present invention should include In the scope of the patent in this case. [Simple diagram of the diagram] The first diagram is the circuit structure diagram of the filterless class D power amplifier of the prior art; the second diagram is the output waveform diagram of the filterless class D power amplifier of the prior art; The circuit structure diagram of the class D power amplifier of the distortion suppression of the present invention; the fourth figure is the circuit structure diagram of the fully differential operational amplifier of the class D power amplifier of the distortion suppression of the creation; A class D function of distortion suppression; a circuit of a pulse modulation unit of a large device 12 M365019 composition; a sixth figure A, a sixth figure B is a level control unit of a class D power amplifier of distortion suppression Circuit structure diagram. [Description of main component symbols] 1 Class D power amplifier with distortion suppression 2 Gain control unit 21 Fully differential operational amplifier 3 Current control unit 4 Pulse modulation unit 41 Comparator 42 Reference wave generator 6 Gate drive unit 7 Output stage field Effect transistor group 8 Level control unit 81 D-type flip-flop 82 Anti-mutation or logic gate (XNOR) 83 Comparator 500 Power amplifier without filter circuit 501 Audio signal 502 Input amplifier 503 Error amplification unit 13 M365019

503 1 積分器 504 第一參考波產生器 505 第二參考波產生器 506 第一比較器 507 第二比較器 508 閘極驅動電路 509 輸出級場效電晶體單元 5 12 揚聲器 5 13 回授單元 5131 回授放大器 RFB1 〜RFB3 電阻 R51 電阻 CIN5 、C51 電容 Q51〜 Q54 場效電晶體 R15〜 R18 電阻 RV1 第一可變電阻 RV2 第二可變電阻 QN N型功率場效電晶體 QP P型功率場效電晶體 VREF 參考電壓 14503 1 integrator 504 first reference wave generator 505 second reference wave generator 506 first comparator 507 second comparator 508 gate drive circuit 509 output stage field effect transistor unit 5 12 speaker 5 13 feedback unit 5131 Feedback amplifier RFB1 ~ RFB3 resistor R51 resistor CIN5, C51 capacitor Q51 ~ Q54 field effect transistor R15 ~ R18 resistor RV1 first variable resistor RV2 second variable resistor QN N-type power field effect transistor QP P-type power field effect Transistor VREF reference voltage 14

Claims (1)

M365019 六、申請專利範園: K 一種失真抑制之D類功率放大器,係具有—正輸㈣ (⑽)與-負輸出端(0utb)以驅動一揚聲器,包括: 增盈控制單元,係轉接—音頻訊號,· •至v m衝調變單元,係耗接該增益控制單元,以接收 增益控制單凡所輸出之一放大音頻訊號,並產生調變訊 號; ° 場效電Ba體驅動單元,係耦接於該脈衝調變單元. ^輸出級場效電晶體組,係麵接該場效電晶體驅動 早^場效電晶體驅動單元接收脈衝調變單元所輪出之 脈衝调變訊號,並基於此脈衝調變訊號以控制該輸出級 場效電晶體組之開關,以驅動該揚聲器;及 、 一準位控制單元,係包括: 至少- D型正反器,係具有二輸入端、二輸出端、及一 R端(R—,該D型正反器之該二輸入端係分別耦接 - VCC之高準位直流訊號,與’一時脈訊號(一), 且D型正反器之該二輸出端係分別輕接於增益控制單 元與’係為浮接(fl〇ating)狀態;及 二二反互斥或邏輯間(X職)’係具有二輪入端與一 輸出為,邊反互斥或邏輯閘之該輪 輸入為係分別耦接於 錢真抑制之D類功率放大器之該正輸出端(㈣鱼該 負輸出端(〇Utb),且反互斥或邏輯閑之該輪出端則轉 15 M365019 接於D型正反器之該R端(Reset) A 、Set) ’當失真抑制之D 類功率放大器之正輪 輸出為(〇Ut)與負輸出端(Outb), 分別同時輸出高準#〆u、t lgh)與底準位(Low)訊號至反 互斥或邏輯閘之二輸入 及立斤或邏輯閘即輸出高準 位訊號予D型|1: θ ^ , Λ > ° 51正反器則輸出高準位訊號回 授至增益控制單元,以 割瑨I控制早疋調降音頻增益 大小,達到抑制音頻失真之效果。 2·如申請專利範圍第 斤述之一種失真抑制之D類功率 放大器,更包括: :電流控制單元’係叙接該脈衝調變單元,該電流控制 早二了產生固定電流訊號’而與該放大音頻訊號形成電 流調變訊號;及 複數個電阻,該電 Ρ耦接该失真抑制之D類功率放大器 之正輸出M (〇Ut)及負輸出端(〇_)與該脈衝調變單 系為輸出之回授冑阻,且麵接於脈衝調變單 元與該增益控制單元,係為輸人之緩衝電阻。 3.如申請專利範項所収—種失真抑社D類功率 放大斋,其中,該增益控制單元包括: 一完全差動運算放大器(Fully differential 0PA ),係具 有正輸入端(Vin+)與一負輸入端(W),及—正 輸:端(V〇叫與1輸出端(V_-),該完全差動 運鼻放大器之u t ^ ^與該負輸入端係轉接於該音類 16M365019 VI. Patent Application Park: K A Class-D power amplifier with distortion suppression, which has a positive (4) ((10)) and a negative output (0utb) to drive a speaker, including: Increase control unit, transfer - audio signal, · • to vm modulation unit, is connected to the gain control unit to receive the gain control unit to output one of the amplified audio signals, and generate a modulation signal; ° field effect electric Ba body drive unit, The system is coupled to the pulse modulation unit. The output stage field effect transistor group is connected to the field effect transistor driving the early field effect transistor driving unit to receive the pulse modulation signal rotated by the pulse modulation unit. And based on the pulse modulation signal to control the switch of the output stage field effect transistor group to drive the speaker; and, a level control unit, comprising: at least a D-type flip-flop having two inputs, The second output end and the R end (R-, the two input ends of the D-type flip-flop are respectively coupled to the high-level DC signal of the VCC, and the 'one-time pulse signal (1), and the D-type positive and negative The two output ends of the device are respectively connected to The control unit and the 'floating state of the line; and the two-two anti-mutual or logical (X job)' system have two rounds of input and one output, side anti-mutation or logic gate The input is coupled to the positive output of the Class D power amplifier of Qianzhen suppression ((4) the negative output of the fish (〇Utb), and the output of the anti-mutation or logic idle is 15 M365019 The R terminal of the D-type flip-flop A, Set) 'When the distortion-reduced D-type power amplifier has the positive-wheel output (〇Ut) and the negative output (Outb), the high-order output is simultaneously output. , t lgh) and the bottom level (Low) signal to the anti-mutation or logic gate two inputs and the jin or logic gate that outputs the high level signal to the D type |1: θ ^ , Λ > ° 51 positive and negative The device outputs a high-level signal to the gain control unit to control the early and lower audio gain by cutting the I to achieve the effect of suppressing audio distortion. 2. A class D power amplifier of the type of distortion suppression as described in the patent application scope includes: a current control unit 'connects the pulse modulation unit, the current control generates a fixed current signal' Amplifying the audio signal to form a current modulation signal; and a plurality of resistors coupled to the positive output M (〇Ut) and the negative output terminal (〇_) of the distortion-suppressed class D power amplifier and the pulse modulation system The feedback resistor for the output is connected to the pulse modulation unit and the gain control unit, and is a buffer resistor for the input. 3. As claimed in the patent application, the distortion control unit D power amplification, wherein the gain control unit comprises: a fully differential operational amplifier (Fully differential 0PA) having a positive input terminal (Vin+) and a negative Input (W), and - positive input: end (V squeak and 1 output (V_-), the ut ^ ^ of the fully differential nose amplifier and the negative input are switched to the tone class 16
TW98205707U 2009-04-08 2009-04-08 Distortion-suppressed D-type power amplifier TWM365019U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI407688B (en) * 2010-05-26 2013-09-01 Richtek Technology Corp Pwm modulator for a class-d amplifier and class-d amplifier adaptive to analog and digital input by using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI407688B (en) * 2010-05-26 2013-09-01 Richtek Technology Corp Pwm modulator for a class-d amplifier and class-d amplifier adaptive to analog and digital input by using the same

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