JP2012231264A - Power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a speaker connected to a power amplifier from popping at an operation start of the power amplifier after offset compensation.SOLUTION: A DC voltage generation circuit 170 supplies a DC voltage to output terminals T21 and T22 of a class D amplifier to offset-cancel differential amplifiers in the class D amplifier. A discharging resistance RDIS and an N channel transistor 183 are interposed between an output terminal T30 of the DC voltage generation circuit 170 and a ground line. On completion of offset cancellation, the N channel transistor 183 is turned on in a stable period before the start of amplification action of the class D amplifier to discharge electrical charges in capacitances C1 and C2 connected to the output terminals T21 and T22 via the discharging resistance RDIS and the N channel transistor 183. This can prevent popping.

Description

  The present invention relates to a power amplifier having an offset cancel function.

  The offset voltage is generated in the differential amplifier inside the power amplifier due to the characteristic variation of each element constituting the power amplifier, and the voltage of the output signal of the power amplifier in the no-signal input state due to this offset voltage. There may be a deviation of the value from the ideal voltage value (that is, the offset voltage of the output signal of the power amplifier). In this case, when the operation of the power amplifier is started from the no-signal input state, an offset voltage is output from the power amplifier to the speaker, so that an unpleasant pop sound is emitted from the speaker. Therefore, various power amplifiers having a function of canceling such an offset voltage are provided. For example, Patent Document 1 discloses a class D amplifier having an offset cancel function. This class D amplifier has an error integrator constituted by a differential amplifier having an offset cancellation function, and a pulse width modulator. Here, the error integrator integrates an error between the input signal and the output pulse signal of the class D amplifier fed back through the feedback resistor. The pulse width modulator outputs a pulse that is pulse width modulated by the integration value of the error integrator. The class D amplifier supplies the pulse output from the pulse width modulator to the load as an output pulse signal. In Patent Document 1, a DC voltage corresponding to an ideal DC level of the output pulse signal of the class D amplifier at the time of no signal input is applied to the output terminal of the class D amplifier, and the same error integrator as at the time of no signal input is obtained. In this state, the differential amplifier of the error integrator performs the offset canceling operation.

JP 2008-17358 A

  By the way, when a speaker is connected to a power amplifier such as a class D amplifier, a low-pass filter including a capacitor is usually interposed between the power amplifier and the speaker. When the above-described offset cancel operation is performed in a state where such a low-pass filter and a speaker are connected to the power amplifier, the capacitance of the low-pass filter is charged by the DC voltage when the DC voltage is applied to the output terminal. Here, after the offset cancel operation is completed, if the power amplifier starts operating with the charge remaining in the capacitance of the low-pass filter, a pop sound may be emitted from the speaker connected to the low-pass filter. is there.

  The present invention has been made in view of the circumstances as described above, and provides technical means for preventing pop sound from being emitted from a speaker connected to the power amplifier at the start of operation of the power amplifier after offset cancellation. It is intended to provide.

  The present invention includes a differential amplifier, a feedback resistor interposed between an output terminal to which a load is connected and an input portion of the differential amplifier, and outputs an output signal from the output terminal to the feedback resistor. An offset correction command is given to a power amplifier that amplifies an input signal by the differential amplifier and generates an output signal for driving the load from the output terminal while negatively feeding back to the input portion of the differential amplifier. Offset control means for performing control to reduce the offset generated in the output signal of the differential amplifier, and DC voltage generating means for outputting a DC voltage corresponding to the output signal of the power amplifier in a no-signal input state, By giving a discharge command, a discharge means for forming a discharge path between the output terminal of the power amplifier and a reference voltage line, and a trigger signal are given. The DC voltage generating means is connected to the output terminal of the power amplifier, and the DC voltage output from the DC voltage generating means is applied to the input portion of the differential amplifier via the feedback resistor, and then the offset control A power amplifier is provided, comprising: control means for giving an offset correction command to the means, then giving a discharge command to the discharge means, and then causing the power amplifier to start an amplification operation.

  According to this invention, the DC voltage generating means is connected to the output terminal of the power amplifier in order to cancel the offset of the differential amplifier in a state where a load comprising a low-pass filter including a capacitor and a speaker is connected to the output terminal of the power amplifier. Is applied to the input portion of the differential amplifier via a feedback resistor, and the capacitance of the low-pass filter connected to the output terminal is charged by this DC voltage. After the offset cancel operation of the differential amplifier is performed, the discharge means forms a discharge path between the output terminal of the power amplifier and the reference voltage line, and charges the capacitor connected to the output terminal of the power amplifier. Charges are discharged through this discharge path. Then, after discharging the charged charge of the capacitor by the discharging means, the amplification operation of the power amplifier is started. Therefore, it is possible to prevent the pop sound from being emitted from the speaker when the amplification operation of the power amplifier is started.

It is a circuit diagram which shows the structure of the class D amplifier which is one Embodiment of the power amplifier by this invention. It is a time chart which illustrates the output pulse signal waveform of the same class D amplifier. It is a circuit diagram which shows the structure of the offset cancellation control circuit of the same class D amplifier. 5 is a time chart showing a process from when an offset cancellation operation is performed to when an amplification operation is started in the same class D amplifier. It is a circuit diagram which shows the structure of the offset cancellation control circuit of the conventional class D amplifier. 5 is a time chart showing a process from when an offset cancellation operation is performed to when an amplification operation is started in the same class D amplifier.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a class D amplifier which is an embodiment of a power amplifier according to the present invention. 1, analog input signals AIN (+) and AIN (−) having opposite polarities are input from the external signal source SIG through capacitors Cin1 and Cin2, respectively. The class D amplifier according to the present embodiment generates pulse signals OUTP and OUTM that are pulse width modulated by analog input signals AIN (+) and AIN (−) from the signal source SIG and whose duty ratio changes complementarily. The amplifiers output from output terminals T21 and T22, respectively.

  In FIG. 1, an input stage amplifier 100 includes a differential amplifier 101, input resistors R11 and R12, feedback resistors R21 and R22, and switches SWOS1 and SWOS2. Here, the input resistor R11 and the switch SWOS1 are inserted in series between the input terminal T11 and the inverting input portion of the differential amplifier 101, and the input resistor R12 and the switch SWOS2 are connected to the input terminal T12 and the differential amplifier 101. It is inserted in series with the non-inverting input unit. A feedback resistor R21 is connected between the inverting input unit and the non-inverting output unit of the differential amplifier 101, and a feedback resistor R22 is connected between the non-inverting input unit and the inverting output unit.

  The error integrator 110 includes a differential amplifier 111, capacitors 112 and 113, and input resistors R31 and R32. Here, the inverting input portion of the differential amplifier 111 is connected to the non-inverting output portion of the differential amplifier 101 via the input resistor R31, and the non-inverting input portion of the differential amplifier 111 is differentially connected via the input resistor R32. It is connected to the inverting output part of the amplifier 101. Further, a capacitor 112 is inserted between the inverting input unit and the non-inverting output unit of the differential amplifier 111, and a capacitor 113 is inserted between the non-inverting input unit and the inverting output unit. Further, a feedback resistor R41 is inserted between the output terminal T21 of the class D amplifier and the inverting input part of the differential amplifier 111, and the output terminal T22 of the class D amplifier and the non-inverting input part of the differential amplifier 111 are connected. A feedback resistor R42 is interposed between them. The error integrator 110 outputs positive and reverse two-phase input signals SA and SB inputted through input resistors R31 and R32, and output pulse signals OUTP and OUTM of a class D amplifier fed back through feedback resistors R41 and R42. Are integrated, and positive and negative two-phase integral value signals SC and SD indicating the integral value are output from the non-inverting output unit and the inverting output unit of the differential amplifier 111, respectively.

  In the present embodiment, the differential amplifier 111 of the error integrator 110 includes a constant current source having a variable current value. One of the transistors constituting the differential transistor pair is selected, and the constant current source of the constant current source is selected. An input offset can be generated by flowing an output current. The comparator 140 and the offset control unit 141 allow the offset of the differential amplifier 111 so that there is no offset between the output signals of the non-inverting output unit and the inverting output unit of the differential amplifier 111 when the offset correction command signal CAN is given. Means for controlling the input offset. In the present embodiment, when an offset voltage is generated in the output pulse signals OUTP and OUTM of the class D amplifier at the time of no signal input, the input composed of the comparator 140 and the offset control unit 141 is generated by the differential amplifier 111. By appropriately controlling the offset, the offset voltage appearing in the output pulse signals OUTP and OUTM is canceled.

  Integration value signals SC and SD output from error integrator 110 are input to pulse width modulation circuit 120. The pulse width modulation circuit 120 uses a triangular wave signal generated by a triangular wave generation circuit (not shown) as a carrier, and uses this carrier to generate complementary two-phase pulses P and M that are pulse width modulated by the integrated value signals SC and SD. Occur.

  The drive circuit 130 includes output buffers 131 and 132. These output buffers 131 and 132 are so-called three-state buffers, and are supplied with an enable signal EN for switching the output state. Here, when the enable signal EN is at the H level, the output buffer 131 outputs the pulse P output from the pulse width modulation circuit 120 to the output terminal T21 as the output pulse signal OUTP, and the output buffer 132 includes the pulse width modulation circuit. The pulse M output from 120 is output as an output pulse signal OUTM to the output terminal T22. On the other hand, when the enable signal EN is at L level, the output impedances of the output buffers 131 and 132 are high impedance.

  The offset cancel control circuit 160 performs control for canceling the offset voltage included in the output pulse signals OUTP and OUTM of the class D amplifier in response to a trigger signal INIT generated when the class D amplifier is reset or activated. It is a circuit to perform. Details of the offset cancel control circuit 160 will be described later.

  A speaker is connected to the output terminals T21 and T22 of the class D amplifier via a low-pass filter. Here, the low-pass filter is a filter for removing carrier frequency components in pulse width modulation from the output pulse signals OUTP and OUTM. FIG. 1 shows an equivalent circuit of a low-pass filter and a speaker connected to the output terminals T21 and T22. Here, one end of the inductor L1 is connected to the output terminal T21, and the other end of the inductor L1 is connected to one end of the internal resistance R0 of the speaker. The output terminal T22 is connected to one end of an inductor L2, and the other end of the inductor L2 is connected to the other end of the internal resistance R0 of the speaker. A capacitor C0 is connected between the other end of the inductor L1 and the other end of the inductor L2. Further, a capacitor C1 is inserted between the other end of the inductor L1 and the ground line, and a capacitor C2 is inserted between the other end of the inductor L2 and the ground line.

  In the above configuration, during normal operation, the switches SWOS1 and SWOS2 are ON, and the enable signal EN is at H level. FIG. 2 exemplifies waveforms of the output pulse signals OUTP and OUTM of the class D amplifier during the normal operation. In this example, the power supply voltages of the output buffers 131 and 132 are 15V, and the power supply voltages of the differential amplifier 101 and the differential amplifier 111 are 3.3V.

  In normal operation, the input stage amplifier 100 amplifies the difference between the analog signal AIN (+) and the analog input signal AIN (−), and outputs forward and reverse two-phase signals SA and SB. The error integrator 110 integrates an error between the input signal SA and the signal SB of the normal / reverse two-phase and the output pulse signals OUTP and OUTM fed back through the feedback resistors R41 and R42, thereby integrating the normal / reverse two-phase integration. The value signals SC and SD are output.

  The pulse width modulation circuit 120 outputs the pulse signals P and M subjected to pulse width modulation by comparing the forward and reverse two-phase integrated value signals SC and SD with the triangular wave signal. Since the enable signal EN is at the H level, the output buffers 131 and 132 output the pulse signals P and M as output pulse signals OUTP and OUTM to the output terminals T21 and T22, respectively.

  Here, in the no-signal input state, the difference between the positive phase signal SA and the negative phase signal SB input to the error integrator 110 is zero. Further, when the difference between the integrated value signals SC and SD output from the error integrator 110 is zero, the pulse width modulation circuit 120 outputs the pulse signals P and M having a duty ratio of 50% and opposite phases to each other. It has a configuration. Accordingly, output pulse signals OUTP and OUTM having a duty ratio of 50% are output from the output buffers 131 and 132 and fed back to the error integrator 110 via the feedback resistors R41 and R42. In this case, the difference between the input signals SC and SD to the error integrator 110 is zero, and the difference between the average voltages of the feedback signals OUTP and OUTM is zero. The difference between the signals SC and SD is also zero. Therefore, in the no-signal input state, the duty ratio is 50%, and the signals OUTP and OUTM having opposite phases to each other continue to be output from the output buffers 131 and 132. At this time, as shown in FIG. 2A, since the duty ratio of the output pulse signal OUTP is 50%, the average value of the signal level of the output pulse signal OUTP is 7.5V. Further, since the duty ratio of the output pulse signal OUTM is also 50%, the average value thereof is 7.5V. Therefore, in the no-signal input state, 7.5V is applied to both input terminals of the speaker and the difference voltage is 0V, so that the speaker is not driven and no sound is output.

  Next, when the signal level of the analog input signal AIN (+) increases from the no-signal input state and the signal level of the analog input signal AIN (−) having the opposite polarity decreases, the period of the H level of the output pulse signal OUTP increases. At the same time, the L level period of the output pulse signal OUTM increases. That is, the duty ratio of the output pulse signal OUTP increases and the duty ratio of the output pulse signal OUTM decreases.

  In this case, as shown in FIG. 2B, the average value of the output pulse signal OUTP is, for example, 9.5 V, which is higher than 7.5 V at the time of no signal input, while the average value of the output pulse signal OUTM is no signal. For example, 5.5V, which is lower than 7.5V at the time of input. Therefore, the voltage difference between the input terminals of the speaker becomes, for example, 4 V (= 9.5 V−5.5 V), and the cone paper of the speaker is driven forward, for example.

  Conversely, when the signal level of the analog input signal AIN (+) decreases and the analog input signal AIN (−) increases from the no-signal input state, the output is reversed as shown in FIG. While the duty ratio of the pulse signal OUTP decreases, the duty ratio of the output pulse signal OUTM increases. As a result, the voltage difference between the input terminals of the speaker becomes, for example, −4V (= 5.5V−9.5V), and the cone paper of the speaker is driven backward, for example.

  As described above, in the normal amplification operation, the duty ratios of the output pulse signal OUTP and the output pulse signal OUTM are controlled in a complementary manner according to the signal level of the analog input signal AIN, so that a difference between the two terminals of the speaker is obtained. A speaker is driven by generating a voltage.

  In the class D amplifier shown in FIG. 1, if there is an input offset in the differential amplifier 101, an offset voltage is generated between the output signals SA and SB of the differential amplifier 101 when no signal is input, and the signals SA and SB Each average voltage becomes a different value from 1.65 V of the reference voltage (1/2 of the power supply voltage) set by the common-mode feedback circuit. This offset voltage is multiplied by the amplification factor (R41 / R31) of the negative feedback amplifier formed by the feedback resistors R41 and R42, the error integrator 110, the pulse width modulation circuit 120, and the output buffers 131 and 132, and output terminals T21 and Appears as a difference potential (offset voltage) between T22.

  Also, when there is an input offset in the differential amplifier 111, an offset voltage is generated between the signals SC and SD, and the average voltage of each of the signals SC and SD is 1.65V which is a reference voltage set by the common-mode feedback circuit. Will be different values.

  Further, when there is a difference in resistance value between the feedback resistors R41 and R42 or when there is a difference in resistance value between the input resistors R31 and R32, an offset voltage is generated between the output pulse signals OUTP and OUTM, and the output pulse The average voltages of the signals OUTP and OUTM are different from 7.5V. The reason will be described below.

  As shown in FIG. 2A, the output pulse signals OUTP and OUTM when no signal is input are complementary rectangular waves with a duty ratio of 50%. Since the power supply voltage of the drive circuit 130 is 15 V, there is no offset voltage in the differential amplifier, and the average of the output pulse signals OUTP and OUTM is ideal under ideal conditions where the resistance values on the positive phase side and the negative phase side are all equal. As described above, both voltages are 7.5V.

  On the other hand, in-phase feedback is performed so that the average voltage of each of the output signals SA and SB of the differential amplifier 101 having the power supply voltage of 3.3V matches the reference voltage VREF which is a half of the power supply voltage. Therefore, it is 1.65V. Accordingly, the voltage difference of 5.85 V between the average value of the output pulse signals OUTP and OUTM and the average value of the output signals SA and SB is the error integration between the feedback resistor R41 and the input resistor R31 and the feedback resistor R42 of the error integrator 110. Applied to the input resistance R32 of the device 110, respectively. As a result, a current corresponding to the sum of the resistance values of the feedback resistor R41 and the input resistor R31 flows from the output unit of the drive circuit 130 to the positive phase output unit of the differential amplifier 101 via the feedback resistor R41 and the input resistor R31. . Similarly, a current corresponding to the sum of the resistance values of the feedback resistor R42 and the input resistor R32 flows from the output unit of the drive circuit 130 to the negative phase output unit of the differential amplifier 101 via the feedback resistor R42 and the input resistor R32. .

  Here, consider a case where there is a difference between the resistance values of the feedback resistors R41 and R42. The voltages at the two inputs of the differential amplifier 111 are equal because feedback is being performed. Therefore, since the voltage applied to both ends of the input resistor R31 is equal to the voltage applied to both ends of the input resistor R32, the currents flowing through the resistors are equal.

  Since currents having the same values flow through the feedback resistors R41 and R42, respectively, a difference in voltage drop between the feedback resistors R41 and R42 occurs in the output portions of the output buffers 131 and 132. Accordingly, an offset voltage corresponding to the difference in resistance value between the feedback resistors R41 and R42 is generated between the output pulse signals OUTP and OUTM.

  Similarly, when there is a difference in resistance value between the input resistors R31 and R32, currents having a difference corresponding to the difference in resistance value flow in the feedback resistors R41 and R42, respectively, and an offset voltage due to the current flows. Appears between output pulse signals OUTP and OUTM.

  All of these offset voltages are combined and appear at the output terminals T21 and T22. When the speaker is driven by the offset voltages, a pop sound is generated when the power is turned off or muted.

  Therefore, the class D amplifier according to the present embodiment is provided with a comparator 140 and an offset control unit 141 for controlling the input offset of the differential amplifier 111, and an offset cancellation control circuit 160.

  FIG. 3 is a circuit diagram showing a configuration of the offset cancel control circuit 160 in the present embodiment. The offset cancel control circuit 160 is a control unit 161, a DC voltage generation circuit 170, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is simply referred to as a transistor hereinafter. .) 181, 182, and 183, and a discharge resistor RDIS.

  DC voltage generation circuit 170 is the same as the average voltage of output pulse signals OUTP and OUTM (complementary rectangular waves with a duty ratio of 50%) obtained from a class D amplifier in an ideal state with no offset in a no-signal input state. It is a circuit that outputs a DC voltage having a voltage value.

  In the illustrated example, the DC voltage generation circuit 170 includes P-channel transistors 171 and 175, N-channel transistors 172 to 174, and a resistor RR. Here, the P-channel transistor 171 is configured such that an output current IREF of a constant current source (not shown) is supplied to the source, and a signal SW_A is supplied to the gate. N-channel transistors 174, 172 and 173 have their sources grounded. The drains of N channel transistors 174 and 172 are connected to the drain of P channel transistor 171. The connection point between the drains of the P-channel transistor 171 and the N-channel transistors 174 and 172 is connected to the gates of the N-channel transistors 172 and 173. The P-channel transistor 175 has a source connected to the power supply PVDD that is the power supply of the output buffers 131 and 132 in FIG. 1, a drain connected to the drain of the N-channel transistor 173 via the resistor RR, and a signal to the gate. SW_A is given. A connection point between the drain of the N-channel transistor 173 and the resistor RR is an output terminal T30 of the DC voltage generation circuit 170.

  In this configuration, when the signal SW_A is at the H level, the P-channel transistors 171 and 175 are turned off. Further, since the N-channel transistor 174 is turned ON and the gate voltage of the N-channel transistor 173 becomes 0V, the N-channel transistor 173 is turned OFF. For this reason, the output impedance at the output terminal T30 of the DC voltage generation circuit 170 is high impedance. On the other hand, when signal SW_A is at the L level, P-channel transistors 171 and 175 are turned on and N-channel transistor 174 is turned off. In this case, N channel transistors 172 and 173 function as a current mirror, a current proportional to constant current IREF flows through N channel transistor 173, and the output voltage at output terminal T 30 of DC voltage generation circuit 170 is N channel transistor 173. A voltage obtained by multiplying the drain current by the resistance value of the resistor RR is subtracted from the power supply voltage PVDD.

  In the present embodiment, the output voltage of the DC voltage generation circuit 170 is the same voltage value as the average voltage of the output pulse signals OUTP and OUTM obtained from the ideal class D amplifier with no offset in the no-signal input state ( In the present embodiment, the resistance values of the constant current IREF and the resistor RR are determined so as to be 7.5 V which is a half of the power supply voltage 15 V).

  The N-channel transistor 181 is interposed between the output terminal T30 of the DC voltage generation circuit 170 and the output terminal T21 of the class D amplifier. The N-channel transistor 182 is interposed between the output terminal T30 of the DC voltage generation circuit 170 and the output terminal T22 of the class D amplifier. Signal SW_B is applied to the gates of these N-channel transistors 181 and 182. When this signal SW_B is at L level, N-channel transistors 181 and 182 are turned OFF, and output terminal T30 of DC voltage generation circuit 170 is disconnected from output terminals T21 and T22 of the class D amplifier. On the other hand, when signal SW_B is at the H level, N-channel transistors 181 and 182 are turned ON, and output terminal T30 of DC voltage generation circuit 170 is connected to output terminals T21 and T22 of the class D amplifier.

  The source of the N-channel transistor 183 is grounded, the drain is connected to the output terminal T30 of the DC voltage generation circuit 170 via the discharge resistor RDIS, and the discharge command signal DSICHHG is given to the gate. N-channel transistor 183 and discharging resistor RDIS are connected to active level (H level) discharge command signal DSICHHG in a state where output terminal T30 of DC voltage generating circuit 170 is connected to output terminals T21 and T22 of a class D amplifier. By being given, it functions as a discharge means for forming a discharge path between the output terminals T21 and T22 of the class D amplifier and the reference voltage line (ground line in this example).

  The control unit 161 outputs the signals SW_A and SW_B, the discharge command signal DISCHG, the enable signal EN, and the offset correction command signal CAN in accordance with a predetermined procedure in response to the trigger signal INIT generated when the class D amplifier is reset or activated. This is a circuit for causing the class D amplifier to perform an offset cancel operation and starting an amplification operation.

  FIG. 4 is a time chart showing a process in which the offset operation is performed and the amplification operation is started in the class D amplifier according to the present embodiment. In FIG. 4, OUT * indicates output signals OUTP and OUTM of the class D amplifier. When the trigger signal INIT is given, the controller 161 first performs control for output charging as shown in FIG. More specifically, the control unit 161 sets the signal SW_A to the L level and the signal SW_B to the H level. Further, the control unit 161 sets the enable signal EN to an inactive level (L level) and sets the output impedance of the output buffers 131 and 132 of the class D amplifier to high impedance. Further, the control unit 161 turns off the switches SWOS1 and SWOS2, cuts off the input signal from the outside, and puts the class D amplifier into the no-signal input state.

  When the signal SW_A becomes L level, the P-channel transistors 175 and 171 are turned ON and the N-channel transistor 174 is turned OFF, so that the output pulse signals OUTP and OUTM of the class D amplifier at the time of no signal input from the DC voltage generation circuit 170 A DC voltage corresponding to the ideal value of the average voltage (7.5 V, which is a half of the power supply voltage 15 V in this embodiment) is output. Further, when the signal SW_B becomes H level, the N-channel transistors 181 and 182 are turned ON. In this case, since the output buffers 131 and 132 are in the high impedance state, the output signals OUTP and OUTM of the class D amplifier rise following the DC voltage output from the DC voltage generation circuit 170. At this time, the capacitors C1 and C2 of the low-pass filter connected to the output terminals T21 and T22 are charged by the output signals OUTP and OUTM.

  Then, the output signals OUTP and OUTM of the class D amplifier are respectively supplied to the inverting input portion and the non-inverting input portion of the differential amplifier 111 in the error integrator 110 via the feedback resistors R41 and R42. As a result, the feedback state to the differential amplifier 111 is the same as the feedback state when the output pulse signals OUTP and OUTM, which are complementary rectangular waves with a duty ratio of 50%, are output from the class D amplifier when no signal is input. Be the same.

  Here, each end of the feedback resistors R41 and R42 is given a bias (OUTP = OUTM = 7.5V) similar to that at the time of actual no-signal input in which a feedback path is formed, but between the feedback resistors R41 and R42. If there is a difference in resistance value, a difference occurs in the value of the current flowing through each of the feedback resistors R41 and R42, and an offset voltage is generated between the inverting input portion and the non-inverting input portion of the differential amplifier 111.

  Specifically, since a voltage of 7.5−1.65 = 5.85 [V] is applied to the feedback resistor R41 and the input resistor R31, 1.65 + 5. A voltage of 85 × R31 / (R31 + R41) [V] is applied. Similarly, a voltage of 1.65 + 5.85 × R32 / (R32 + R42) [V] is applied to the positive phase input portion of the differential amplifier 111. As a result, a voltage difference (that is, an offset voltage) corresponding to variations in resistance values of the input resistors R31 and R32 and the feedback resistors R41 and R42 is generated at the input portion of the differential amplifier 111. This offset voltage is equal to the offset voltage generated at the time of no signal input in the normal operation in which the feedback path is formed.

  In addition, when there is an offset voltage between the output signals SA and SB of the differential amplifier 101, the offset voltage is input to the differential amplifier 111. Further, when there is an imbalance such as mutual conductance between the transistors of the differential transistor pair of the differential amplifier 111, an offset voltage due to the imbalance is generated at the input portion of the differential amplifier 111. In the process of output charging, the offset voltage due to such various factors appears at the input of the differential amplifier 111, and the offset voltage is amplified by the differential amplifier 111 and appears in the output signals SC and SD.

  When the output charging process is finished, the control unit 161 performs control for offset cancellation. Specifically, the control unit 161 outputs an offset correction command signal CAN to the offset control unit 141. Accordingly, the offset control unit 141 performs control for causing the differential amplifier 111 to generate an input offset voltage for eliminating the offset voltage currently generated between the output signals SC and SD of the differential amplifier 111. Specifically, the offset control unit 141 monitors the signal level of the output signal Comp of the comparator 140, and the differential amplifier 111 performs differential detection from the constant current source for offset adjustment until the signal level is inverted from the initial state. The operation of changing the current value flowing through one transistor of the transistor pair by a predetermined amount is repeated. As a result, the differential amplifier 111 is in a state where the offset voltage due to the various factors described above is canceled. Note that details of such offset cancellation control are disclosed in, for example, Japanese Patent Application Laid-Open No. H10-228707.

  Next, the control unit 161 controls the class D amplifier to start an amplifying operation after a stable period of a predetermined time length. Here, when the stable period starts, control unit 161 sets signal SW_A to H level to set the output impedance of DC voltage generation circuit 170 to high impedance in a state where N-channel transistors 181 and 182 are continuously turned on, and discharge command The signal DSICHHG is set to an active level (H level), and the N-channel transistor 183 is turned ON. As a result, after the charges charged in the capacitors C1 and C2 in the course of the output charge pass through the path formed by the inductor L1 and the N-channel transistor 181 and the path formed by the inductor L2 and the N-channel transistor 182, respectively, the discharge resistor RDIS And discharged to the ground line via the N-channel transistor 183. As a result, the output signals OUTP and OUTM are attenuated to 0V. In the present embodiment, the resistance value of the discharge resistor RDIS is determined so that the output signals OUTP and OUTM can be attenuated to 0 V in a stable period as short as possible without causing large ringing in the waveforms of the output signals OUTP and OUTM. ing.

When the stable period ends, the control unit 161 performs control for causing the class D amplifier to start an amplification operation. Specifically, the control unit 161 sets the discharge command signal DISCHG to an inactive level (L level) to turn off the N channel transistor 183, and sets the signal SW_B to L level to turn off the N channel transistors 181 and 182. DC voltage generation circuit 170 and discharging resistor RDIS are disconnected from output terminals T21 and T22. The control unit 161 turns on the switches SWOS1 and SWOS2 and sets the enable signal EN to the H level. As a result, in the class D amplifier, the input signal from the signal source SIG is supplied to the differential amplifier 101, the normal amplification operation is started, and the output pulse signal is output from the output buffers 131 and 132 to the output terminals T21 and T22. OUTP and OUTM are output.
The above is the details of the present embodiment.

  Next, the effect of this embodiment will be described in comparison with the prior art. FIG. 5 is a circuit diagram showing a configuration of an offset cancel control circuit 160A in a conventional class D amplifier. As shown in FIG. 5, the conventional offset cancel control circuit 160A does not have an equivalent to the N-channel transistor 183 and the discharge resistor RDIS in this embodiment, and the control unit 161A of the offset cancel control circuit 160A. Does not have a function of generating the discharge command signal DISCHG.

  FIG. 6 is a time chart showing a process of starting an amplification operation by performing offset cancellation in a conventional class D amplifier. As shown in FIG. 6, the control unit 161A of the conventional class D amplifier raises the signal SW_A to the H level at the start timing of the stable period, and simultaneously lowers the signal SW_B to the L level. Was disconnected from the output terminals T21 and T22.

  For this reason, in the stable period, the charge charged in the capacitor C1 flows into the non-inverting output portion of the differential amplifier 101 via the first path including the inductor L1, the feedback resistor R41, and the input resistor R31, and enters the capacitor C2. The charged electric charge flows into the inverting output portion of the differential amplifier 101 through the second path including the inductor L2, the feedback resistor R42, and the input resistor R32 (see FIG. 1). In this case, since the time constants of the first and second paths are large, charged charges may remain in the capacitors C1 and C2 even after the stabilization period ends. In such a state, when the amplification operation of the class D amplifier is started, a pop sound may be emitted from the speaker due to the influence of the charge remaining in the capacitors C1 and C2 at that time.

  On the other hand, according to the present embodiment, as described with reference to FIG. 4, the N-channel transistor 183 is turned on by setting the discharge command signal DSICHHG to the active level in the stable period after the offset cancellation, and the capacitance Charges of C1 and C2 are discharged through the discharge resistor RDIS and the N-channel transistor 183. For this reason, the charged charges of the capacitors C1 and C2 are discharged more rapidly than in the case of the prior art, and the charged charges of the capacitors C1 and C2 become sufficiently small within the stable period. Therefore, it is possible to prevent the pop sound from being generated when the class D amplifier starts the amplification operation.

  Although one embodiment of the present invention has been described above, other embodiments can be considered in addition to this. For example:

(1) In the above embodiment, a MOSFET (specifically, an N-channel transistor) is used as switch means for connecting or disconnecting the output terminal T30 of the DC voltage generation circuit 170 and the output terminals T21 and T22 of the class D amplifier to each other. 181 and 182) are used, but switches such as semiconductor switches or electromagnetic relays other than MOSFETs may be used. The same applies to the N-channel transistor 183 constituting the discharging means.

(2) In the above embodiment, a differential class D amplifier is given as an example of the power amplifier according to the present invention. However, the present invention may be applied to a single-ended class D amplifier. The scope of application of the present invention is not limited to the class D amplifier. The present invention is applicable to all power amplifiers having a configuration in which a feedback resistor is provided and a DC voltage is applied to the differential amplifier via the feedback resistor to perform an offset cancel operation.

DESCRIPTION OF SYMBOLS 100 ... Input stage amplifier, 110 ... Error integrator, 101, 111 ... Differential amplifier, 140 ... Comparator, 141 ... Offset control part, 120 ... Pulse width modulator, 130 ... Drive circuit, 131, 132 ... Output buffer, 160 ... offset cancel control circuit, T21, T22 ... output terminal, C0 to C2 ... capacitance, R0 ... speaker resistance, 161 ... control unit, 181 to 183, 172 to 174 ... N channel transistors, 171 and 175 ... P channel transistors, RDIS: discharging resistor, 170: DC voltage generating circuit, R41, R31, R42, R32: feedback resistors.

Claims (3)

A differential amplifier, and a feedback resistor interposed between an output terminal to which a load is connected and an input portion of the differential amplifier, and the differential signal is output from the output terminal by the feedback resistor. In the power amplifier that amplifies the input signal by the differential amplifier while negatively feeding back to the input portion of the amplifier, and generates an output signal for driving the load from the output terminal,
Offset control means for performing control to reduce the offset generated in the output signal of the differential amplifier by being given an offset correction command;
DC voltage generating means for outputting a DC voltage corresponding to the output signal of the power amplifier in a no-signal input state;
Discharging means for forming a discharge path between the output terminal of the power amplifier and a reference voltage line by being given a discharge command;
When the trigger signal is given, the DC voltage generating means is connected to the output terminal of the power amplifier, and the DC voltage output from the DC voltage generating means is connected to the input section of the differential amplifier via the feedback resistor. And a control means for giving an offset correction command to the offset control means, then giving a discharge command to the discharge means, and then causing the power amplifier to start an amplification operation. The power amplifier is a class D amplifier that outputs, from two output terminals, complementary rectangular pulses that are pulse width modulated by the output signal of the differential amplifier.
Two switches are respectively inserted between each of the two output terminals and the output terminal of the DC voltage generating means,
The discharging means is interposed between the output terminal of the DC voltage generating means and the reference voltage line,
The control means turns on the two switches, supplies the DC voltage output from the DC voltage generating means to the two output terminals of the power amplifier via the two switches, and the offset control means. An offset correction command is given to the discharge means, then a discharge command is given to the discharge means, and discharge is performed from the two output terminals to the reference voltage line via the two switches and the discharge means. The power amplifier according to claim 1.   3. The power amplifier according to claim 1, wherein the discharging means includes a field effect transistor and a resistor connected in series.

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