JPH08191247A - Pll circuit - Google Patents

Abstract

PURPOSE: To improve frequency pull-in capacity by controlling the oscillation of a voltage controlled oscillator circuit in accordance with a frequency difference and a phase difference between a demodulated clock obtained by multiplexing and a data string signal. CONSTITUTION: It is supposed that the oscillation frequency of the voltage controlled oscillator circuit 140 is sharply separated from objective frequency, e.g. the frequency fPCK of a demodulation clock PCK 152 is outside the frequency pull-in range of a PLL circuit. An output signal from a frequency detector 160 is controlled by a control signal UF 161 so as to increase the oscillation frequency of the circuit 140 or by a control signal DF 162 so as to reduce the oscillation frequency. When either one of the signals 161, 162 becomes logical level '1', a multiplexing means 120 multiplexes output signals 111, 112 from a phase comparator 110 with output signals 161, 162 from the detector 160. The oscillation of the circuit 140 is controlled in accordance with a frequency difference and a phase difference between the signals 161, 162 and a data string signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for matching a signal with a reference signal according to a phase level.

[0002]

2. Description of the Related Art PLL is an abbreviation for Phase Locked Loop.
This is a method of fitting the signal to the reference signal at the phase level.

The PLL is basically a closed loop of three elements, (1) phase comparator, (2) loop filter, and (3) VCO, which is a negative feedback loop of frequency and phase. There is.

The phase comparator is an error detector for detecting the phase difference between two signals. The loop filter removes high-frequency components and noise contained in the output of the phase comparator, and P
It has the function of holding the lock of LL. Two signals are added to the phase comparator, and only the difference between the two signals, that is, the error signal is output.

After that, it is passed through a loop filter and given to the VCO as a correction value. The frequency of the VCO is controlled by the correction value so as to approach the reference signal, and this operation is repeated little by little, and finally the VCO generates a clock whose phase is exactly in phase with the reference signal. This state is called lock.

Then, even if the VC is locked for some reason
Even if O is uncomfortable, continue to work again. According to such a PLL method, the PLL circuit is
A data string signal (for example, CD, M
In order to receive and demodulate a digital audio interface signal (DAI signal) used for exchanging data signals between digital audio devices such as D, DAT, and DCC, the phase of the received data string signal Generates a demodulation clock whose frequency is synchronized with.

An example of a conventional PLL circuit will be described below.
This will be described with reference to the drawings. FIG. 15 is a diagram showing an example of a conventional PLL circuit for generating a demodulated clock. In FIG. 15, reference numeral 140 is a voltage controlled oscillation circuit, which generates a signal having a frequency according to the applied voltage.

Reference numeral 1510 is a frequency divider circuit for dividing the output of the voltage controlled oscillator circuit 140, and the output of the frequency divider circuit 1510 is the demodulation clock 152. Reference numeral 110 denotes a phase comparator, which receives the data string signal 100 as a reference input, and uses a demodulation clock 152 which is an output of the frequency dividing circuit 1510 as a variable input to compare the phases of the two and compare the demodulation clock with the data string signal 100. The control signal D _P 112 is output when the phase of 152 is advanced, and conversely, the control signal U _P 111 is output when the phase of the demodulation clock 152 is delayed with respect to the data string signal 100.

Reference numeral 1500 denotes a charge pump, which operates to raise the control voltage 131 of the voltage controlled oscillator circuit 140 by the control signal _UP 111 output from the phase comparator 110, while the output of the phase comparator 110. The control signal D _P 112, which is a control signal, causes the control voltage 131 of the voltage controlled oscillator circuit 140 to decrease.

Reference numeral 130 denotes a loop filter, which smoothes a voltage change due to the operation of the charge pump 1500,
A DC voltage is applied as a control voltage 131 to the voltage controlled oscillator circuit 140.

The PLL circuit for generating a demodulated clock having the above-described configuration, when the phase of the demodulated clock 152 is delayed with respect to the data string signal 100, the phase comparator 110.
Control signal _UP 111 is output, which causes the charge pump 1500 to operate to increase the control voltage 131 of the voltage controlled oscillator circuit 140.

The loop filter 130 smoothes a rapid voltage rise change due to the operation of the charge pump 1500 and raises the control voltage 131 to the voltage controlled oscillator circuit 140, whereby the oscillation frequency of the voltage controlled oscillator circuit 140 is increased. It operates so that the phase of the demodulated clock 152 rises.

On the contrary, when the phase of the demodulation clock 152 leads the data string signal 100, the phase comparator 110
Control signal D _P 112 is output, which causes the charge pump 1500 to operate to lower the control voltage 131 of the voltage controlled oscillator circuit 140.

The loop filter 130 smoothes the abrupt voltage drop change due to the operation of the charge pump 1500 and drops the control voltage 131 to the voltage controlled oscillator circuit 140, whereby the oscillation frequency of the voltage controlled oscillator circuit 140 is reduced. It operates so that the phase of the demodulation clock 152 is delayed.

Thus, the phase difference between the demodulated clock 152 and the data string signal 100 operates so as to decrease, and when the phase difference disappears, the output DC voltage of the loop filter 130 becomes constant. This state is called a locked state, and a state in which the phase difference is changing in the process of being pulled into the locked state is called an unlocked state.

[0016]

However, the conventional PLL circuit as described above has the following problems.

IEC-958 standard "Digital audio inte
Received data string signal (self-synchronous transmission system signal) on which a clock is superimposed, such as a digital audio interface signal (DAI signal) specified by "rface"
To demodulate the data, it is necessary to extract a clock component from the data string signal and read the data with a demodulation clock generated based on the extracted clock component.

On the other hand, in order to read data, generally,
At twice the maximum repetition frequency of the data string signal,
Moreover, a demodulation clock having a predetermined phase relationship with the data string signal is required.

To this end, a data string signal is input to the phase comparator of the PLL circuit as a reference input, and the output signal of the voltage controlled oscillator circuit is input as a variable input to the maximum repetition frequency of the data string signal, which is 2 times. Input the demodulated clock divided by twice to control the voltage controlled oscillator circuit via the charge pump and the low pass filter by the output of the phase comparator, and generate the demodulated clock whose phase matches the data string signal. It is being generated by a voltage controlled oscillator circuit.

However, when the frequency of the data string signal, which is the reference input of the phase comparator, and the frequency of the demodulation clock, which is the variable input, are too far apart, the difference between the two frequencies is a predetermined range called the frequency pull-in range (capture range). If it is not within the range, the control of the voltage controlled oscillator circuit by the phase comparator will not be performed in the direction of decreasing the phase difference between the demodulated clock and the data string signal, and the PLL circuit will never enter the phase locked state. Had.

The above problems can be solved by expanding the frequency pull-in range (capture range) of the PLL circuit. However, in the conventional PLL circuit which controls only by the phase comparator, There was no one with sufficient frequency pull-in ability to satisfy.

The present invention solves the above-mentioned problems of the prior art by improving the frequency pull-in capability, expanding the substantial capture range as compared with the prior art, and providing data in a phase locked state. An object of the present invention is to provide a PLL circuit capable of increasing the frequency difference between the column signal and the demodulation clock.

[0023]

In order to achieve the above object, a PLL circuit according to a first aspect of the present invention uses a phase comparator to detect an input data string signal and an oscillation frequency of a voltage controlled oscillation circuit. The phase of the demodulated clock is compared with the generated demodulated clock, the oscillation of the voltage controlled oscillator circuit is controlled based on the detected phase difference, and the demodulated clock whose phase and frequency are synchronized with the data string signal is output. The PLL circuit outputs a signal according to the oscillation frequency of the voltage controlled oscillator circuit, based on the comparison clock different from the demodulation clock and the data string signal, which is generated based on the oscillation frequency of the voltage controlled oscillator circuit. And a multiplexing means for multiplexing the output signal of the phase comparator and the output signal of the frequency detector, the multiplexing means being obtained by the multiplexing. Wherein in accordance with the frequency difference and phase difference between the demodulation clock and the data stream signal, configured to control the oscillation of the voltage controlled oscillator circuit.

In the PLL circuit according to a second aspect of the present invention, the phase comparator compares the phase of the input data string signal with the phase of the demodulated clock generated based on the oscillation frequency of the voltage controlled oscillation circuit, and detects the detected phase. A PLL circuit that controls the oscillation of the voltage controlled oscillator circuit based on the phase difference and outputs the demodulated clock whose phase and frequency are synchronized with the data string signal is generated based on the oscillation frequency of the voltage controlled oscillator circuit. A frequency detector that outputs a signal according to the oscillation frequency of the voltage controlled oscillator circuit based on a comparison clock different from the demodulation clock and the data sequence signal, and the phases of the demodulation clock and the data sequence signal are The phase comparison is performed based on the determination by the lock detection means that detects the synchronization and determines that the data is demodulated and is in the lock state. And a multiplexing means for multiplexing the output signal of the frequency detector and the output signal of the frequency detector, and the multiplexing means does not perform the multiplexing when the lock detecting means determines the locked state. , The oscillation of the voltage controlled oscillation circuit is controlled by the output signal of the phase comparator according to the phase difference between the demodulated clock and the data string signal, and the lock detection means is arranged in a state opposite to the locked state. When it is determined to be in the unlocked state, the multiplexing is performed, and the oscillation of the voltage controlled oscillation circuit is controlled according to the frequency difference and the phase difference between the demodulated clock and the data string signal.

A PLL circuit according to a third aspect is the first aspect.
Alternatively, the frequency detector according to claim 2 divides an output signal of the voltage control oscillation circuit by a sync detection unit that detects a sync pattern of data that periodically appears in the data string signal,
A frequency dividing circuit for generating a clock having a cycle corresponding to a cycle in which a sync pattern appears in the data string signal, and an output signal of the frequency dividing circuit as a variable input and an output signal of the sync detecting means as a reference input, and both frequencies A frequency phase comparator for comparing phases, and the frequency phase comparator,
It is configured to output a signal according to a frequency difference and a phase difference between the output signal of the frequency dividing circuit and the output signal of the sync detecting means.

A PLL circuit according to a fourth aspect is the PLL circuit according to the first aspect.
Alternatively, the frequency detector according to claim 2 divides an output signal of the voltage control oscillation circuit by a sync detection unit that detects a sync pattern of data that periodically appears in the data string signal,
A frequency dividing circuit for generating a clock having a cycle corresponding to the cycle in which a sync pattern appears in the data string signal, and one of the output signal of the frequency dividing circuit and the output signal of the sync detecting means is a variable input and the other is a reference input. As a frequency phase comparator for comparing the frequency and phase of both, and a frequency pull-in determination means for determining whether the oscillation frequency of the voltage controlled oscillator circuit is within a predetermined range, the frequency phase comparator When the frequency pull-in determination means determines that the oscillation frequency of the voltage controlled oscillation circuit is out of a predetermined range, the output signal of the sync detection means is set to the variable input and the output signal of the frequency division circuit is set to the variable input. When the frequency pull-in determination means determines that the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range using the reference input, the frequency division is performed. A signal according to a frequency difference and a phase difference between the output signal of the frequency dividing circuit and the output signal of the sync detecting means, with the output signal of the path being the variable input and the output signal of the sync detecting means being the reference input. To output.

A PLL circuit according to a fifth aspect is the PLL circuit according to the first aspect.
Alternatively, the frequency detector according to claim 2 is provided with counting means for counting the inversion period of the data string signal by the comparison clock based on the output signal of the voltage controlled oscillation circuit, and the frequency detector is provided with the counting means. When the numerical value is larger than the expected count value in the maximum inversion period of the data string signal, a signal for lowering the oscillation frequency of the voltage controlled oscillation circuit is output.

A PLL circuit according to a sixth aspect is the PLL circuit according to the first aspect.
Alternatively, in the frequency detector according to claim 2, the counting value is reset by the counting means for counting the inversion period of the data string signal by the comparison clock based on the output signal of the voltage controlled oscillation circuit and the sync pattern by the sync detecting means. And a sync window signal generating means for generating a signal indicating the sync period, which is counted by the comparison clock, and the period from the count value reaching 0 to a predetermined value is defined as the sync period. The detector outputs a signal for lowering the oscillation frequency of the voltage controlled oscillation circuit when the count value by the counting means is larger than the expected count value in the maximum inversion period of the data string signal outside the sync period. To configure.

A PLL circuit according to a seventh aspect is the PLL circuit according to the first aspect.
Alternatively, the frequency detector according to claim 2 is provided with counting means for counting the inversion period of the data string signal by the comparison clock based on the output signal of the voltage controlled oscillation circuit, and the frequency detector is provided with the counting means. When the numerical value is smaller than the expected count value in the minimum inversion period of the data string signal, a signal for increasing the oscillation frequency of the voltage controlled oscillation circuit is output.

A PLL circuit according to an eighth aspect is the PLL circuit according to the third aspect.
Alternatively, the sync detecting means according to claim 4 is provided with a counting means for counting the inversion period of the data string signal by the comparison clock based on the output signal of the voltage controlled oscillation circuit, and the sync detecting means is provided by the counting means. When the numerical value is equal to or larger than the expected count value in the maximum inversion period of the data string signal, it is determined that the sync string is the sync pattern of the data string signal, and the sync pattern is detected.

A PLL circuit according to a ninth aspect is the PLL circuit according to the third aspect.
Alternatively, in the sync detecting means according to claim 4, the comparing clock based on the output signal of the voltage controlled oscillator circuit is used to count the inversion period of the data string signal, and the count value is reset when the sync is detected. And a mask signal generation unit for generating a signal indicating the sync detection stop period, which is a period from the count value of 0 to a predetermined value.
The sync detection means, the count value by the counting means,
When it is equal to or more than the expected count value in the maximum inversion period of the data string signal during the period other than the sync detection stop period, it is determined that the sync pattern is the sync pattern of the data string signal and the sync pattern is detected.

According to a tenth aspect of the present invention, the PLL circuit according to the fourth aspect detects whether or not the sync pattern of the data string signal is detected in a correct cycle by the frequency pull-in determination means, and the sync pattern is detected. If the oscillation is not performed in the correct cycle, it is determined that the oscillation frequency of the voltage controlled oscillator is out of the predetermined range. If the sync pattern is detected in the correct period, the oscillation of the voltage controlled oscillator is oscillated. It is configured to determine that the frequency is within a predetermined range.

According to a 11th aspect of the present invention, in the PLL circuit of the 11th aspect, the frequency pull-in determination means includes a counting means for counting the inversion period of the data string signal by the comparison clock based on the output signal of the voltage controlled oscillator circuit. The frequency pull-in determination means, when the count value by the counting means is larger than the expected count value in the maximum inversion period of the data string signal, the oscillation frequency of the voltage controlled oscillation circuit is higher than a predetermined frequency. If the count value by the counting means is smaller than the expected count value in the minimum inversion cycle of the data string signal, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is lower than a predetermined frequency, and the voltage The control oscillation circuit is configured to determine that the oscillation frequency is outside the predetermined range.

According to a twelfth aspect of the present invention, there is provided a PLL circuit in which the frequency pull-in determination means according to the fourth aspect includes counting means for counting the inversion period of the data string signal by the comparison clock based on the output signal of the voltage controlled oscillation circuit. , The count value is reset by the detection of the sync pattern by the sync detection means,
The frequency lock determination is provided by including a sync window signal generating unit that counts by the comparison lock, and sets a period from the count value of 0 to a predetermined value as a sync period to generate a signal indicating the sync period. The means determines that the oscillation frequency of the voltage controlled oscillation circuit is higher than a predetermined frequency when the count value by the counting means is larger than the expected count value in the maximum inversion period of the data string signal outside the sync period. However, when the count value by the counting means is smaller than the expected count value in the minimum inversion period of the data string signal outside the sync period, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is lower than a predetermined frequency. Then, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is outside the predetermined range.

According to a thirteenth aspect of the present invention, in the PLL circuit of the first aspect, when the control signal instructs the prohibition of the multiplexing based on an instruction of a predetermined control signal,
When the oscillation of the voltage controlled oscillation circuit is controlled only by the output signal of the phase comparator according to the phase difference between the demodulated clock and the data string signal, and the control signal instructs multiplexing,
A configuration is provided in which the output signal of the phase comparator and the output signal of the frequency detector are multiplexed and the oscillation of the voltage controlled oscillator circuit is controlled according to the frequency difference and phase difference between the demodulated clock and the data string signal. To do.

According to a fourteenth aspect of the present invention, in the PLL circuit of the second aspect, the multiplexing means according to the second aspect:
When the oscillation of the voltage controlled oscillation circuit is controlled only by the output signal of the phase comparator according to the phase difference between the demodulated clock and the data string signal, and the control signal instructs multiplexing,
Based on the determination result of the lock detection means, at the time of unlocking, the output signal of the phase comparator and the output signal of the frequency detector are multiplexed to control the oscillation of the voltage controlled oscillation circuit, and at the time of locking, the The output signal of the phase comparator controls the oscillation of the voltage controlled oscillator circuit.

[0037]

According to the structure of the present invention, the output signal of the frequency detector is multiplexed with the output signal of the phase comparator, and the output signal of the phase comparator loops according to the phase difference between the demodulated clock and the data string signal. And the loop output is controlled by the output signal of the frequency detector according to the frequency difference between the demodulated clock and the data string signal.

According to the second aspect of the invention, when it is determined that the unlock state is obtained based on the determination result of the lock detecting means, the output signal of the frequency detector is multiplexed with the output signal of the phase comparator. , Depending on the output signal of the phase comparator,
The loop is controlled according to the phase difference between the demodulated clock and the data string signal, and the output signal of the frequency detector controls the loop according to the frequency difference between the demodulated clock and the data string signal.

When it is determined that the lock state is established based on the determination result of the lock detecting means, the loop control is performed only by the output signal of the phase comparator in accordance with the phase difference between the demodulation clock and the data string signal. I do.

According to the third aspect of the invention, the frequency detector of the first aspect or the second aspect uses the sync detection result of the data string signal as a reference and a clock having a cycle corresponding to the cycle in which the sync pattern appears. The frequency difference and the phase difference are detected, and based on the detected difference, the loop is controlled according to the frequency difference between the demodulation clock and the data string signal.

According to the structure of claim 4, the frequency detector according to claim 1 or claim 2 determines whether or not the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range by the frequency pull-in determination means. If the oscillation frequency of the voltage controlled oscillator is out of the predetermined range, the sync detection result and the cycle corresponding to the cycle in which the sync pattern appears are referenced based on the clock in the cycle corresponding to the cycle in which the sync pattern appears in the data string signal. A frequency difference and a phase difference with the clock are detected, and based on the detected difference, the loop is controlled according to the frequency difference between the demodulated clock and the data string signal.

When the oscillation frequency of the voltage controlled oscillation circuit is within the predetermined range, the frequency difference and position between the sync detection result and the clock having the cycle corresponding to the cycle in which the sync pattern appears, with the sync detection result of the data string signal as a reference. The phase difference is detected, and based on this, the loop is controlled according to the frequency difference between the demodulation clock and the data string signal.

According to the structure of claim 5, the frequency detector according to claim 1 or 2 counts the inversion cycle of the data string signal with the clock whose output is the time base of the voltage controlled oscillation circuit, and counts the data string. When a count value larger than the expected count value C _MAX in the maximum inversion period of the signal appears, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is high, and based on this, the oscillation frequency of the voltage controlled oscillation circuit is lowered.

According to the structure of claim 6, the frequency detector according to claim 1 or 2 counts the inversion cycle of the data string signal with the clock whose output is the time-base of the voltage controlled oscillator circuit and counts the data string signal. When a count value larger than the expected count value C _MAX in the maximum inversion period of the signal appears outside the sync period, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is high, and based on this, the oscillation frequency of the voltage controlled oscillation circuit is determined. Lower.

According to the structure of claim 7, the frequency detector according to claim 1 or 2 counts the inversion cycle of the data string signal with the clock whose output is the time-based base of the voltage controlled oscillator circuit. When a _count value smaller than the expected count value C _MIN in the minimum inversion period of the signal appears, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is low, and based on this, the oscillation frequency of the voltage controlled oscillation circuit is increased.

According to the structure of claim 8, the sync detecting means according to claim 3 or 4 counts the inversion cycle of the data string signal with the clock whose output is the time base of the voltage controlled oscillation circuit to count the data string signal. When a count value larger than the expected count value C _MAX in the maximum inversion period of the signal appears, it is determined to be the sync pattern of the data string signal and detected, and the frequency detector corresponds to the sync detection result and the cycle in which the sync pattern appears. The frequency difference and the phase difference from the clock having the above cycle are detected, and based on the detected difference, the loop is controlled according to the frequency difference between the demodulation clock and the data string signal.

According to the structure of claim 9, the sync detecting means of claim 3 or 4 counts the inversion cycle of the data string signal with the clock whose output is the time base of the voltage controlled oscillation circuit, and the data string. When a count value larger than the expected count value C _MAX in the maximum inversion period of the signal appears outside the sync detection stop period, it is determined to be the sync pattern of the data string signal and detected, and the frequency detector detects the sync detection result. And the frequency difference and the phase difference with the clock of the cycle corresponding to the cycle in which the sync pattern appears, based on this,
The loop is controlled according to the frequency difference between the demodulation clock and the data string signal.

According to the structure of claim 10, the frequency pull-in determination means of claim 4 detects whether or not the sync detection of the data string signal is performed in the correct cycle, and the sync detection is not performed in the correct cycle. In this case, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is outside the predetermined range.

When the sync detection is performed in the correct cycle, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is within the predetermined range. Based on this, if the frequency detector has an oscillation frequency of the voltage controlled oscillation circuit outside the predetermined range,
The demodulated clock and the data string are detected by detecting the frequency difference and phase difference between the sync detection result and the clock having the cycle corresponding to the cycle in which the sync pattern appears, with the clock having the cycle corresponding to the cycle in which the sync pattern appears in the data string signal as a reference. The loop is controlled according to the frequency difference from the signal.

When the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range, the frequency difference and position between the sync detection result and the clock having the cycle corresponding to the cycle in which the sync pattern appears, with the sync detection result of the data string signal as a reference. By detecting the phase difference, the loop is controlled according to the frequency difference between the demodulated clock and the data string signal.

According to the eleventh aspect of the invention, the frequency pull-in determination means of the fourth aspect counts the inversion period of the data string signal with a clock whose time base is the output signal of the voltage controlled oscillation circuit, and detects the data string signal. When a count value larger than the expected count value C _MAX in the maximum inversion cycle is detected or a _count value smaller than the expected count value C _MIN in the minimum inversion cycle of the data string signal is detected, the voltage controlled oscillator circuit It is determined that the oscillation frequency is outside the predetermined range,
Expected count value C _MAX in the maximum inversion period of the data string signal
When the larger count value is not detected and the _count value smaller than the expected count value C _MIN in the minimum inversion interval of the data string signal is also not detected, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is within the predetermined range. .

Based on this, when the oscillation frequency of the voltage controlled oscillation circuit is out of the predetermined range, the frequency detector uses the clock of the cycle corresponding to the cycle in which the sync pattern appears in the data string signal as a reference to detect the sync detection result. By detecting a frequency difference and a phase difference from a clock having a period corresponding to the period in which the sync pattern appears, the loop is controlled according to the frequency difference between the demodulated clock and the data string signal.

When the oscillation frequency of the voltage controlled oscillation circuit is within the predetermined range, the frequency difference and position between the sync detection result and the clock having the cycle corresponding to the cycle in which the sync pattern appears, with the sync detection result of the data string signal as a reference. By detecting the phase difference, the loop is controlled according to the frequency difference between the demodulated clock and the data string signal.

According to the twelfth aspect of the invention, the frequency pull-in determination means of the fourth aspect counts the inversion period of the data string signal with a clock whose time base is the output signal of the voltage controlled oscillator circuit, and detects the data string signal. When a count value larger than the expected count value C _MAX in the maximum inversion cycle is detected outside the sync period, or when a _count value smaller than the expected count value C _MIN in the minimum inversion cycle of the data string signal is detected, It is determined that the oscillation frequency of the control oscillation circuit is out of the predetermined range, a count value larger than the expected count value C _MAX in the maximum inversion cycle of the data string signal is not detected except in the sync period, and the minimum inversion of the data string signal is detected. When the _count value smaller than the expected count value C _MIN in the interval is not detected, it is determined that the oscillation frequency of the voltage controlled oscillator circuit is within the predetermined range.

Based on this, when the oscillation frequency of the voltage controlled oscillation circuit is out of the predetermined range, the frequency detector uses the clock of the cycle corresponding to the cycle in which the sync pattern appears in the data string signal as a reference, and outputs the sync detection result. By detecting a frequency difference and a phase difference from a clock having a period corresponding to the period in which the sync pattern appears, the loop is controlled according to the frequency difference between the demodulated clock and the data string signal.

When the oscillation frequency of the voltage controlled oscillation circuit is within the predetermined range, the frequency difference and position between the sync detection result and the clock having the cycle corresponding to the cycle in which the sync pattern appears with the sync detection result of the data string signal as a reference. By detecting the phase difference, the loop is controlled according to the frequency difference between the demodulated clock and the data string signal.

According to the thirteenth aspect of the present invention, when the multiplexing means of the first aspect controls the loop by the control signal, the output signal of the phase comparator controls the loop according to the phase difference. When the control signal indicates multiplexing, the output signal of the frequency detector is multiplexed with the output signal of the phase comparator.

The output signal of the phase comparator controls the loop according to the phase difference, and the output signal of the frequency detector controls the loop according to the frequency difference. According to the structure of claim 14, when the control signal indicates the prohibition of multiplexing, the multiplexing means of claim 2 controls the loop according to the phase difference by the output signal of the phase comparator,
When the control signal indicates multiplexing, based on the determination result of the lock detection means, when it is determined that the unlocked state, the output signal of the frequency detector, the output signal of the phase comparator Multiplexing, the output signal of the phase comparator controls the loop according to the phase difference between the demodulated clock and the data string signal, and the output signal of the frequency detector
The loop is controlled according to the frequency difference between the demodulation clock and the data string signal.

If it is determined that the lock state is set,
The output signal of the phase comparator controls the loop according to the phase difference between the demodulated clock and the data string signal.

[0060]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to an embodiment of the present invention will be described below with reference to the drawings. The PLL circuit described below with reference to the drawings is used when a demodulated clock whose phase and frequency are synchronized with the data string signal is extracted from the data string signal on which the clock is superimposed.

In the present embodiment, for simplicity, for example, in FIG. 1, the comparison clock (SDTCK) 151 for counting the inversion period of the DAI signal is replaced with the demodulation clock (PCK).
It is assumed that the clock has the same frequency as 152.

That is, the frequency dividing circuit 150 divides the output signal 141 of the voltage controlled oscillator circuit 140 to generate a demodulation clock, which is used as the comparison clock 151 and the demodulation clock 1.
It is assumed that the output is 52. However, the present invention is not limited to this embodiment, and the comparison clock 151 that counts the inversion period of the DAI signal does not necessarily have to be a clock having the same frequency as the demodulation clock 152.

A PLL circuit as the first embodiment of the present invention will be described. FIG. 1 is a block diagram of the PLL circuit of the first embodiment. In FIG. 1, 100 is a data stream signal (RX) received through a digital audio interface (DAI), and 110 is a data stream signal 1.
00 and the demodulated clock (PCK) 152 are phase comparators 111, 112 for comparing the phases.
111 is a control signal ( _UP ) indicating a phase delay of the demodulation clock 152 at a logic level "1", 1
12 is a control signal (D _P ) indicating the phase advance of the demodulation clock 152 at the logic level “1”, 160 is the frequency dividing circuit 15
0 of the comparison clock 151 and the data string signal 1
00, a frequency detector that outputs a signal according to the oscillation frequency of the voltage controlled oscillation circuit 140, 161, 16
2 is an output of the frequency detector 160, 161 is a control signal (U _F ) indicating that the oscillation frequency f _VCO of the voltage controlled oscillation circuit 140 is low at the logic level “1”, 162 is
A control signal ( _DF ) indicating that the oscillation frequency f _VCO of the voltage controlled oscillation circuit 140 is high at the logic level "1", 120
Is the frequency detector 16 in the output signal of the phase comparator 110.
0 is a multiplexing means for multiplexing the output signal, 121 is a phase comparison output, 130 is a loop filter for smoothing the voltage change of the phase comparison output 121 and applying a control voltage to the voltage controlled oscillation circuit 140, 140 is a voltage It is a controlled oscillator circuit.

A detailed operation of the PLL circuit configured as described above will be described below. The PLL circuit shown in FIG. 1 has a frequency f _PCK of the demodulation clock (PCK) 152.
Is, for example, outside the frequency pull-in range (capture range) of the PLL circuit, the voltage-controlled oscillation circuit 140
The oscillation frequency f _VCO is if you are far from a target frequency, the output signal of the frequency detector 160, a control signal for controlling so as to increase the oscillation frequency of the voltage controlled oscillator circuit 140 (U _F) 161, Alternatively, either one of the control signal ( _DF ) 162 for controlling the oscillation frequency of the voltage controlled oscillator circuit 140 to be lowered becomes the logic level "1", and the multiplexing means 120 causes the phase comparator 110 to operate based on this. Output signal 111, 112 of the frequency detector 16
The output signals 161 and 162 of 0 are multiplexed and the phase comparison output 121 is output.

The above operation is performed until the frequency f _PCK of the demodulated clock 152 is within the frequency pull-in range (capture range) of the PLL circuit and is reflected in the output signals 161 and 162 of the frequency detector 160 (that is, frequency detection). It repeats until both output signals 161 and 162 of the device 160 are constantly at the logic level "0".

Thus, the frequency f of the demodulation clock 152
_{If the PCK} is within the frequency pull-in range (capture range) of the PLL circuit, the operation thereafter is exactly the same as that of the conventional PLL circuit for generating a demodulated clock.

That is, the phase difference between the demodulation clock 152 and the data string signal 100 is reduced, and when the phase difference disappears, the output DC voltage 1 of the loop filter 130 is reduced.
31 becomes constant, and the demodulation clock 152 at this point is
The frequency is twice the maximum repetition frequency f _MAX of the data sequence signal 100, and the data sequence signal 100 becomes stable in a predetermined phase relationship.

A PLL circuit as a second embodiment of the present invention will be described. FIG. 2 is a block diagram of the PLL circuit of the second embodiment. In FIG. 2, 100 is a data stream signal (RX) received through a digital audio interface (DAI), and 110 is a data stream signal 1.
00 and the demodulated clock (PCK) 152 are phase comparators 111, 112 for comparing the phases.
111 is a control signal ( _UP ) indicating a phase delay of the demodulation clock 152 at a logic level "1", 1
12 is a control signal (D _P ) indicating the phase advance of the demodulation clock 152 at the logic level “1”, 160 is the frequency dividing circuit 15
0 of the comparison clock 151 and the data string signal 1
00, a frequency detector that outputs a signal according to the oscillation frequency of the voltage controlled oscillation circuit 140, 161, 16
2 is an output of the frequency detector 160, 161 is a control signal (U _F ) indicating that the oscillation frequency f _VCO of the voltage controlled oscillation circuit 140 is low at the logic level “1”, 162 is
A control signal ( _DF ) indicating that the oscillation frequency f _VCO of the voltage controlled oscillation circuit 140 is high at the logic level "1", 200
Is a lock detecting means for determining whether or not the phase of the demodulation clock 152 and the phase of the data string signal 100 are synchronized and data demodulation is possible, and 210 is a lock detecting means 2.
When it is determined by 00 that it is in the unlocked state, the output signals 111 and 1112 of the phase comparator 110
The output signals 161 and 162 of the frequency detector 160 are multiplexed to generate the phase comparison output 121, and the output signal 11 of the phase comparator 110 when it is determined to be in the locked state.
1, 112, the multiplexing means for generating the phase comparison output 121; 121, the phase comparison output; 130, the voltage change of the phase comparison output 121;
A loop filter for applying a control voltage to 0, 140 is a voltage controlled oscillator circuit.

The detailed operation of the PLL circuit thus configured will be described below. The PLL circuit shown in FIG. 2 has a frequency f _PCK of the demodulation clock (PCK) 152.
Is, for example, outside the frequency pull-in range (capture range) of the PLL circuit, the voltage-controlled oscillation circuit 140
The oscillation frequency f _VCO is if you are far from a target frequency, the output signal of the frequency detector 160, a control signal for controlling so as to increase the oscillation frequency of the voltage controlled oscillator circuit 140 (U _F) 161, Alternatively, one of the control signals ( _DF ) 162 for controlling the oscillation frequency of the voltage controlled oscillator circuit 140 to be lowered becomes the logic level "1".

In this case, the lock detecting means 200
Determines that data cannot be demodulated, and based on this, the multiplexing means 210 outputs the output signals 111 and 112 of the phase comparator 110 to the output signal 16 of the frequency detector 160.
1, 162 are multiplexed and the phase comparison output 121 is output.

The above operation is performed until the frequency f _PCK of the demodulated clock 152 is within the frequency pull-in range (capture range) of the PLL circuit and is reflected in the output signals 161 and 162 of the frequency detector 160 (that is, frequency detection). Until both output signals 161 and 162 of the container are constantly at the logic level "0").

Thus, the frequency f of the demodulation clock 152
_{If the PCK} is within the frequency pull-in range (capture range) of the PLL circuit, the operation thereafter is exactly the same as that of the conventional PLL circuit for generating a demodulated clock.

That is, when the phase difference between the demodulated clock 152 and the data string signal 100 is reduced, and when the phase difference disappears, the output DC voltage 1 of the loop filter 130 is reduced.
31 becomes constant, and the demodulation clock 152 at this point is
The frequency is twice the maximum repetition frequency f _MAX of the data sequence signal 100, and the data sequence signal 100 becomes stable in a predetermined phase relationship.

At this point, the lock detecting means 200
Determines that the data can be demodulated, and the multiplexing means 21
0 controls to generate the phase comparison output 121 only from the output signals 111 and 112 of the phase comparator 110.

As a result, when the PLL circuit is locked, the outputs 161 and 162 of the frequency detector 160 are not reflected on the phase comparison output 121, and noise may be added to the received data string signal 100, for example. , Frequency detector 16
Even if 0 malfunctions, the PLL operates stably.

A frequency detector as the third embodiment of the present invention will be described. FIG. 3 is a configuration diagram of the frequency detector 160 in the PLL circuits of the first and second embodiments. In FIG. 3, 100 is a digital audio
It is a data string signal (RX) received through an interface (DAI), and will be described as a digital audio interface signal (DAI signal) conforming to the IEC-958 standard in this embodiment.

Reference numeral 151 is a comparison clock, 300 is a sync detecting means for detecting a sync pattern periodically appearing in the received data string signal 100, 301 is a sync detection result signal (R3T), and 310 is a frequency division of the comparison clock 151. Then, a frequency dividing circuit for generating a clock having a cycle corresponding to the cycle in which a sync pattern appears in the data string signal 100, 311 is an output signal (2Fs) of the frequency dividing circuit 310, and 320 is a sync based on the sync detection result signal 301. It is a frequency phase comparator that compares the detection result signal 301 and 2Fs 311 to detect the frequency difference and the phase difference.

The frequency detector 160 configured as described above
The detailed operation of the above will be described below. As shown in FIG. 16, the DAI signal (data string signal) 100 is obtained by bi-phase encoding digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and
Further, fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data, and the other channel is the R channel of audio data. A 2-channel signal has a frame composed of three types of preambles “B”, “M”, and “W”, and is transmitted with 192 frames as one block.

As described above, in the DAI signal 100, the preamble portion appears periodically (1/2 fs), and since 3T is used only in this preamble portion, the sync (preamble) is detected by detecting 3T. Can be detected.

The sync detecting means 300 detects the DAI signal 10
3T is detected from the relationship between 0 and the comparison clock 151 and is output as the sync detection result signal 301. Further, the frequency dividing circuit 310 uses the comparison clock 151 (in this embodiment, the comparison clock = the demodulation clock, so the frequency of the comparison clock 151 is 128 times the sampling frequency).
Is divided by 64 and a clock (2Fs) having a cycle corresponding to the cycle in which the sync (preamble) appears in the DAI signal 100
Generate

The frequency phase comparator 320 has a reference input (R
ef. ) And the signal applied to the variable input (Var.) Are compared in frequency and phase, and an output signal corresponding to the frequency difference and the phase difference is generated.

In the case of the present embodiment, the sync detection result signal 301 is used as a reference and the sync detection result signal 301 and the output signal (2Fs) 311 of the frequency dividing circuit 310 are compared in frequency and phase, and the frequency dividing circuit 310 is compared. Output signal (2Fs) 31
When it is determined that the frequency of 1 is high or the phase is advanced, it indicates that the frequency f _PCK of the demodulation clock 152 is high, and a control signal (control signal for controlling the oscillation frequency of the voltage controlled oscillation circuit 140 to be lowered ( The logic level "1" is output to D _F ) 162, and the control signal (U _F ) 161 is set to the logic level "0".

In addition, the output signal (2F
s) When it is determined that the frequency of 311 is low or the phase is delayed, it indicates that the frequency f _PCK of the demodulation clock 152 is low, and control is performed to increase the oscillation frequency of the voltage controlled oscillation circuit 140. Signal (U _F ) 161
Output a logic level "1" to the control signal ( _DF ) 162
Is a logic level "0".

A frequency detector as a fourth embodiment of the present invention will be described. FIG. 4 is a configuration diagram of the frequency detector 160 in the PLL circuits of the first and second embodiments. In FIG. 4, 100 is a digital audio
A data string signal (RX) received through the interface (DAI), 151 is a comparison clock, 300 is a sync detecting means for detecting a sync pattern periodically appearing in the received data string signal 100, and 301 is a sync detection result signal ( R3T) and 310 are frequency dividing circuits for dividing the comparison clock 151 to generate a clock having a cycle corresponding to the cycle in which the sync pattern appears in the data string signal 100.
Is an output signal (2Fs) of the frequency dividing circuit 310, 400 is a frequency pull-in determination means for determining whether the oscillation frequency of the voltage controlled oscillator circuit 140 is within a predetermined range, 401
Is an output signal of the frequency pull-in determination means indicating that the oscillation frequency of the voltage controlled oscillator 140 is out of the predetermined range at the logic level "1", and 410 is the select signal 401.
A selector 411 that selectively outputs 2Fs 311 to 411 when the logic level is “1” and selectively outputs R3T301 to 411 when the logic level is “0” is a selector 41.
When the select signal 401 is at the logic level “1”, the R3T301 is selectively output to 421, and when the select signal 401 is at the logic level “0”, 2Fs311 is set to 42.
1 is a selector for selectively outputting 1; 320 is a reference input 411
Is a reference, and the reference input 411 and the variable input 421 are compared to detect a frequency difference and a phase difference.

The frequency detector 160 configured as described above
The detailed operation of the above will be described below. As shown in FIG. 16, the DAI signal (data string signal) 100 is obtained by bi-phase encoding digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs,
Further, fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT, in which one channel is the L channel of audio data and the other channel is the R channel of audio data. A 2-channel signal has a frame composed of three types of preambles “B”, “M”, and “W”, and is transmitted with 192 frames as one block.

As described above, in the DAI signal 100, the preamble part appears periodically (1/2 fs), and 3T is used only in this preamble part. Therefore, by detecting 3T, the sync (preamble) is detected. can do.

The sync detecting means 300 uses the DAI signal 10
3T is detected from the relationship between 0 and the comparison clock 151 and is output as the sync detection result signal 301. Further, the frequency divider circuit 310 outputs the comparison clock 151 (128 fs) to 64
Frequency division is performed to generate a clock having a cycle corresponding to the cycle in which the sync (preamble) appears in the DAI signal.

The frequency pull-in determination means 400 uses the DAI
From the relationship between the signal 100 and the comparison clock 151, it is determined whether the oscillation frequency of the voltage controlled oscillator circuit 140 is within the predetermined range. If it is outside the predetermined range, the logic level "1" is within the predetermined range. In that case, the logic level “0” is output to the signal 401.

As a result, the selector 410 outputs the output signal (2Fs) of the frequency divider circuit 310 when the select signal 401 is at the logic level "1", that is, when the oscillation frequency of the voltage controlled oscillator circuit 140 is outside the predetermined range. 311 to 41
1 and selectively output the select signal 401 to the logical level “0”, that is, when the oscillation frequency of the voltage controlled oscillator 140 is within a predetermined range, the sync detection result signal (R3T) 301 is selectively output to 411. .

Further, the selector 420 outputs the select signal 4
When 01 is the logic level "1", that is, when the oscillation frequency of the voltage controlled oscillator circuit 140 is outside the predetermined range, the sync detection result signal (R3T) 301 is selectively output to 421, and the select signal 401 is the logic level "1". In the case of 0 ″, that is, when the oscillation frequency of the voltage controlled oscillator circuit 140 is within a predetermined range, the output signal (2Fs) 3 of the frequency divider circuit 310
11 is selectively output to 421.

Therefore, the frequency and phase comparison is performed to compare the frequency and phase of the signal applied to the reference input (Ref.) And the signal applied to the variable input (Var.) And generate an output signal corresponding to the frequency difference and the phase difference. When the oscillation frequency of the voltage controlled oscillation circuit 140 is outside the predetermined range, the device 320
When the frequency and phase of R3T and 2Fs are compared based on 2Fs and it is determined that the frequency of R3T is high or the phase is advanced, it indicates that the frequency f _PCK of the demodulated clock 152 is high, Voltage controlled oscillator circuit 140
Signal ( _DF ) 1 to control the oscillation frequency of the
The logic level "1" is output to 62, and the control signal (U _F ) 1
61 is a logic level "0".

The frequency of R3T is low, or
If it is determined that the phase is delayed, it indicates that the frequency f _PCK of the demodulation clock 152 is low, and the control signal (U _F ) 161 for controlling to increase the oscillation frequency of the voltage controlled oscillation circuit 140 has the logical level “ 1 "is output and the control signal ( _DF ) 162 is set to the logic level" 0 ".

On the other hand, when the oscillation frequency of the voltage controlled oscillation circuit 140 is within the predetermined range, the frequency phase comparator 320
Compares the frequency and phase of R3T and 2Fs with R3T as a reference, and when it is determined that the frequency of 2Fs is high or the phase is advanced, the demodulation clock 152
_Shows that the frequency f _PCK of the voltage control oscillator circuit 1 is high.
A control signal (D that controls to lower the oscillation frequency of 40
_F ) outputs a logic level "1" to 162 and outputs a control signal (U
_F ) 161 has a logic level "0".

The frequency of 2Fs is low, or
If it is determined that the phase is delayed, it indicates that the frequency f _PCK of the demodulation clock 152 is low, and the control signal (U _F ) 161 for controlling to increase the oscillation frequency of the voltage controlled oscillation circuit 140 has the logical level “ 1 "is output and the control signal ( _DF ) 162 is set to the logic level" 0 ".

A frequency detector as the fifth embodiment of the present invention will be described. FIG. 5 is a block diagram of the frequency detector 160 in the PLL circuits of the first and second embodiments. In FIG. 5, 100 is a digital audio
The data string signal (RX) received through the interface (DAI), 151 is the comparison clock, and 500 is the received data string signal 10 according to the comparison clock 151.
Counting means for counting the inversion period of 0, 501 is count value data, and 510 is a voltage when a count value larger than the expected count value C _MAX of the maximum inversion cycle (3T) of the received data string signal 100 appears. C _MAX <detection means for determining that the oscillation frequency of the control oscillation circuit 140 is high.

The frequency detector 160 configured as described above
The detailed operation of the above will be described below. As shown in FIG. 16, the DAI signal (data string signal) 100 is obtained by bi-phase encoding digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data, and the other channel is the R channel of audio data. A 2-channel signal has a frame composed of three types of preambles “B”, “M”, and “W”, and is transmitted with 192 frames as one block.

When the inversion period of the DAI signal 100 is counted by the comparison clock 151, the count value 501 by the counting means 500 becomes maximum at 3T of the DAI signal 100, and at 1T, as shown in FIG. The count value 501 by the counting means 500 becomes the minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases. However, when the PLL is locked, the comparison clock 151 is generated. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value when the PLL is in the locked state is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100. When the demodulation clock 152 is selected as the comparison clock 151, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) Similarly, the minimum count value when the PLL is in the locked state is uniquely determined, and this is determined in the minimum inversion period of the DAI signal 100. It is defined as the expected count value C _MIN .

The demodulation clock 152 is used as the comparison clock 151.
If you select C_MIN Is 1. (See FIG. 16 and FIG.
Timing of DAI signal 100 and demodulated clock 152 shown
See the drawing. ) C_MAX <Detection means is DAI signal 100
Expected count value C in the maximum inversion period of _MAX Greater than
Is displayed, the oscillation frequency of the voltage controlled oscillation circuit 140
Is determined to be high, and the oscillation frequency of the voltage controlled oscillation circuit 140
Control signal (D_F ) 162 to the logical level
Output bell "1".

A frequency detector as a sixth embodiment of the present invention will be described. FIG. 6 is a configuration diagram of the frequency detector 160 in the PLL circuits of the first and second embodiments. In FIG. 6, 100 is a digital audio
The data string signal (RX) received through the interface (DAI), 151 is the comparison clock, and 500 is the received data string signal 10 according to the comparison clock 151.
Counting means for counting the inversion period of 0, 501 is count value data, 300 is a sync detecting means for detecting a sync pattern periodically appearing in the received data string signal 100, 30
1 is a sync detection result signal (R3T), and 600 is a count value that is reset immediately when the sync is detected by the sync detection means 300 and is counted by the comparison clock 151, and the count value becomes a predetermined value from 0. Up to a sync window signal generation means for generating a signal indicating that it is a sync period, 601 is a sync window signal, and 610 is an expected count value C of the maximum inversion period (3T) of the received data string signal 100. _{MA X} larger count value, when appearing on the non-sync period, a C _MAX <detecting means determines that the higher the oscillation frequency of the voltage controlled oscillator 140.

The frequency detector 160 configured as described above
The detailed operation of the above will be described below. As shown in FIG. 16, the DAI signal (data string signal) 100 is obtained by bi-phase encoding digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is an L channel of audio data and the other channel is an R channel of audio data.

A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and 192 frames are transmitted as one block.
Now, when the inversion period of the DAI signal 100 described above is counted by the comparison clock 151, as shown in FIG.
At 3T of the AI signal 100, the count value 501 by the counting means 500 becomes maximum, and at 1T, the count value 501 by the counting means 500 becomes minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases. However, when the PLL is locked, the comparison clock 151 is generated. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value in the locked state of the PLL is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100.

The demodulation clock 152 is used as the comparison clock 151.
If is selected, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) Similarly, the minimum count value when the PLL is in the locked state is uniquely determined, and this is determined in the minimum inversion period of the DAI signal 100. It is defined as the expected count value C _MIN .

The demodulation clock 152 is used as the comparison clock 151.
If C _MIN is selected, C _MIN is 1. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) 300 is a sync detecting means, but as described in the third embodiment, in the DAI signal 100, the preamble part is periodic ( 1/2 fs) and 3T only in this preamble part
, The sync (preamble) can be detected by detecting 3T.

The sync detecting means 300 detects the DAI signal 10
3T is detected from the relationship between 0 and the comparison clock 151,
The sync detection result signal 301 is output. The sync window signal generation means 600 generates a section signal indicating the preamble period (sync period) of the DAI signal 100 based on the sync detection result 301 and the comparison clock 151, and as the sync window signal 601, C _MAX <detection. Supply to the means.

C_MAX <Detection means is for the DAI signal 100
Expected count value C in the maximum inversion period _MAX Greater than
Is less than the sync period indicated by the sync window signal 601.
When it appears outside, the oscillation frequency of the voltage-controlled oscillation circuit 140
The oscillation frequency of the voltage controlled oscillation circuit 140 is determined to be high.
Control signal (D_F ) Logic to 162
Outputs level "1".

A frequency detector as the seventh embodiment of the present invention will be described. FIG. 7 is a configuration diagram of the frequency detector 160 in the PLL circuits of the first and second embodiments. In FIG. 7, 100 is a digital audio
The data string signal (RX) received through the interface (DAI), 151 is the comparison clock, and 500 is the received data string signal 10 according to the comparison clock 151.
Counting means for counting the inversion period of 0, 501 is count value data, 700 is a voltage when a count value smaller than the expected count value C _MIN of the minimum inversion cycle (1T) of the received data string signal 100 appears. C _MIN > detection means for determining that the oscillation frequency of the control oscillation circuit 140 is low.

The frequency detector 160 configured as above
The detailed operation of the above will be described below. As shown in FIG. 16, the DAI signal (data string signal) 100 is obtained by bi-phase encoding digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data, and the other channel is the R channel of audio data.

A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and 192 frames are transmitted as one block.
Now, when the inversion period of the DAI signal 100 described above is counted by the comparison clock 151, as shown in FIG.
At 3T of the AI signal 100, the count value 501 by the counting means 500 becomes maximum, and at 1T, the count value 501 by the counting means 500 becomes minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases. However, when the PLL is locked, the comparison clock 151 is generated. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value when the PLL is locked is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100.

The demodulation clock 152 is used as the comparison clock 151.
If is selected, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) Similarly, the minimum count value when the PLL is in the locked state is uniquely determined, and this is determined in the minimum inversion period of the DAI signal 100. It is defined as the expected count value C _MIN .

The demodulation clock 152 is used as the comparison clock 151.
If you select C_MIN Is 1. (See FIG. 16 and FIG.
Timing of DAI signal 100 and demodulated clock 152 shown
See the drawing. ) C_MIN > The detection means is the minimum inversion period of the DAI signal 100.
Expected count value in C _MIN When a smaller value appears
It is determined that the oscillation frequency of the voltage controlled oscillator circuit 140 is low.
Then, increase the oscillation frequency of the voltage controlled oscillation circuit 140.
Control signal to control (D_F ) Set the logic level “1” to 162
Output.

A sync detecting means as an eighth embodiment of the present invention will be described. FIG. 8 is a block diagram of the sync detecting means 300 in the frequency detector 160 of the third and fourth embodiments. In FIG. 8, 100 is a data string signal (RX) received through a digital audio interface (DAI), 151 is a comparison clock, 8
00 is counting means for counting the inversion period of the received data string signal 100 by the comparison clock 151, 801 is count value data, and 810 is the received data string signal 10.
When the count value equal to or larger than the expected count value C _MAX of the maximum inversion period (3T) of 0 appears, C _MAX ≦ detection means for determining the sync pattern of the data string signal 100.

The sync detecting means 30 configured in this way
The detailed operation of 0 will be described below. As shown in FIG. 16, the DAI signal (data string signal) 100 is obtained by bi-phase encoding digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data, and the other channel is the R channel of audio data.

A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and 192 frames are transmitted as one block.
Thus, in the DAI signal 100, the preamble portion appears periodically (1/2 fs), and 3T is used only in this preamble portion. Therefore, by detecting 3T,
The sync (preamble) can be detected.

When the inversion period of the DAI signal 100 is counted by the comparison clock 151, the count value 801 by the counting means 800 becomes maximum at 3T of the DAI signal 100, and at 1T as shown in FIG. The count value 801 by the counting means 800 becomes the minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases. However, when the PLL is locked, the comparison clock 151 is generated. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value when the PLL is in the locked state is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100.

The demodulation clock 152 is used as the comparison clock 151.
If is selected, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) When the PLL is in the locked state, C _MAX (= 3) appears only in 3T, that is, only in the preamble part.

Similarly, when the PLL is in the locked state, the minimum
The count value is uniquely determined.
Expected count value C in the minimum inversion period_MIN Is defined. ratio
When the demodulation clock 152 is selected as the comparison clock 151,
C_MIN Is 1. (The DAI signal shown in FIG. 16 and FIG.
See the timing diagram of No. 100 and demodulation clock 152. ) C_MAX ≦ Detection means is the maximum inversion period of the DAI signal 100
Expected count value in C _MAX If the above value appears, D
It is a sync pattern (preamble) of the AI signal 100.
The sync detection result signal (R3T) 301
Outputs level "1".

A sync detecting means as a ninth embodiment of the present invention will be described. FIG. 9 is a block diagram of the sync detecting means 300 in the frequency detector 160 of the third and fourth embodiments. In FIG. 9, 100 is a data string signal (RX) received through a digital audio interface (DAI), 151 is a comparison clock, 8
00 is counting means for counting the inversion period of the received data string signal 100 by the comparison clock 151, 801 is count value data, and 900 is the count value reset immediately when the sync is detected, and by the comparison clock 151. Mask signal generation means for counting and generating a signal indicating a sync detection stop period for the period from the count value reaching a predetermined value from 0, 901 is a mask signal, 910
Is the maximum inversion period (3
Expected measurement value C _{MA X} or more counts of T) is, if they appear in addition to the sync detection stop period, a C _MAX ≦ detecting means determines that Shinkupatan data string signal 100.

The sync detecting means 30 configured as described above
The detailed operation of 0 will be described below. As shown in FIG. 16, the DAI signal (data string signal) 100 is obtained by bi-phase encoding digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data and the other channel is the R channel of audio data.

A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and 192 frames are transmitted as one block.
Thus, in the DAI signal 100, the preamble portion appears periodically (1/2 fs), and 3T is used only in this preamble portion. Therefore, by detecting 3T,
The sync (preamble) can be detected.

When the inversion period of the DAI signal 100 is counted by the comparison clock 151, the count value 801 by the counting means 800 becomes maximum at 3T of the DAI signal 100, and at 1T, as shown in FIG. The count value 801 by the counting means 800 becomes the minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases. However, when the PLL is locked, the comparison clock 151 is generated. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value when the PLL is in the locked state is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100.

The demodulation clock 152 is used as the comparison clock 151.
If is selected, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) When the PLL is in the locked state, C _MAX (= 3) appears only in 3T, that is, only in the preamble part.

Similarly, when the PLL is in the locked state, the minimum
The count value is uniquely determined.
Expected count value C in the minimum inversion period_MIN Is defined. ratio
When the demodulation clock 152 is selected as the comparison clock 151,
C_MIN Is 1. (The DAI signal shown in FIG. 16 and FIG.
See the timing diagram of No. 100 and demodulation clock 152. ) The mask signal generation means 900 uses the sync detection result 301.
And the sync detection stop period based on the comparison clock 151
C as a section signal (mask signal) 901 indicating _MAX ≤
Supply to the detection means.

C_MAX ≦ Detection means is the DAI signal 100
Expected count value C in the maximum inversion period _MAX The above value is
The sync detection stop period indicated by the sync signal 901.
Sync pattern of DAI signal 100 when it appears outside
(Preamble), the sync detection result signal
The logic level "1" is output to (R3T) 301.

A frequency pull-in determination means as the tenth embodiment of the present invention will be described. FIG. 10 is a block diagram of the frequency pull-in determination means 400 in the frequency detector 160 of the fourth embodiment. In FIG. 10, 100 is a data stream signal (RX) received through a digital audio interface (DAI), 151 is a comparison clock, and 300 is a sync for detecting a sync pattern periodically appearing in the received data stream signal 100. Detecting means, 301 is a sync detection result signal (R3T), 1000
Divides the comparison clock 151 to generate the data string signal 100.
A frequency dividing circuit for generating a clock having a cycle corresponding to the cycle in which the sync pattern appears, 1001 is an output signal of the frequency dividing circuit (2Fs), and 1010 is an output signal of the frequency dividing circuit (2Fs).
s) Counting how many syncs are detected in one cycle of 1001, and if the count value is within a predetermined range,
It is an I3T counting means that sets the output signal 401 to the logic level "0" and indicates that the frequency pull-in is completed.

A detailed description of the operation of the frequency pull-in determination means 400 configured as described above will be given below. D
The AI signal (data string signal) 100 is, as shown in FIG. 16, bi-phase encoded of digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data and the other channel is the R channel of audio data.

A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and is transmitted with 192 frames as one block.
Thus, in the DAI signal 100, the preamble portion appears periodically (1/2 fs), and 3T is used only in this preamble portion. Therefore, by detecting 3T,
The sync (preamble) can be detected.

When the inversion period of the DAI signal 100 is counted by the comparison clock 151, the count value 801 by the counting means 800 becomes maximum at 3T of the DAI signal 100, and at 1T, as shown in FIG. The count value 801 by the counting means 800 becomes the minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases. However, when the PLL is locked, the comparison clock 151 is generated. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value when the PLL is in the locked state is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100.

The demodulation clock 152 is used as the comparison clock 151.
If is selected, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) When the PLL is in the locked state, C _MAX (= 3) appears only in 3T, that is, only in the preamble part.

As described in the eighth embodiment, the sync detecting means 300 detects the count value data of C _MAX (= 3) or more and determines that it is the sync. Now, the DAI signal 100 is shown in FIG.
As shown in FIG. 6, three types of preambles (“B”,
"M" and "W"), but since 3T appears twice or once in each preamble, the PLL is
Is locked, 3T is detected twice or once in one cycle of the output signal (2Fs) of the frequency dividing circuit 1000.

The 3T counting means 1010 is the frequency dividing circuit 100.
In one cycle of the output signal (2Fs) of 0, the output signal 401 is set to the logical level “0” when the count value is 1 or 2.
Therefore, if the frequency of the voltage controlled oscillator circuit 140 (the frequency of the comparison clock 151) reaches the target value, the preamble is correctly detected periodically, so that the output signal 401 of the I3T counting means is always at the logical level “0”, Indicates that the PLL frequency acquisition is complete.

The frequency pull-in determination means as the 11th embodiment of the present invention will be described. FIG. 11 is a block diagram of the frequency pull-in determination means 400 in the frequency detector 160 of the fourth embodiment. In FIG. 11, reference numeral 100 is a data stream signal (RX) received through a digital audio interface (DAI), 151 is a comparison clock, and 500 is an inversion cycle of the received data stream signal 100 according to the comparison clock 151. Counting means 501, count value data 501, and an expected count value C of the maximum inversion period (3T) of the received data string signal 100.
_{When a count} value larger than _MAX appears, it is determined that the oscillation frequency of the voltage controlled oscillator circuit 140 is high. C _MAX <Detection unit, 700 is an expected counter for the minimum inversion period (1T) of the received data string signal 100. When a _count value smaller than the numerical value C _MIN appears, it is determined that the oscillation frequency of the voltage controlled oscillation circuit 140 is low C _MIN > detection means 1110 is C _MAX.
<The output signal of the detection means and C _MIN > An OR gate that takes the logical sum of the output signal of the detection means.

A detailed description of the operation of the frequency pull-in determination means 400 configured as above will be given below. D
The AI signal (data string signal) 100 is, as shown in FIG. 16, bi-phase encoded of digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data, and the other channel is the R channel of audio data.

A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and 192 frames are transmitted as one block.
Now, when the inversion period of the DAI signal 100 described above is counted by the comparison clock 151, as shown in FIG.
At 3T of the AI signal 100, the count value 501 by the counting means 500 becomes maximum, and at 1T, the count value 501 by the counting means 500 becomes minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases, but the comparison clock 151 is generated when the PLL is locked. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value in the locked state of the PLL is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100.

The demodulation clock 152 is used as the comparison clock 151.
If is selected, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) Similarly, the minimum count value when the PLL is in the locked state is uniquely determined, and this is determined in the minimum inversion period of the DAI signal 100. It is defined as the expected count value C _MIN .

The demodulation clock 152 is used as the comparison clock 151.
If you select C_MIN Is 1. (See FIG. 16 and FIG.
Timing of DAI signal 100 and demodulated clock 152 shown
See the drawing. ) C_MAX <Detection means is the maximum inversion period of the DAI signal 100.
Expected count value in C _MAX When a larger value appears
It is determined that the oscillation frequency of the voltage controlled oscillator circuit 140 is high.
Then, the logic level "1" is output.

C_MIN > The detecting means is to detect the DAI signal 100.
Expected count value C in the minimum inversion period _MIN Less than
When it appears, the oscillation frequency of the voltage controlled oscillator circuit 140 is
It is determined to be low, and "1" is output.

Since the OR gate 1110 ORs the output signal of C _MAX <detection means and the output signal of C _MIN > detection means, a value larger than the expected count value C _MAX in the maximum inversion period of the DAI signal 100 is obtained. If it appears, or
Expected count value C in the minimum inversion period of DAI signal 100
_{When a} value smaller than _MIN appears, a logic “1” is output to indicate that the oscillation frequency of the voltage controlled oscillator circuit 140 is outside the predetermined range, and the expected count value C _MAX in the maximum inversion period of the DAI signal 100. No larger value appears, and
Expected count value C in the minimum inversion period of DAI signal 100
_{When a} value smaller than _MIN does not appear, a logic "0" is output to indicate that the oscillation frequency of the voltage controlled oscillator circuit 140 is within the predetermined range.

When the frequency of the voltage controlled oscillator circuit 140 (the frequency of the comparison clock 151) is within the predetermined range, the output signal of the OR gate 1110 is always at the logic level "0", indicating that the PLL frequency pull-in is completed. Show.

A frequency pull-in judging means as a twelfth embodiment of the present invention will be described. FIG. 12 is a block diagram of the frequency pull-in determination means 400 in the frequency detector 160 of the fourth embodiment. In FIG. 12, reference numeral 100 is a data stream signal (RX) received through a digital audio interface (DAI), 151 is a comparison clock, and 500 is an inversion cycle of the received data stream signal 100 according to the comparison clock 151. Counting means, 501 is count value data, 300 is sync detecting means for detecting a sync pattern periodically appearing in the received data string signal 100, and 301 is sync detection result signal (R3
T), 600, the count value is reset as soon as the sync is detected by the sync detecting means 300, counting is performed by the comparison clock 151, and the period from the count value being 0 to a predetermined value is the sync period. 601 is a sync window signal generating means for generating a signal indicating that the count value is larger than the expected count value C _MAX of the maximum inversion period (3T) of the received data string signal 100. If it appears in a period other than the sync period, it is determined that the oscillation frequency of the voltage controlled oscillator circuit 140 is high. C _MAX <Detection means 700 is an expected count value C of the minimum inversion period (1T) of the received data string signal 100. _{When a count} value smaller than _MIN appears, it is determined that the oscillation frequency of the voltage controlled oscillator circuit 140 is low C _MIN > Detection means 1110 is C _MAX
<The output signal of the detection means and C _MIN > An OR gate that takes the logical sum of the output signal of the detection means.

The detailed operation of the thus-configured frequency pull-in determination means 400 will be described below. D
The AI signal (data string signal) 100 is, as shown in FIG. 16, bi-phase encoded of digital audio data, and the data is composed of two types of signals, 1T and 2T.

Here, T is T = 1 / 128fs, and fs is a sampling frequency (sampling frequency) of audio data. However, 3T is used only for the preamble (synchronization signal) indicating the delimiter of each channel (channel 1, channel 2).

FIG. 16 shows an example of DAT. One channel is the L channel of audio data, and the other channel is the R channel of audio data.

A 2-channel signal has a frame composed of three types of preambles "B", "M", and "W", and is transmitted with 192 frames as one block.
Now, when the inversion period of the DAI signal 100 described above is counted by the comparison clock 151, as shown in FIG.
At 3T of the AI signal 100, the count value 501 by the counting means 500 becomes maximum, and at 1T, the count value 501 by the counting means 500 becomes minimum.

The count value increases as the frequency of the comparison clock 151 increases, and decreases as the frequency of the comparison clock 151 decreases. However, when the PLL is locked, the comparison clock 151 is generated. The maximum count value and the minimum count value are uniquely determined by the frequency division number of the frequency dividing circuit 150.

As described above, the maximum count value when the PLL is in the locked state is uniquely determined, and this is defined as the expected count value C _MAX in the maximum inversion period of the DAI signal 100.

The demodulation clock 152 is used as the comparison clock 151.
If is selected, C _MAX is 3. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) Similarly, the minimum count value when the PLL is in the locked state is uniquely determined, and this is determined in the minimum inversion period of the DAI signal 100. It is defined as the expected count value C _MIN .

The demodulation clock 152 is used as the comparison clock 151.
If C _MIN is selected, C _MIN is 1. (Refer to the timing diagrams of the DAI signal 100 and the demodulation clock 152 shown in FIGS. 16 and 17.) 300 is a sync detecting means, but as described in the third embodiment, in the DAI signal 100, the preamble part is periodic ( 1/2 fs) and 3T only in this preamble part
, The sync (preamble) can be detected by detecting 3T.

The sync detecting means 300 detects the DAI signal 10
3T is detected from the relationship between 0 and the comparison clock 151,
The sync detection result signal 301 is output. The sync window signal generation means 600 generates a section signal indicating the preamble period (sync period) of the DAI signal 100 based on the sync detection result 301 and the comparison clock 151, and as the sync window signal 601, C _MAX <detection. Supply to the means.

C_MAX <Detection means is for the DAI signal 100
Expected count value C in the maximum inversion period _MAX Greater than
Is less than the sync period indicated by the sync window signal 601.
When it appears outside, the oscillation frequency of the voltage-controlled oscillation circuit 140
It is determined that the number is high, and the logic level "1" is output.

C_MIN > The detecting means is to detect the DAI signal 100.
Expected count value C in the minimum inversion period _MIN Less than
When it appears, the oscillation frequency of the voltage controlled oscillator circuit 140 is
It is determined to be low, and "1" is output.

Since the OR gate 1110 ORs the output signal of C _MAX <detection means and the output signal of C _MIN > detection means, a value larger than the expected count value C _MAX in the maximum inversion period of the DAI signal 100 is obtained. When it appears in a period other than the sync period, or when a value smaller than the expected count value C _MIN in the minimum inversion period of the DAI signal 100 appears, a logic “1” is output and the oscillation frequency of the voltage controlled oscillator circuit 140 is changed. Indicates that the DAI signal 100 is out of the predetermined range.
When a value larger than the expected count value C _MAX in the maximum inversion cycle of the DAI signal does not appear in a period other than the sync period and a value smaller than the expected count value C _MIN in the minimum inversion cycle of the DAI signal 100 does not appear, a logic “0” is set. It is output to indicate that the oscillation frequency of the voltage controlled oscillator circuit 140 is within a predetermined range.

When the frequency of the voltage controlled oscillator circuit 140 (the frequency of the comparison clock 151) is within the predetermined range, the output signal of the OR gate 1110 is always at the logic level "0", indicating that the PLL frequency pull-in is completed. Show.

PLL times as the thirteenth embodiment of the present invention
The route will be described. FIG. 13 is a block diagram of another PLL circuit
Is. In FIG. 13, 100 is a digital audio
Data stream received through the video interface
No. (RX) and 110 are the data string signal 100 and the demodulation clock.
Phase comparison to compare phase with lock (PCK) 152
, 111, 112 are output signals of the phase comparator 110.
Yes, 111 is the demodulation clock 15 at the logic level "1".
A control signal (U _P ), 112 is a logical
A control that indicates the phase advance of the demodulation clock 152 at level "1".
Signal (D_P ), 160 is the output of the frequency dividing circuit 150.
Relationship between the comparison clock 151 and the data string signal 100
From the voltage controlled oscillator circuit 140
Frequency detectors 161, 162 for outputting the
The output of the detector 160, 161 is a logic level
The oscillation frequency f of the voltage controlled oscillator circuit 140 is "1". _VCO But
Control signal (U_F ), 162 are logical levels
The oscillation frequency f of the voltage controlled oscillator circuit 140 is set to "1"._VCO 
Control signal (D_F ) 1300 is the phase
The output signal of the comparator 110 is the output of the frequency detector 160.
Multiplexing means for multiplexing signals; 121, phase comparison output;
130 smoothes the voltage change of the phase comparison output 121,
A loop for applying a control voltage to the voltage controlled oscillator circuit 140
A filter, 140 is a voltage controlled oscillator circuit.

The detailed operation of the PLL circuit configured as described above will be described below. The PLL circuit shown in FIG. 1 has a frequency f _PCK of the demodulation clock (PCK) 152.
Is, for example, outside the frequency pull-in range (capture range) of the PLL circuit, and when the oscillation frequency f _VCO of the voltage-controlled oscillation frequency is far from the target frequency, the output signal of the frequency detector 160 Is a control signal (U _F ) 161 for controlling to increase the oscillation frequency of the voltage controlled oscillator circuit 140, or the voltage controlled oscillator circuit 14
Control signal ( _DF ) that controls to reduce the oscillation frequency of 0
One of 162 becomes the logic level "1", and based on this, the multiplexing means 1300 causes the phase comparator 110 to operate.
Output signals 111 and 112 of the frequency detector 160
The output signal of 1 is multiplexed and output to 121 as a phase comparison output.

In the above operation, the frequency f _PCK of the demodulation clock 152 is within the frequency pull-in range (capture range) of the PLL circuit, and the output signal 16 of the frequency detector is
1 and 162 (that is, until both the output signals 161 and 162 of the frequency detector are constantly at the logic level "0").

The multiplexing means 1300 of this embodiment, based on the instruction of the predetermined control signal (DTFS) 1301, outputs the output signal 111 of the phase comparator 110 when the control signal 1301 indicates the inhibition of multiplexing. By 112 only,
When the loop control is performed according to the phase difference between the demodulation clock 152 and the data string signal 100, and the control signal 1301 indicates multiplexing, the output signal 11 of the phase comparator 110
1 and 112, the output signal 161 of the frequency detector 160,
By multiplexing 162, the demodulation clock 152
And the data string signal 100, the loop is controlled according to the frequency difference and the phase difference.

In this way, if the frequency f _PCK of the demodulation clock 152 falls within the frequency pull-in range (capture range) of the PLL circuit, the operation thereafter is exactly the same as that of the conventional PLL circuit for generating the demodulation clock. .

That is, the phase difference between the demodulation clock 152 and the data string signal 100 is reduced, and when the phase difference disappears, the output DC voltage of the loop filter 130 becomes constant, and at this point the demodulation clock 152 becomes , The frequency is twice as high as the maximum repetition frequency f _MAX of the data string signal 100, and the data string signal 100 is stable in a predetermined phase relationship.

A PLL circuit as a 14th embodiment of the present invention will be described. FIG. 14 is a block diagram of yet another PLL circuit. In FIG. 14, 100 is a digital
The data sequence signal (RX) received through the audio interface 110 is a phase comparator for comparing the phases of the data sequence signal 100 and the demodulation clock (PCK) 152, and 111 and 112 are output signals of the phase comparator 110. And 111 is the demodulation clock 1 at the logic level "1".
52 a control signal indicating a phase delay of (U _P), 112 is a control signal indicating a phase lead of the demodulation clock 152 a logic level _{"1" (D P),} 160 , the comparison clock which is an output of the frequency divider circuit 150 From the relationship between 151 and the data string signal 100, a frequency detector that outputs a signal according to the oscillation frequency of the voltage controlled oscillation circuit 140, 161, 162 are outputs of the frequency detector 160, and 161 is a logical level. A control signal (U _F ) indicating that the oscillation frequency f _VCO of the voltage controlled oscillation circuit 140 is low at “1”, 162 is an oscillation frequency f _VCO of the voltage controlled oscillation circuit 140 at a logic level “1”.
Is a control signal ( _DF ) that indicates a high level, and 200 is a lock detection unit that determines whether or not the phase of the demodulation clock 152 and the phase of the data string signal 100 are synchronized and the data can be demodulated. When the lock detection means 200 determines that the lock signal is in the unlocked state, the output signal of the phase comparator 110 is multiplexed with the output signal of the frequency detector 160 to generate the phase comparison output 121, which is in the locked state. When it is determined that the output signal of the phase comparator 110, the multiplexing means for generating the phase comparison output 121, 121 is the phase comparison output, 130 is the phase comparison output 1
21 is a loop filter for smoothing the voltage change of 21 and applying a control voltage to the voltage controlled oscillator circuit 140, and 140 is a voltage controlled oscillator circuit.

The detailed operation of the PLL circuit thus configured will be described below. The PLL circuit shown in FIG. 1 has a frequency f _PCK of the demodulation clock (PCK) 152.
Is, for example, outside the frequency pull-in range (capture range) of the PLL circuit, and when the oscillation frequency f _VCO of the voltage-controlled oscillation frequency is far from the target frequency, the output signal of the frequency detector 160 Is a control signal (U _F ) 161 for controlling to increase the oscillation frequency of the voltage controlled oscillator circuit 140, or the voltage controlled oscillator circuit 14
Control signal ( _DF ) that controls to reduce the oscillation frequency of 0
One of 162 becomes the logic level "1".

In this case, the lock detecting means 200
Determines that the data cannot be demodulated, and based on this, the multiplexing means 1400 multiplexes the output signals 111 and 112 of the phase comparator 110 with the output signal of the frequency detector 160 to perform phase comparison. The output 121 is output.

In the above operation, the frequency f _PCK of the demodulation clock 152 is within the frequency pull-in range (capture range) of the PLL circuit, and the output signal 16 of the frequency detector is
1 and 162 (that is, until both the output signals 161 and 162 of the frequency detector are constantly at the logic level "0").

The multiplexing means 1400 of this embodiment, based on the instruction of the predetermined control signal (DTFS) 1301, when the control signal 1301 indicates the inhibition of multiplexing, the output signal 111 of the phase comparator 110, By 112 only,
When the loop is controlled in accordance with the phase difference between the demodulation clock 152 and the data string signal 100, and the control signal 1301 indicates multiplexing, the phase is detected during unlocking based on the determination result of the lock detecting means 200. The output signals 161 and 162 of the frequency detector 160 are multiplexed with the output signals 111 and 112 of the comparator 110 to control the loop, and when locked, the output signals 111 and 11 of the phase comparator 110 are locked.
2 controls the loop.

In this way, if the frequency f _PCK of the demodulation clock 152 is within the frequency pull-in range (capture range) of the PLL circuit, the operation thereafter is exactly the same as that of the conventional PLL circuit for demodulation clock generation. .

That is, the phase difference between the demodulation clock 152 and the data string signal 100 is reduced, and when the phase difference disappears, the output DC voltage of the loop filter 130 becomes constant, and at this point the demodulation clock 152 becomes , The frequency is twice as high as the maximum repetition frequency f _MAX of the data string signal 100, and the data string signal 100 is stable in a predetermined phase relationship.

At this point, the lock detecting means 200
Determines that the data can be demodulated, and the multiplexing means 14
00 controls to generate the phase comparison output 121 only from the output signal of the phase comparator 110.

As a result, when the PLL circuit is locked, the output of the frequency detector 160 is the phase comparison output 12
1, the PLL can operate stably even if the frequency detector 160 malfunctions due to noise on the received data string signal 100 or the like.

By the operation of each of the above-mentioned embodiments, the frequency pull-in capability can be improved, the substantial capture range can be expanded as compared with the conventional one, and the data train signal and the demodulation clock which are in the phase locked state can be obtained. The frequency difference can be increased.

[0201]

As described above, according to the present invention, when the frequency difference between the maximum repetition frequency of the data string signal and the frequency of the demodulation clock is outside the frequency pull-in range (capture range) of the PLL circuit, Is detected by the frequency detector, and the frequency detector performs the frequency pulling operation so that the frequency difference between the maximum repetition frequency of the data string signal and the frequency of the demodulation clock falls within the frequency pulling range of the PLL circuit. You can

Further, since the frequency detector is configured to make a relative comparison between the data string signal and the demodulated clock, even if the pitch of the data string signal changes greatly, the PLL circuit will not be erroneously compared. The frequency pull-in operation can be performed following the tracking.

Therefore, it is possible to improve the frequency pull-in capability, to expand the substantial capture range as compared with the conventional one, and to expand the frequency difference between the data string signal in the phase locked state and the demodulation clock. it can.

In addition, since the output of the frequency detector is not reflected in the phase comparison output for controlling the loop when the PLL circuit is in the lock state, noise such as noise may be added to the received data string signal. Even if the frequency detector malfunctions due to the cause, it operates stably without being affected by this.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a PLL circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a frequency detector (third embodiment) in a PLL circuit according to first and second embodiments of the present invention.

FIG. 4 is a configuration diagram of a frequency detector (fourth embodiment) in the PLL circuits of the first and second embodiments of the present invention.

FIG. 5 is a configuration diagram of a frequency detector (fifth embodiment) in the PLL circuits of the first and second embodiments of the present invention.

FIG. 6 is a configuration diagram of a frequency detector (sixth embodiment) in the PLL circuits according to the first and second embodiments of the present invention.

FIG. 7 is a configuration diagram of a frequency detector (seventh embodiment) in the PLL circuits of the first and second embodiments of the present invention.

FIG. 8 is a configuration diagram of sync detecting means (eighth embodiment) in the frequency detectors of the third and fourth embodiments of the present invention.

FIG. 9 is a configuration diagram of sync detection means (ninth embodiment) in the frequency detectors of the third and fourth embodiments of the present invention.

FIG. 10 is a configuration diagram of frequency pull-in determination means (tenth embodiment) in a frequency detector according to a fourth embodiment of the present invention.

FIG. 11 is a configuration diagram of frequency pull-in determination means (eleventh embodiment) in a frequency detector according to a fourth embodiment of the present invention.

FIG. 12 is a configuration diagram of frequency pull-in determination means (twelfth embodiment) in a frequency detector according to a fourth embodiment of the present invention.

FIG. 13 is another PLL circuit of the present invention (thirteenth embodiment).
Configuration diagram of

FIG. 14 is a configuration diagram of still another PLL circuit (14th embodiment) of the present invention.

FIG. 15 is a configuration diagram of a conventional PLL circuit.

FIG. 16 is a timing diagram showing the format of the DAI signal.

FIG. 17 is a timing chart of C _MAX <detection means, C _MAX ≦ detection means, and C _MIN > detection means of the PLL circuit according to the embodiment of the present invention.

[Explanation of symbols]

 120 Multiplexing means 160 Frequency detector 200 Lock detecting means 210 Multiplexing means 300 Sync detecting means 310 Dividing circuit 320 Frequency phase comparator 400 Frequency pull-in determining means 500 Counting means 600 Sync window signal generating means 800 Counting means 900 Mask signal generating Means 1300 Multiplexing means 1400 Multiplexing means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03L 7/08 B

Claims (14)

[Claims] 1. A phase comparator compares the phases of an input data string signal with a demodulation clock generated based on the oscillation frequency of a voltage controlled oscillator circuit, and based on the detected phase difference, the voltage control is performed. In a PLL circuit that controls the oscillation of an oscillation circuit and outputs the demodulation clock whose phase and frequency are synchronized with the data string signal, a comparison that is generated based on the oscillation frequency of the voltage controlled oscillation circuit and is different from the demodulation clock A frequency detector that outputs a signal according to the oscillation frequency of the voltage controlled oscillator circuit based on a clock and the data string signal, and an output signal of the phase comparator and an output signal of the frequency detector are multiplexed. And a multiplexer for controlling the voltage control according to a frequency difference and a phase difference between the demodulated clock and the data string signal obtained by the multiplexing. A PLL circuit configured to control the oscillation of the oscillator circuit. 2. The phase comparator compares the phase of the input data string signal with the phase of the demodulation clock generated based on the oscillation frequency of the voltage controlled oscillator circuit, and based on the detected phase difference, the voltage control is performed. In a PLL circuit that controls the oscillation of an oscillation circuit and outputs the demodulation clock whose phase and frequency are synchronized with the data string signal, a comparison that is generated based on the oscillation frequency of the voltage controlled oscillation circuit and is different from the demodulation clock Based on the clock and the data string signal, a frequency detector that outputs a signal according to the oscillation frequency of the voltage controlled oscillator circuit, and detects that the phase of the demodulated clock and the data string signal are synchronized, A lock detecting unit that determines that a data demodulation is possible, and an output signal of the phase comparator and the frequency detector based on the determination of the lock detecting unit. When the lock detecting means determines that the lock state is the locked state, the multiplexing means does not perform the multiplexing, and the demodulation clock and the data string signal are provided. The output signal of the phase comparator according to the phase difference between the control circuit and the oscillation of the voltage-controlled oscillation circuit is configured to be controlled, and when the lock detecting means determines an unlocked state opposite to the locked state. Is a PLL circuit configured to perform the multiplexing and control the oscillation of the voltage controlled oscillation circuit according to the frequency difference and the phase difference between the demodulated clock and the data string signal. 3. A frequency detector, a sync detecting means for detecting a sync pattern of data which appears periodically in the data string signal, and a frequency of the output signal of the voltage controlled oscillator circuit, and a cycle in which the sync pattern appears in the data string signal. And a frequency phase comparator for comparing the frequency and phase of both with the output signal of the frequency divider circuit as a variable input and the output signal of the sync detecting means as a reference input. 3. The frequency phase comparator is configured to output a signal according to a frequency difference and a phase difference between the output signal of the frequency dividing circuit and the output signal of the sync detecting means. The PLL circuit described in 1. 4. A frequency detector, a sync detection means for detecting a sync pattern of data that appears periodically in a data string signal, and a frequency-divided output signal of a voltage controlled oscillator circuit, and a cycle in which the sync pattern appears in the data string signal. A frequency dividing circuit for generating a clock having a cycle corresponding to the above, and one of the output signal of the frequency dividing circuit and the output signal of the sync detecting means is used as a variable input and the other is used as a reference input, and the frequencies and phases of both are compared. And a frequency pull-in determination means for determining whether the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range, and the frequency phase comparator has the frequency pull-in determination means for the voltage When it is determined that the oscillation frequency of the control oscillation circuit is out of the predetermined range, the output signal of the sync detecting means is set to the variable input and the frequency division is performed. When the output signal of the circuit is used as the reference input and the frequency pull-in determination means determines that the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range, the output signal of the frequency dividing circuit is used as the variable input. At the same time, the output signal of the sync detecting means is used as the reference input, and a signal according to a frequency difference and a phase difference between the output signal of the frequency dividing circuit and the output signal of the sync detecting means is output. The PLL according to claim 2.
circuit. 5. The frequency detector is provided with counting means for counting the inversion period of the data string signal by a comparison clock based on the output signal of the voltage controlled oscillator circuit, and the frequency detector is provided with a count value by the counting means. , If it is larger than the expected count value in the maximum inversion period of the data string signal,
The PLL circuit according to claim 1 or 2, wherein the PLL circuit is configured to output a signal for reducing the oscillation frequency of the voltage controlled oscillator circuit. 6. The frequency detector resets the count value by counting means for counting the inversion period of the data string signal by a comparison clock based on the output signal of the voltage controlled oscillation circuit, and by the sync pattern detected by the sync detecting means. The period from the count value to a predetermined value, which is counted by the comparison clock, is defined as a sync period, and a sync window signal generating means for generating a signal indicating the sync period is provided. When the count value by the counting means is larger than the expected count value in the maximum inversion period of the data string signal outside the sync period, a signal for lowering the oscillation frequency of the voltage controlled oscillator circuit is output. The configured PLL according to claim 1 or claim 2.
circuit. 7. The frequency detector is provided with counting means for counting the inversion period of the data string signal by a comparison clock based on the output signal of the voltage controlled oscillator circuit, and the frequency detector is provided with a count value by the counting means. , If it is smaller than the expected count value in the minimum inversion period of the data string signal,
The PLL circuit according to claim 1 or 2, wherein the PLL circuit is configured to output a signal for increasing the oscillation frequency of the voltage controlled oscillation circuit. 8. The sync detecting means is provided with counting means for counting the inversion cycle of the data string signal by a comparison clock based on the output signal of the voltage controlled oscillator circuit, and the sync detecting means is provided with a count value by the counting means. 5. The method according to claim 3 or 4, wherein when the count value is equal to or larger than an expected count value in the maximum inversion cycle of the data string signal, the sync pattern is determined to be the sync pattern of the data string signal and the sync pattern is detected. PLL circuit. 9. The sync detecting means includes a counting means for counting the inversion period of the data string signal by a comparison clock based on the output signal of the voltage controlled oscillator circuit, and a count value reset when the sync is detected and counting by the comparison clock. Then, a period from the count value becoming 0 to a predetermined value is set as a sync detection stop period, and a mask signal generating means for generating a signal indicating the sync detection stop period is provided, and the sync detection means is When the count value by the counting means is equal to or larger than the expected count value in the maximum inversion period of the data string signal outside the sync detection stop period, it is determined that the sync pattern is the sync string of the data string signal, and this sync pattern is detected. The PLL circuit according to claim 3 or 4, wherein the PLL circuit is configured to: 10. The frequency pull-in determination means detects whether or not the sync pattern of the data string signal is detected in a correct cycle, and when the sync pattern is not detected in a correct cycle, voltage control oscillation is performed. A configuration for determining that the oscillation frequency of the circuit is outside a predetermined range, and determining that the oscillation frequency of the voltage controlled oscillation circuit is within a predetermined range when the sync pattern is detected in a correct cycle. Item 5. The PLL circuit according to Item 4. 11. The frequency pull-in determination means is provided with counting means for counting the inversion period of the data string signal by a comparison clock based on the output signal of the voltage controlled oscillator circuit, and the frequency pull-in determination means is counted by the counting means. When the numerical value is larger than the expected count value in the maximum inversion period of the data string signal, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is higher than a predetermined frequency, and the count value by the counting means is the data string. When it is smaller than the expected count value in the minimum inversion period of the signal, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is lower than a predetermined frequency, and the oscillation frequency of the voltage controlled oscillation circuit is determined to be outside the predetermined range. The PLL circuit according to claim 4, which is configured to: 12. The frequency pull-in determination means resets the count value by counting means for counting the inversion period of the data string signal by a comparison clock based on the output signal of the voltage controlled oscillator circuit and by the sync pattern detection by the sync detection means. , A sync window signal generating means for generating a signal indicating the sync period, the period being counted from the comparison lock, and the period from the count value being 0 to a predetermined value being a sync period, and the frequency pull-in When the count value by the counting means is larger than the expected count value in the maximum inversion period of the data string signal outside the sync period, the determining means determines that the oscillation frequency of the voltage controlled oscillation circuit is higher than a predetermined frequency. It is determined that the count value by the counting means is the expected value in the minimum inversion period of the data string signal outside the sync period. When the value is smaller than a numerical value, it is determined that the oscillation frequency of the voltage controlled oscillation circuit is lower than a predetermined frequency, and it is determined that the oscillation frequency of the voltage controlled oscillation circuit is outside a predetermined range. P described
LL circuit. 13. A phase comparator according to a phase difference between a demodulation clock and a data string signal, when the multiplexing means instructs the inhibition of multiplexing based on an instruction of a predetermined control signal. Control the oscillation of the voltage controlled oscillator circuit only by the output signal of, when the control signal indicates multiplexing, by multiplexing the output signal of the phase comparator and the output signal of the frequency detector, The P according to claim 1, wherein the oscillation of the voltage controlled oscillator circuit is controlled according to the frequency difference and the phase difference between the demodulated clock and the data string signal.
LL circuit. 14. A phase comparator according to a phase difference between a demodulation clock and a data string signal, wherein the multiplexing means, based on an instruction of a predetermined control signal, when the control signal indicates inhibition of multiplexing. The output signal of the phase comparator is controlled based on the determination result of the lock detection means when the oscillation of the voltage controlled oscillation circuit is controlled only by the output signal of the above, and the control signal indicates multiplexing. And the output signal of the frequency detector are multiplexed to control the oscillation of the voltage controlled oscillation circuit, and when locked, the oscillation of the voltage controlled oscillation circuit is controlled by the output signal of the phase comparator. The PLL circuit according to claim 2.