KR20010011117A - Clock recovery circuit having wide capture range - Google Patents

Abstract

PURPOSE: A circuit for restoring a clock having a large frequency inducing range is provided to generate an optimum playback clock signal through a digital PLL(Phase Locked Loop) by adaptively varying a frequency of a control clock signal according to a bit rate of an EFM(Eight to Fourteen Modulation) signal. CONSTITUTION: A frequency synchronizing unit generates a reference clock signal and a control clock signal with first/second variables. A digital PLL generates a playback clock signal to modulate an EFM signal with the control clock signal. An adaptive clock control unit(30) decides an initial value of the first variable according to a resolution of the PLL and a velocity of a disk. The adaptive clock control unit controls the first variable to adaptively vary the control clock signal according to a bit rate of the EFM signal with the control clock signal. The optimum playback clock signal is restored by adaptively varying a frequency of the control clock signal.

Description

Clock recovery circuit having wide capture range

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for generating a reproduction clock signal used for recovering EFM data in an optical disc reproduction system such as a CDP (Copact Dick Player) or a DVD (Digital Versatile Dick Player). The present invention relates to a clock recovery circuit having a wide frequency introduction range capable of varying the frequency according to the bit rate of the EFM signal.

In optical disc playback systems such as CDP or DVDP, EFM demodulation data is extracted from the EFM signal read from the disc, and the extracted EFM demodulation data is stored in internal or external memory of 16 to 33 kbits and read at a constant speed to correct errors. The error-corrected data is outputted through the DAC. In an ideal case, the EFM signal is input at a bit rate of 4.3218MHz and output at 44.1KHZ. In practice, however, the output is constant at 44.1 kHz by the clock of the crystal oscillator, but the input has jitter due to variations in disk rotation speed. Thus, a clock reproduction signal synchronized with the EFM signal is generated by internally or externally providing a phase synchronization loop, and the EFM demodulated data is recovered by using the clock reproduction signal. However, if the jitter accumulates, even if the phase-locked loop operates normally and the EFM signal is read correctly, the memory for error correction is full or empty due to the difference between the input bit rate and the output bit rate. can not do it. Therefore, even if the locking characteristic of the phase locked loop is good, it is not significant. In fact, the phase-locked loop used in the typical CDP has a frequency introduction range of 3 to 7%. However, when the ESP (Electric Shock Proof) function is added, it uses a separate memory of 1Mbit or more for the data buffer and reads or stops data on the disk according to the pool or empty of the memory. Does not affect. Therefore, the characteristics of the PLL become more important, and a phase locked loop having a large frequency introduction range is required.

1 is a block diagram schematically illustrating a general clock regeneration circuit. The conventional clock regeneration circuit comprises a frequency synthesizer 10 and a digital PLL 12.

The frequency synthesizer 10 shown in FIG. 1 supplies a control clock signal VCOCK for operating the digital PLL 22. At this time, the control clock signal VCOCK has a frequency n times the bit rate of the EFM signal according to the resolution of the digital PLL 22. Here, when the disk is 1x speed, the bit rate of the EFM signal is 4.3218 MHz. The configuration and operation of the frequency synthesizer 10 will be described later in detail.

The control clock signal VCOCK output from the frequency synthesizer 10 is determined by Equation 1 according to the speed of the disk and the resolution of the digital PLL.

VCOCK = FIN * M / P

Here, FIN is a reference clock signal having a constant period output from the crystal oscillator, and M and P are first and second variables determined by the resolution of the digital PLL and the speed of the disk.

Conventionally, when the resolution and the speed are determined, the first and second variables M and P are determined, and thus the control clock signal VCOCK is automatically determined.

The digital PLL 12 detects the frequency error and phase error of the EFM signal in response to the control clock signal VCOCK and ideally generates a reproduction clock signal PLCK of 4.3218 MHz (at 1x speed). Demodulate the EFM signal using (PLCK).

However, regardless of the resolution of the digital PLL, when the jitter of the EFM signal is 0.5T or more (where T is one cycle of the reproduction clock signal), an incorrect frequency error and a phase error are detected. As a result, the EFM signal may not be properly followed, resulting in detection of a wrong EFM signal.

The technical problem to be achieved by the present invention is to provide a wide frequency introduction range for adaptively varying the frequency of the control clock signal that controls the operation of the digital PLL according to the bit rate of the EFM signal so that the digital PLL can generate an optimal reproduction clock signal. It is to provide a clock recovery circuit having.

1 is a block diagram schematically illustrating a general clock regeneration circuit.

2 is a block diagram schematically illustrating a clock recovery circuit having a wide frequency introduction range according to the present invention.

3 is a circuit diagram illustrating a first exemplary embodiment of the present invention of an adaptive clock controller in the apparatus shown in FIG. 2.

FIG. 4 is a block diagram showing a second embodiment according to the present invention of the adaptive clock controller shown in FIG.

5A to 5J are timing diagrams illustrating a process of changing the first variable M in the apparatus shown in FIG. 4.

In order to achieve the above object, a reproduction clock recovery circuit having a wide frequency introduction range according to the present invention for detecting an EFM signal in an optical disc reproducing system and reconstructing a reproduction clock signal used for EFM demodulating the detected EFM signal has a period. A frequency synthesizer which receives a constant reference clock signal, a first variable, and a second variable and generates a control clock signal by the following equation;

VCOCK = FIN * M / P

(Where VCOCK represents a control clock signal, FIN represents a reference clock signal, M represents a first variable, and P represents a second variable).

The initial value of the first variable is determined according to the resolution of the digital phase lock loop and the digital phase lock loop and the speed of the disc which generate a reproduction clock signal for receiving the control clock signal and the EFM signal and demodulating the EFM signal. It is preferable to include an adaptive clock control unit which receives the signal and the control clock signal and controls the first variable so that the control clock signal is adaptively changed according to the bit rate of the EFM signal.

2 is a block diagram schematically illustrating a clock recovery circuit having a wide frequency introduction range according to the present invention. The clock recovery circuit having a wide frequency introduction range according to the present invention includes an adaptive clock controller 30, a frequency synthesizer 34, and a digital PLL 32.

Referring to FIG. 2, the frequency synthesizer 34 includes the first variable M and the second variable, which are determined according to the reference clock signal FIN having a constant period, the resolution of the digital PLL 32, and the speed of the disc as described above. The variable is received and a control clock signal VCOCK is generated by Equation 1. In more detail, frequency synthesizer 34 includes first and second dividers 20 and 22, phase difference detector 24, charge pump 25, loop filter 26, and voltage controlled oscillator 28. It is composed.

The first divider 20 receives the reference clock signal FIN having a constant period generated from an external crystal oscillator, divides the signal into the second variable P, and generates the divided signal as the first divider signal. The second divider 22 receives the control clock signal VCOCK generated by the voltage controlled oscillator 28 and divides it into the first variable M, and generates the divided signal as the second divided signal. The phase difference detector 24 detects the phase difference between the first and second divided signals generated by the first and second dividers 20 and 22 and outputs the result, and the charge pump 25 outputs the phase difference detector 24. The charge corresponding to the phase difference detected in the sink is supplied from the loop filter 26 or supplied to the loop filter 26. The loop filter 26 low pass filters the signal supplied from the charge pump 25 or sinks into the charge pump 25, and generates the low pass filtered signal as a control voltage. The voltage controlled oscillator 28 generates a control clock signal VCOCK that oscillates corresponding to the control voltage generated from the loop filter 26.

The digital PLL 32 receives the control clock signal VCOCK and the EFM signal and generates a reproduction clock signal PLCK for demodulating the EFM signal.

The adaptive clock controller 30 determines the initial value M0 of the first variable M according to the resolution of the digital PLL 32, receives the EFM signal and the control clock signal PLCK, and applies the bit rate of the EFM signal. Accordingly, the first variable M is controlled such that the control clock signal PLCK is adaptively changed. In other words, the frequency of the control clock signal VCOCK output from the frequency synthesizer 34 is not fixed according to the resolution of the digital PLL 32 and the speed of the disc, but the EFM signal is varied by the change of the rotation speed of the disc. Since the first variable M is adaptively varied according to the bit rate, the control clock signal VCOCK follows the EFM signal.

In general, the longest duty (MAXT) interval exists in the EFM signal for frame synchronization every frame. In the case of CD, the longest duty (MAXT) is 11T, which is generated twice in succession. In the case of DVD, the longest duty MAXT is 14T, which is generated once. As such, the longest duty MAXT of the EFM signal can be counted as the control clock signal VCOCK to estimate the bit rate of the EFM signal. Accordingly, the value of the first variable M is changed to fall within the frequency introduction range of the digital PLL. The frequency of the control clock signal VCOCK can be changed.

When the resolution of the digital PLL 32 is Nr, the frequency of the control clock signal VCOCK can be obtained by multiplying the resolution Nr by the bit rate of the EFM signal, and the bit rate of the EFM signal is determined by the speed of the disk. For example, at 1x, the bit rate of the EFM signal is 4.3218 MHz, and at nx, the bit rate of the EFM signal is n * 4.3218MHz.

At this time, if the longest duty MAXT is 11T, in the ideal case, the value of counting the longest duty MAXT as the control clock signal VCOCK is 11 * Nr. Therefore, when the maximum duty MAXT> 11 * Nr + α is a low bit rate of the EFM signal, the value of the first variable M is decreased to decrease the frequency of the control clock signal VCOCK. On the other hand, if the maximum duty MAXT <11 * Nr-α, the bit rate of the EFM signal is fast, so that the value of the first variable M is increased to increase the frequency of the control clock signal VCOCK. Here, α is a margin value corresponding to a frequency introduction range that the digital PLL 32 can follow. That is, if the value of the first variable M is changed until 11 * Nr−α ≦ longest duty ≦ 11 * Nr + α, the digital PLL follows the error of ± α and reproduces in synchronization with the bit rate of the EFM signal. Since the clock signal PLCK is output, the correct regenerative clock signal PLCK can be restored.

3 is a circuit diagram illustrating a first exemplary embodiment of the adaptive clock controller 30 according to the present invention in the apparatus shown in FIG. 2. The adaptive clock controller 30 according to the first embodiment includes a counter 70, a maximum value generator 80, and a variable controller 90.

Referring to FIG. 3, the counter 70 counts the control clock signal for each high section and low section of the EFM signal. Here, 11T, which is the longest duty of the CD, may appear in the form of '00000000000' or in the form of '11111111111'. The same applies to DVD. Therefore, in order to count the longest duty 11T or 14T, the control clock signal VCOCK must be counted for each of the high and low sections of the EFM signal.

The maximum value generator 80 extracts the maximum value among the values counted by the counter 70 for a predetermined period in response to the control signal C, and outputs the extracted maximum value. At this time, extracting the maximum value detects the frame sync period, and therefore, the frame sync period must be included in the period in which the maximum value is extracted. A detailed description of the maximum value generator 80 will be described later with reference to FIG. 4.

If the maximum value output from the maximum value generator 80 is greater than the first reference value REF1, the variable controller 90 decreases the value of the first variable M by a predetermined value, and the maximum value is the second reference value ( If less than REF2), the value of the first variable M is controlled to be larger by a predetermined value. In the case of CD, the first reference value REF1 is (11 * Nr + α) and the second reference value REF2 is (11 * Nr−α). In the case of DVD, the first reference value REF1 is (14 * Nr + α) and the second reference value REF2 is (14 * Nr−α). For example, if the maximum value output from the maximum value generator 80 is greater than the first reference value REF1 when the value of the first variable M is 98, the bit rate of the EFM signal is slow. In order to reduce the frequency of the signal VCOCK, the value of the first variable M is adjusted downward to 97. In addition, if the maximum value output from the maximum value generation unit 80 is less than the second reference value REF2 when the value of the first variable M is 98, the bit rate of the EFM signal is fast. In order to increase the frequency of the signal VCOCK, the value of the first variable M is adjusted upward to 99. A detailed description of the variable control unit 90 will be described later with reference to FIG. 4.

On the other hand, in the case of DVD, 14T, which is the longest duty MAXT, is generated once in the frame sync period, but in the case of CD, 11T is generated twice in succession. Therefore, in the case of CDP, 11T, which is generated twice consecutively without counting 11T, which is the longest duty MAXT, is counted, that is, 22T is counted to increase accuracy in the case of CDP.

FIG. 4 is a block diagram showing a second embodiment according to the present invention of the adaptive clock controller 30 shown in FIG. The clock controller 30 according to the second embodiment includes a counter 46, a maximum value generator 60, and a variable controller 62. Preferably, the counter unit 46 includes a first counter 40, a second counter 42, and a selector 44, and the maximum value generating unit 60 includes a maximum value extracting unit 50, And a register 52 and a low pass filter 54. The variable control unit 62 includes a comparator 56 and an up / down counter 58.

5A to 5J are timing diagrams illustrating a process of changing the first variable M in the apparatus shown in FIG. 4. FIG. 5 (a) shows the EFM signal, FIG. 5 (b) shows the output of the first counter 40, FIG. 5 (c) shows the output of the second counter 42, and FIG. 5 (d) Denotes the output of the selector 44, FIG. 5 (e) shows the output of the maximum value extracting section 50, FIG. 5 (f) shows the control signal C, and FIG. 52 (h) shows the second control signal C2 output from the comparator 56, and FIG. 5 (i) shows the third control signal C3 output from the comparator 56. FIG. 5 (j) shows the first variable M output from the up / down counter 58, respectively. The input / output results shown in FIGS. 5 (a) to (j) have a reference frequency (FIN, see FIG. 2) of 16.9344 MHz, a second variable P of 48, and an initial value of the first variable M. Is the result when M0 is 98, Nr, which is the resolution of the digital PLL (32, see FIG. 2) is 8, and alpha is 4.

Referring to FIG. 4, the counter 46 counts the control clock signal VCOCK for each section in which the rising edge of the EFM signal rises to obtain the first count value CNT1, and the next falling edge of the falling edge. The control clock signal VCOCK is counted for each section in which an edge occurs to obtain a second count value CNT2. Here, consecutive 11T-11T may be represented in the form of '0000000000011111111111' or may be represented in the form of '1111111111100000000000'. Therefore, in order to count consecutive 1T-11T, the control clock signal VCOCK must be counted in both the rising edge of the EFM signal and the falling edge of the falling edge. In addition, the counter unit 46 selectively outputs the first count value CNT1 or the second count value CNT2 in response to the selection signal S. FIG.

In more detail, the first counter 40 of the counter unit 46 counts the control clock signal PLCK at the rising edge of the EFM signal shown in FIG. 5A, and counts the next rising edge when the next rising edge is generated. Is output to the selector 44, is reset, and the control clock signal PLCK is counted again. That is, the first counter 40 counts the control clock signal VCOCK during the next rising edge period from the rising edge of the EFM signal, and counts the counted value as the first count value CNT1 shown in FIG. Output The second counter 42 counts the control clock signal PLCK at the falling edge of the EFM signal shown in FIG. 5A, outputs the counted value to the selector 44 when the next falling edge is generated, and resets it. The control clock signal PLCK is counted again. That is, the second counter 42 counts the control clock signal VCOCK during the next falling edge section from the falling edge of the EFM signal, and the counted value is the second count value CNT2 as shown in FIG. ) The selector 44 accepts the first and second count values CNT1 and CNT2 output from the first and second counters 40 and 42, and responds to the selection signal S as shown in FIG. 5 (d). As described above, the first or second count values CNT1 and CNT2 are selectively output. Here, the selection signal S uses an EFM signal. That is, if the EFM signal is high level, the first count value CNT1 output from the first counter 42 is selected and output. If the EFM signal is low level, the second count value CNT2 output from the second selector 40 is selected. Select).

The maximum value generator 60 extracts the maximum value among the values output from the counter 46 for a predetermined period in response to the first control signal C1, and outputs the extracted maximum value.

In more detail, the maximum value extracting section 50 of the maximum value generating section 60 is the counter section (d) shown in FIG. 5 (d) during one period of the first control signal C1 shown in FIG. 46), and extracts the maximum of them. In the method, as shown in Fig. 5 (e), the maximum value extracting section 50 stores the first 40 output from the counter section 46, and then stores 128 which is a value larger than 40, and then Can extract the maximum value of the output values of the counter unit 46 generated during one period of the first control signal C1 by storing 164, which is a value larger than 128. When the first control signal C1 is enabled, the maximum value extractor 50 outputs the stored maximum value to the register 52, resets it, and then generates it for the next one period of the first control signal C1. The maximum value of the output values of the counter unit 46 is extracted and output to the register 52. In this case, as described above, extracting the maximum value detects the frame synchronization period which is the longest duty period of 11T-11T. Therefore, the frame synchronization period must be included in the period of the first control signal C1 extracting the maximum value. do. The register 52 latches the maximum value output from the maximum value extracting section 50 as shown in FIG. 5 (g), and the LPF 54 provides stability to the maximum value latched in the register 52. For the sake of brevity, it may be omitted.

If the maximum value output from the maximum value generator 60 is greater than the first reference count value REF1, the variable controller 62 decreases the value of the first variable M by a predetermined value, and the maximum value is the second reference. If it is smaller than the count value REF2, the value of the first variable M is adjusted by a predetermined value. Here, the first reference value REF1 is (22 * Nr + α) and the second reference value REF2 is (22 * Nr−α). For example, if the maximum value output from the maximum value generator 80 is greater than the first reference value REF1 when the value of the first variable M is 98, the bit rate of the EFM signal is slow. In order to reduce the frequency of the signal VCOCK, the value of the first variable M is adjusted downward to 97. In addition, if the maximum value output from the maximum value generation unit 80 is less than the second reference value REF2 when the value of the first variable M is 98, the bit rate of the EFM signal is fast. In order to increase the frequency of the signal VCOCK, the value of the first variable M is adjusted upward to 99.

In more detail, the comparator 56 compares the maximum value generated from the maximum value generator 60 with the first and second reference values REF1 and REF2 and their sizes, and according to the comparison result, the second and third values. Generate control signals C2 and C3. That is, the comparator 56 must adjust the value of the first variable M up / down by a predetermined value when the maximum value is larger than the first reference count value REF1 or smaller than the second reference count value REF2. As shown in FIG. 5 (h), the second control signal C2 is set to a high level. In addition, the comparator 56 compares the maximum value with the third reference count value REF3 and indicates whether to adjust the value of the first variable M up or down according to the comparison result. ) Here, the third reference count value REF3 is the count value 22 * Nr in the ideal case. For example, as shown in FIG. 5I, when the maximum value is smaller than the third reference count value REF3, the third control signal C3 is set to the high level in order to adjust the first variable M upward. If the maximum value is larger than the third reference count value REF3, the third control signal C3 is set at the low level to adjust the first variable M downward.

The up / down counter 58 adjusts the value of the first variable M in response to the second and third control signals C2 and C3 output from the comparator 56. At this time, the up / down counter 58 is initially set to M0, which is the initial value of the first variable M. FIG. The up / down counter 58 maintains the current first variable value M when the second control signal C2 is at a low level. On the other hand, when the second control signal C2 becomes high, the value of the first variable M is increased or decreased in accordance with the third control signal C3. That is, the up / down counter 58 is the current level when the second control signal C2 is high level and the third control signal C3 is high level, as shown in FIGS. A value up counted by a predetermined value (for example, 1) from the first variable M is output. In addition, the up / down counter 58 has a predetermined value (for example, 1) in the current first variable M when the second control signal C2 is high level and the third control signal C3 is low level. Output the down counted value.

As described above, as the bit rate of the EFM signal is changed by the rotational speed of the disk, the frequency of the control clock signal VCOCK for controlling the operation of the digital PLL 32 is converted into the frequency of the digital PLL 32. By adaptively varying to fit within, the digital PLL 32 can accurately follow the EFM signal and restore the optimal reproduction clock signal.

Meanwhile, in order to deal with a defect, the maximum value may be set to a maximum value and a minimum value that can be accommodated, and may be ignored when out of the range.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the clock recovery circuit having the wide frequency introduction range according to the present invention uses the frequency of the control clock signal for controlling the operation of the digital PLL 32 according to the bit rate of the EFM signal. By adaptively varying to fit within, the digital PLL 32 can follow the EFM signal accurately to restore the optimal reproduction clock signal.

Claims (3)

A reproduction clock recovery circuit having a wide frequency introduction range for detecting an EFM signal in an optical disc reproduction system and recovering a reproduction clock signal used for EFM demodulating the detected EFM signal, A frequency synthesizer which receives a reference clock signal having a constant period, a first variable, and a second variable and generates a control clock signal by the following equation; VCOCK = FIN * M / P Where VCOCK represents the control clock signal, FIN represents the reference clock signal, M represents the first variable, and P represents the second variable. A digital phase locked loop which receives the control clock signal and the EFM signal and generates a reproduction clock signal for demodulating the EFM signal; And The initial value of the first variable is determined according to the resolution of the digital phase locked loop and the speed of the disc, the EFM signal and the control clock signal are received, and the control clock signal is adapted according to the bit rate of the EFM signal. And a adaptive clock controller for controlling the first variable to be variable. The method of claim 1, wherein the adaptive clock control unit A counter for counting the control clock signal at every high and low period of the EFM signal; A maximum value generator for extracting a maximum value among the values counted by the counter for a predetermined period in response to a control signal and outputting the extracted maximum value; And If the maximum value output from the maximum value generator is greater than a reference count value, the value of the first variable is made smaller by a predetermined value. If the maximum value is less than the reference count value, the value of the first variable is increased by a predetermined value. A clock recovery circuit having a wide frequency introduction range, characterized in that it comprises a variable control unit for greatly controlling. The method of claim 1, wherein the adaptive clock control unit The first clock value is calculated by counting the control clock signal at each rising edge of the EFM signal and a second count is counted at each falling edge of the next falling edge at the falling edge. A counter unit for obtaining a value and outputting the first count value or the second count value in response to a selection signal; A maximum value generator for extracting a maximum value among the values output from the counter for a predetermined period in response to a control signal, and outputting the extracted maximum value; And If the maximum value output from the maximum value generator is greater than a reference count value, the value of the first variable is made smaller by a predetermined value. If the maximum value is less than the reference count value, the value of the first variable is increased by a predetermined value. A clock recovery circuit having a wide frequency introduction range, characterized in that it comprises a variable control unit for greatly controlling.