JPH0758736A - Timing regenerating device - Google Patents

Abstract

PURPOSE:To provide a device which is not affected by a data pattern and generates a stable clock even for a differentiation detection signal and suits to IC-implementation as to a timing regenerating device which detects a bit phase from a digital regenerated signal. CONSTITUTION:A phase comparator as a constituent element of the timing regenerating device consists of a T/2 edge pulse generating circuit 14 (24), an edge trigger RS-FF 15 (25), and an arithmetic circuit 16 (26) and generates an error signal corresponding to time differences only between respective edges of input data and edges of a clock generated by a voltage-controlled oscillator 9. For a signal as an object of PR(1, 0, -1) detection, two comparing circuits 13 and 23 detect edge data and compare their phases with a clock separately and an adding circuit 18 adds the phase errors, so that the accurate clock is generated without being affected by the data pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing reproduction for detecting a bit phase from a signal reproduced from a magnetic recording medium of a digital magnetic recording / reproducing apparatus for converting a video signal and an audio signal into a digital signal and recording / reproducing. It relates to the device.

[0002]

2. Description of the Related Art Conventionally, in a digital magnetic recording / reproducing apparatus, a signal reproduced from a magnetic recording medium via a magnetic head is input to an equalizer (hereinafter referred to as EQ) circuit to correct frequency characteristics deteriorated by recording / reproducing. To do.

The frequency characteristic correction described above differs for each digital signal to be recorded. For example, in a D1 digital VTR, a scrambled-NRZ code (hereinafter S-NR
Z) is used.

In the case of S-NRZ, an EQ circuit corrects the reproduced signal to a Nyquist characteristic with a roll-off rate of 0.3 to 1 and outputs a binary eye pattern, and a comparison circuit identifies the binary eye pattern. Thus, the reproduced digital signal is detected. Here, the EQ circuit is composed of an integrating circuit and a transversal filter (integral detection).

By the way, in recent years, in order to achieve high-density digital recording, interleaved-NRZI which is less susceptible to interference of crosstalk signals reproduced from adjacent tracks.
The code (hereinafter referred to as I-NRZI) has been attracting attention.

In the case of I-NRZI, the EQ circuit uses PR
The frequency is corrected to (1, 0, -1), the ternary eye pattern is output, and the reproduced digital signal is detected by identifying the ternary eye pattern by the two comparison circuits. In this case, E
The Q circuit does not include the integral characteristic and positively utilizes the differential characteristic of the magnetic recording system.

Next, a timing reproduction device is used to generate a reproduction clock (hereinafter, simply referred to as a clock) indicating a bit phase from these reproduction digital signals.

The technical contents described above are described in detail, for example, in "Digital Video Recording Technology", published by Nikkan Kogyo Shimbun, by Yoshizumi Eto et al.

FIG. 7 shows a block diagram of a main part of a conventional timing reproducing apparatus. The digital signal reproduced through the magnetic head 1 is corrected by the EQ circuit 2 for the frequency characteristic deteriorated during recording and reproduction, and a partial response waveform (particularly, here, I-NRZI modulation is assumed for three-value detection). Will be used to explain PR (1, 0, -1) detection used together with the comparison A, B circuits 13,
23 is output. Since PR (1, 0, -1) is assumed here, the outputs of the comparison A, B circuits 13 and 23 are EX-O by the EX-OR circuit (exclusive OR circuit) 43.
By taking R (exclusive OR), it can be converted into binary data. In addition, the timing reproduction device 44 includes the tank circuit 4
5, multiplication circuit 46, low-pass filter (hereinafter referred to as LPF) 8, voltage-controlled oscillation circuit (hereinafter referred to as VCO) 9
In this configuration, the clock component is extracted from the binary data and the bit timing is generated by locking the phase with the reproduced signal (for example, Shoji Kaneko's "PCM Communication Technology", Industrial Publication).

[0010]

When the timing reproducing device is realized by an IC, as shown in FIG. 7, a phase comparator,
A PLL circuit composed of LPF and VCO is suitable.

As the phase comparison circuit, the edge comparison type is more advantageous than the multiplication circuit type shown in FIG. 7 in terms of the pull-in range and the stability of the lock phase. This is because in the case of using an analog multiplier or an EX-OR circuit, the phase comparison characteristic has a triangular wave comparison characteristic, and the straight line section is half that of the edge comparison type. Further, since the phase comparison output is compared with the reference voltage, there is a drawback that the lock phase changes when the reference voltage changes or the frequency of the input data changes.

FIG. 8 shows a conventional phase comparator which is widely used as a phase comparator for edge comparison.

However, since this type of phase comparator detects not only the phase difference but also the frequency, it cannot be used alone for a data signal having a missing edge, and a tank circuit or a replacement circuit for compensating for the missing edge is used. I need. In addition, in the method using the tank circuit, if the loss of the signal edge continues for a long time, a phase shift occurs due to fluctuations in the input frequency, variations in the resonance frequency of the tank circuit, and temperature characteristics.

The present invention has been made in view of the above points, and has a simple structure and can detect data regardless of a data pattern for binary detection, ternary detection, or differential detection and integral detection. The purpose of the present invention is to provide a timing recovery device that generates an error signal according to the time difference between each edge and the nearest clock edge to control the clock frequency and phase, and holds the clock phase in the part where there is no edge. There is.

[0015]

In order to achieve the above object, the timing reproducing apparatus of the present invention generates an input data signal input means having a clock cycle of approximately T and a clock synchronized with the input data signal. Voltage controlled oscillating means and a width T /
T / 2 edge pulse generating means for obtaining two pulses, SR flip-flop means for using the change point of the input data signal as a set signal and one change point of the output of the voltage controlled oscillator means as a reset signal, and the above T / 2-edge pulse generation means output signal and arithmetic operation means for arithmetically operating the SR flip-flop means output signal, and unnecessary components are removed from the output of the arithmetic means, and the output controls the oscillation frequency and phase of the voltage controlled oscillation means. And low-pass filter means.

[0016]

With the above structure, the timing reproducing apparatus of the present invention calculates the T / 2 edge pulse generating means output signal and the SR flip-flop means output signal by the calculating means to obtain T /
A signal corresponding to the phase difference is output only between the trailing edge of the output signal of the two-edge pulse generation means and one change point of the output of the voltage controlled oscillation means.

Further, for the partial response waveform premised on ternary detection, for the outputs of the two comparison means,
By providing T / 2 edge pulse generating means, SR flip-flop means, and calculating means respectively, and adding and averaging the outputs of the two calculating means, the property of the ternary eye pattern, that is, the upper and lower eye patterns are Due to the nature that the phase errors output from the two PCs are present in pairs and have the same magnitude and opposite phase error directions with respect to the true bit synchronization position to be detected, The position can be detected accurately.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the timing reproducing apparatus of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a main part of a timing reproducing apparatus according to the first embodiment of the present invention, which is an example in which a clock signal is reproduced by a binary detection signal.

The digital signal reproduced through the magnetic head 1 is equalized by the EQ circuit 2 into a waveform on the premise of binary detection. In the comparison circuit 3, the EQ circuit 2
The identification level is provided at the center level of the signal output from
Output binary data.

The T / 2 edge pulse generation circuit 4 generates a constant pulse having a width of approximately T / 2 and falling at a change point of the output of the comparison circuit 3 (that is, both rising and falling edges).

Next, the edge trigger SR-flip-flop (hereinafter referred to as SR-FF) 5 is set at the front edge of the output of the T / 2 edge pulse generation circuit 4, and the VCO 9 delayed by the delay correction circuit 10 for a predetermined time. Reset on one edge of output. The arithmetic circuit 6 receives the output of the T / 2 pulse generation circuit 4 and the output of the edge trigger SR-FF5,
A signal corresponding to the phase difference (time difference) of the rear edges of both signals is generated. The output of the arithmetic circuit 6 which is a digital quantity is connected to the charge pump circuit 7 and converted into an analog quantity. The LPF 8 integrates the output of the charge pump circuit 7 to remove unnecessary components, and controls the oscillation frequency and phase of the VCO 9 with the output.

The delay correction circuit 10 corrects the data edge position being delayed by T / 2 in the T / 2 edge pulse generation circuit 4, and particularly when the IC is formed, the T / 2 edge pulse generation circuit 4 is used. When the delay characteristics of the delay correction circuit 10 are the same, variations in delay characteristics and temperature characteristics are completely compensated. Furthermore, by adjusting the delay time of the delay compensating circuit 10, the timings of data and clock can be perfectly matched.

As a result, a clock whose timing matches the data output from the output terminal 11 is output from the output terminal 12.

FIG. 2 is a waveform diagram showing the operation timing of the timing reproducing apparatus in the first embodiment.

In FIG. 2, (a) is a binary eye pattern output from the EQ circuit 2, and (b) is a comparison circuit 3.
Output from the T / 2 edge pulse detection circuit 4, (d) output of the VCO 9 delayed by the delay correction circuit 10, (e) output of the edge trigger RS-FF 5, (f) ) And (g) are outputs of the arithmetic circuit 6, and when the rear edge of the edge trigger RS-FF5 output is behind the rear edge of the output of the T / 2 edge pulse detection circuit 4, an output is generated at (f), An output is generated when the rear edge of the output of the edge trigger RS-FF5 is before the rear edge of the output of the T / 2 edge pulse detection circuit 4 (g).

FIG. 3 shows a concrete circuit example of the edge trigger SR-FF5 and the arithmetic circuit 6, and the edge trigger SR-F.
F5 is a delay inverter (having a capacity if necessary)
And an edge detection circuit using NAND and two NANDs
The SR-FF according to the above, and the arithmetic circuit 6 can basically be constituted by an inverter for inverting one polarity and an AND circuit.

However, an unnecessary output appears in one output of the arithmetic circuit 6 due to the delay of the leading edge of the T / 2 edge pulse by the edge trigger SR-FF5. The leading edge of the edge pulse is delayed.

Here, the AND circuit of the arithmetic circuit 6 is SR-
Both inputs are High, H only when the trailing edge of the FF output is after the trailing edge of the output of the edge pulse generation circuit.
The NOR circuit outputs High (f output), and the NOR circuit outputs Hi only when both the rear edge of the SR-FF output is before the rear edge of the output of the edge pulse generation circuit.
It becomes gh and High and outputs High (g output).

FIG. 4 is a block diagram of a main part of a timing reproducing apparatus according to the second embodiment of the present invention, which is an example in which a clock signal is reproduced by a ternary detection signal.

The digital signal reproduced through the magnetic head 1 is detected by the EQ circuit 2 in three values, that is, PR.
The waveform is equalized assuming (1, 0, -1) detection. In the comparison A circuit 13 and the comparison B circuit 23, discrimination levels are provided above and below the center level of the signal output from the EQ circuit 2, respectively discriminates and outputs two binary data.

T / 2 edge pulse detection circuit 1 having the same structure
Reference numerals 4 and 24 denote change points of the outputs of the comparison A circuit 13 and the comparison B circuit 23 (that is, both rising and falling edges).
A pulse having a width of approximately T / 2, which falls at, is generated.

Next, the edge trigger SR-FF 15, 25
Are set at the front edges of the outputs of the T / 2 edge pulse generation circuits 14 and 24, respectively, and are reset at one edge of the VCO 9 output delayed by the delay correction circuit 10 for a predetermined time. The arithmetic circuits 16 and 26 output the T / 2 edge pulse generation circuits 14 and 24 and the edge trigger SR-FF 15 and 25, respectively.
The output is used as an input and a signal is generated according to the phase difference (time difference) of the rear edges of both signals. The outputs of the arithmetic circuits 16 and 26, which are digital quantities, are the charge pump circuit 1.
7 and 27, converted into an analog amount, and added in an analog manner in the adder circuit 18. LPF8 is addition circuit 1
8 outputs are integrated to remove unnecessary components, and VCO
9 controls the oscillation frequency and phase.

The T / 2 edge pulse generation circuit 14,
As in the case of FIG. 1, the delay characteristic is compensated by the delay correction circuit 10 according to the delay characteristic of 24.

As a result, a clock whose timing matches the data output from the output terminal 11 via the data detection circuit 19 is output from the output terminal 12.

FIG. 5 is a waveform diagram showing the operation timing of the timing reproducing apparatus in the second embodiment.

In FIG. 5, (a) is a ternary eye pattern output from the EQ circuit 2, and (b1) and (b2).
Is the data output from the comparison A circuit 13 and the comparison B circuit 23, (c1) and (c2) are the outputs of the T / 2 edge pulse detection circuits 14 and 24, and (d) is the VCO 9 delayed by the delay correction circuit 10. Outputs, (e1) and (e2) are outputs of the edge trigger RS-FFs 15 and 25, (f1) and (g1) are outputs of the arithmetic circuit 16, and (f2) and (g2) are arithmetic circuits 26.
Is the output of.

The data shown in FIG. 9A is (1, 0, -1,
1, 0, -1) is shown. In the case of a three-valued differential signal, change from -1 to 1 through 0 and -1 to 1, 1 to -1
There is a non-zero change. In the case of a change not involving 0, the interval between the edges detected by the comparison A circuit 13 and the comparison B circuit 23 is T / 2 or less. Therefore, the T / 2 edge pulses overlap in the same time. Further, depending on the conditions, (f1), (f2) and (g1), (g2) are simultaneously output. In order to solve this problem, a T / 2 edge pulse generator circuit, an edge trigger SR-FF, and an arithmetic circuit are used.
The problem is solved by providing a pair and adding the obtained outputs in an analog manner.

The figure shows the state of accurate phase synchronization,
It can be seen that the average values of the outputs of (f1 + f2) and (g1 + g2) are equal, and when they are averaged by the charge pump circuit and the LPF, the error signal becomes zero and is in a stable state.

Therefore, according to the timing reproducing apparatus of the present invention, an accurate phase error can always be obtained.

FIG. 6 is a block diagram showing the main part of a timing reproducing apparatus according to the third embodiment of the present invention, which is I-NRZ.
This is a configuration example in which the data and the clock phase can be accurately matched with respect to I.

In FIG. 6, reference numerals 31 and 32 are analog delay circuits having a delay amount of T / 2 hours. Where T /
To generate the two-edge pulse, the comparison A circuits 33 and 34 and the comparison B circuits 35 and 36 are provided for the input and output of the analog delay circuit 31, and the outputs of the comparison A circuits 33 and 34 are EX-ORed.
-OR circuit 37, comparison B circuits 35 and 36 outputs EX-O
This is performed by the EX-OR circuit 38 for R.

By the way, in the case of I-NRZI, it is necessary to detect the data by adding the EQ circuit output and the signal delayed by T time. The adder circuit 39 adds the output of the EQ circuit 2 and the signals delayed by the time T in the delay circuits 31 and 32, detects three values in the comparison A and B circuits 40 and 41, and the EX-OR circuit 4
It is converted into binary data at 2 and output from the output terminal 12.

In this case, since the data and the T / 2 edge pulse are delayed by T / 2 time with respect to the output of the EQ circuit 2, the timings match and no correction is required.

[0045]

As described above, according to the timing reproducing apparatus of the present invention, regardless of whether the form of the reproduced data signal is binary detection, ternary detection, differential detection, or integral detection, a data pattern is generated. Regardless, an accurate phase error signal according to the time difference between the signal edge and the closest clock edge can be obtained, and a stable clock can be generated. Also, it is suitable for integration into an IC, and almost all the phase comparison parts can be built in the IC.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part showing a configuration of a timing reproduction device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation timing of the timing reproducing apparatus in the first embodiment.

FIG. 3 is a block diagram showing an internal configuration of a T / 2 edge pulse generation circuit and an arithmetic circuit in the first embodiment.

FIG. 4 is a principal block diagram showing the configuration of a timing reproducing device according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram showing the operation timing of the timing reproducing apparatus in the second embodiment.

FIG. 6 is a principal block diagram showing the configuration of a timing reproduction device according to a third embodiment of the present invention.

FIG. 7 is a principal block diagram showing the configuration of an example of a conventional timing reproduction device.

FIG. 8 is a circuit diagram showing an example of a conventional edge comparator type phase comparator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 magnetic head 2 EQ circuit 3 comparison circuit 4,14,24 T / 2 edge pulse generation circuit 5,15,25 edge trigger SR-FF circuit 6,16,26 arithmetic circuit 7,17,27 charge pump circuit 8 LPF 9 VCO 10 delay circuit 11 clock output terminal 12 data output terminal 13, 33, 34, 40 comparison A circuit 18, 39 adder circuit 19 data detection circuit 23, 35, 36, 41 comparison B circuit 31, 32 analog delay circuit 37 , 38, 42, 43 EX-OR circuit 44 Timing recovery device 45 Tank circuit 46 Multiplier circuit

Claims (4)

[Claims] 1. An input data signal input means having a clock cycle of approximately T, a voltage controlled oscillating means for generating a clock synchronized with the input data signal, and a width T having a change point of the input data signal as a front edge. T / 2 edge pulse generating means for obtaining a pulse of / 2, SR flip-flop means for setting a change point of the input data signal as a set signal and one change point of the output of the voltage controlled oscillation means as a reset signal, The phase difference between the trailing edge of the T / 2 edge pulse generating means output signal and one change point of the voltage controlled oscillation means output is calculated by calculating the output signal of the T / 2 edge pulse generating means and the output signal of the SR flip-flop means. And an oscillating frequency and a phase of the voltage controlled oscillating means by removing unnecessary components from the output of the operating means. The timing reproducing apparatus comprising: the low-pass filter means for controlling, that is constructed from. 2. A clock cycle reproduced from a magnetic recording medium of a digital magnetic recording / reproducing apparatus for converting a video signal and an audio signal into a digital signal and recording / reproducing the signal is approximately T.
Equalizer means for equalizing a data signal to be a partial response waveform on the premise of ternary detection, voltage controlled oscillating means for generating a clock for synchronizing with the data signal, and first, second identifying the output of the equalizer means. And the first and second T / s for obtaining a pulse having a width of T / 2 with the changing points of the outputs of the first and second comparing means as front edges.
The two edge pulse generation means and the first and second change points of the outputs of the first and second comparison means are set signals, and one change point of the output of the voltage controlled oscillation means is a reset signal. SR flip-flop means, the first and second T / 2 edge pulse generating means output signals, and the first and second SR flip-flop means output signals are calculated, and T / 2 edge pulse generating means output signals The outputs of the first and second calculating means and the first and second calculating means for outputting a voltage according to the phase difference between the trailing edge and one of the changing points of the output signal of the voltage controlled oscillation means are added. A timing recovery device comprising: an addition means; and a low-pass filter means for removing an unnecessary component from the output of the addition means and controlling the oscillation frequency and phase of the voltage controlled oscillation means with the output. Place 3. The T / 2 edge pulse width variation is compensated by providing delay means for delaying the output of the voltage controlled oscillator means to be a reset signal of the SR flip-flop. The timing playback device described in. 4. The T / 2 edge pulse generation means includes a first analog delay device for delaying the output of the equalizer means for T / 2 time, and a first and a third detection device for detecting an input signal of the first analog delay device. Second comparing means, third and fourth comparing means for ternary detecting the output signal of the first analog delay device,
A first exclusive OR means for taking an exclusive OR of the outputs of the first and third comparing means, and a second exclusive OR for taking an exclusive OR of the outputs of the second and fourth comparing means. Second analog delay means output for further delaying the input signal of the first analog delay element and the output signal of the first analog delay element by T / 2 time with respect to the clock output timing. 4. The timing reproducing device according to claim 3, wherein the timing reproduction device matches the data output obtained from the addition signal of.