KR20000008832A - Phase lock loop system for photo-disk - Google Patents

Abstract

PURPOSE: A phase lock loop(PLL) system for photo-disk is provided to reduce an oscillating frequency by using an eight to fourteen modulation(EFM) generating circuit having a header signal and a wobble signal. CONSTITUTION: The PLL system comprises a frequency detecting section generating pulse width modulation signal for up and down an oscillating frequency of a voltage control oscillator if an error is happened after counting a frame synchronization pattern period of the EFM signal input from the photo-disk as phase synchronization clock and comparing with a fixed count value, and a micro-processor applying the pulse width control signal to the frequency detecting section for control the pulse width for the pulse width to meet the error.

Description

Phase Synchronous Loop System for Optical Discs

The present invention relates to a phase locked loop system for an optical disc, and more particularly, to a phase locked loop system for lowering an oscillation frequency of a voltage controlled oscillator.

The optical disc player is one of various optical discs such as CD (Compact Disc), CD-ROM (Compact Disc-Read Only Memory), LD (Laser Disc), MD (Mini Disc), DVD (Digital Video Disc), etc. Refers to a system that plays back information recorded on a disc. In such an optical disc reproducing apparatus, a data phase locked loop (hereinafter referred to as "PLL") is an essential element in reproducing data recorded on an optical disc.

1 shows a block configuration of a conventional PLL system for an optical disc to which the present invention is applied. Voltage control oscillator (hereinafter referred to as "VCO") 100 is an oscillator that varies the oscillation frequency by a predetermined input voltage. The microcomputer 102 generates a predetermined pulse width control signal for adjusting the pulse width of the pulse width modulation signal and applies it to the frequency detector 104. The frequency detector 104 adjusts the length of the frame synchronization pattern of the EFM signal, which is a predetermined data stream signal reproduced and input from the optical disk, from the VCO 100. The frequency of the EFM signal is detected by counting with a clock PLCK. In the case of CD (Compact Disc), if the interval of 11 sections of the phase synchronization clock maintains high or low state, a frame synchronization pattern is detected. In case of DVD (Digital Versatile Disc), the phase synchronization clock is detected. The frame synchronization pattern is detected when the interval between 14 sections of the frame is kept high or low. The frequency detection unit 100 counts the frame synchronization pattern as the phase-locked clock at every frame synchronization, and the reference count preset to the frame synchronization pattern is counted. Compared with the value, if an error occurs, a pulse width modulation signal for adjusting the oscillation frequency of the VCO 100 is generated according to the pulse width control signal of the microcomputer 102.

Hereinafter, the operation of each of the frequency detector 104 and the PLL system will be described in detail with reference to DVD. When the interval of synchronization is smaller than 14 sections of the phase synchronization clock, the phase synchronization clock is performed. Since the oscillation is slow, the charge pump is generated by generating a pulse width modulated signal (hereinafter referred to as "frequency up adjustment signal") (UP) for frequency up adjustment in which the pulse width is set to compensate for this in order to speed it up. (106). Then, the charge pump 106 “turns on” the first switch 200 as shown in FIG. 2 by using the frequency up adjustment signal UP for speeding up the oscillation frequency of the VCO 100 as a switching signal. The voltage VDD is supplied to the VCO 100 for a time corresponding to the pulse width of the frequency up adjustment signal UP to increase the input voltage of the VCO 100. On the other hand, if the interval of synchronization is greater than 14 sections of the phase synchronization clock, the phase synchronization clock is fast, so that the frequency detector 104 modulates the pulse width for frequency down adjustment in which the pulse width is set to compensate for this. A signal (hereinafter referred to as "frequency down adjustment signal") DOWN is generated and applied to the charge pump 106. Then, the charge pump 106 "turns on" the second switch 202 by using the frequency down adjustment signal DOWN as a switching signal as in the case where the frequency up adjustment signal UP is applied. As shown, the input voltage of the VCO 100 is discharged by a time corresponding to the pulse width of the frequency down adjustment signal DOWN, thereby lowering the input voltage of the VCO 100. In addition, if the synchronization interval coincides with the 14 sections of the phase synchronization clock, it is determined that the oscillation frequency of the phase synchronization clock is properly adjusted, and the frequency detector 104 multiplexes the frequency lock signal F_lock with the multiplexer 110. The input voltage of the VCO 100 is controlled so as not to be changed by the frequency adjustment signal of the frequency detector 104. The multiplexer 110 selectively applies the frequency adjustment signal generated from the frequency detector 104 and the phase detector 112 to the charge pump 106. The low pass filter (hereinafter referred to as "LPF") 108 is input in the form of a pulse to the VCO 100 through the charge pump 106 according to the pulse width modulation signal generated from the frequency detector 104. The voltage VDD is filtered and supplied to the VCO 100. The phase detector 112 checks whether the phase of the phase synchronization clock input from the VCO 100 matches the phase of the input EFM signal, and is a pulse width modulated signal set to a predetermined pulse width like the frequency detector 104. When the frequency up or down adjustment signal is generated and the phase of the phase synchronization clock PLCK is slower than the phase of the EFM signal as in the time point T1 of FIG. 3, the pulse width of the frequency up adjustment signal UP is generated. By setting the width to wide to control the charge pump 106 to increase the input voltage supplied to the VCO (100). On the other hand, when the phase of the phase synchronization clock PLCK is earlier than the phase of the EFM signal as in the point T3 of FIG. 3, the charge pump 106 is generated by setting a narrow pulse width of the frequency up adjustment signal UP. Control to lower the input voltage supplied to the VCO 100. The half frequency divider 114 is oscillated twice from the VCO 100 for a more precise count of the input EFM signal frame synchronization pattern for frequency detection in the conventional phase synchronization loop circuit frequency detector 104. The frequency of the clock is divided by the original frequency and applied to the phase detector 112.

4 is a flowchart illustrating a process of detecting a frequency of an EFM signal input from a conventional frequency detector. Here, the CD-ROM has a synchronization signal of 11T section once every 256 edges of the EFM signal, and the DVD-ROM and DVD-RAM have a synchronization signal of 14T section once every 512 edges. Therefore, the frequency detector 104 is set to detect 11T synchronization signals for every 256 edges of the input EFM signal when the optical disc is a CD-ROM, and 14T synchronization signals every 512 edges for a DVD-ROM or DVD-RAM. It is set to detect. "T" means one clock period of the phase locked clock. The frequency detector 104 is provided inside and detects the 11T or 14T synchronization signal by using a counter for counting the frame synchronization pattern of the EFM signal using a phase synchronization clock. As shown, a count is performed when the rising edge of the phase locked clock oscillated at twice the frequency of the original phase locked clock. Therefore, the phase-locked normal count value of the synchronization signal of the CD-ROM is preset to 22T and the DVD-ROM and DVD-RAM are set to 28T. In the following description, a case where the optical disc is a DVD-ROM or a DVD-RAM is described for convenience of explanation.

First, the frequency detector 104 counts the edges of the input EFM signal using the double phase oscillation clock applied from the VCO 100 in operation 400. Next, the frequency detector 104 proceeds to step 402 to check whether the edge of the EFM signal corresponds to the 512th step. At this time, if the edge of the EFM signal is not the 512th frequency detector 104 returns to step (400) and performs steps (400) to (402) again. On the contrary, if the edge of the EFM signal is 512th in step 402, the frequency detector 104 proceeds to step 404 to output the maximum count value Tmax among the count values, and is set in advance in step 406. Check whether the count value of the synchronization signal, that is, equal to 28T. At this time, if the maximum count value Tmax among the inter-edge count values of the EFM signal output from the counter of the frequency detector 104 is equal to the reference count value 28T preset to the synchronization signal, that is, the synchronization is corrected. Operation 104 proceeds to step 408 and outputs a frequency lock signal F_lock for locking the frequency to the multiplexer 110. In operation 410, the frequency detector 104 controls the multiplexer 110 such that the frequency up or down adjustment signal of the phase detector is applied to the charge pump. Accordingly, only the frequency up or down adjustment signal output from the phase detector 112 among the frequency up or down adjustment signals input to the multiplexer 110 is applied to the charge pump 106 to control the input voltage of the VCO 100. Done. On the contrary, if the maximum count value Tmax is not equal to the reference count value 28T preset in the synchronization signal, the frequency detector 104 performs the step 412 in step 406. The process proceeds to to check whether the maximum count value Tmax in which the synchronization signal is counted among the inter-edge count values of the EFM signal is larger than the reference count value 28T preset in the synchronization signal. At this time, if the maximum count value Tmax in which the synchronization signal is counted among the edge-to-edge count values of the EFM signal is larger than the reference count value 28T preset in the synchronization signal, the oscillation frequency of the VCO 100 is fast, and thus the frequency detection unit ( In step 414, the frequency down adjustment signal DOWN is applied to the charge pump 106 through the multiplexer 110 to lower the input voltage of the VCO 100. Accordingly, the input voltage of the VCO 100 is adjusted low by the time corresponding to the pulse width of the frequency down adjustment signal DOWN, so that the oscillation frequency of the VCO 100 is adjusted low. On the contrary, if the maximum count value Tmax in which the synchronization signal is counted among the inter-edge count values of the EFM signal is smaller than the reference count value 28T preset in the synchronization signal, the oscillation frequency of the VCO 100 is determined. Since the frequency is slow, the frequency detector 104 proceeds to step 416 and applies the frequency up adjustment signal UP that increases the input voltage of the VCO 100 to the charge pump 106 through the multiplexer 110. Accordingly, the input voltage of the VCO 100 is adjusted high by the time corresponding to the pulse width of the frequency up adjustment signal UP, so that the oscillation frequency of the VCO 100 is adjusted high.

As described above, the frequency of the phase locked clock is doubled from the VCO to be input to the frequency detector for more precise counting in the frequency detector, and the original phase is required in the phase detector that requires the original phase locked clock. A 1/2 divider had to be used to make the synchronous clock. Therefore, since the high frequency from the VCO is to be oscillated, it becomes a problem for a signal having a high frequency as in the case of DVD_ROM 4x speed, and there is a problem that a 1/2 divider must be additionally provided in front of the phase detector.

As described above, the frequency of the phase locked clock is doubled from the VCO to be input to the frequency detector for more detailed counting in the frequency detector, and the original phase is required in the phase detector that requires the original phase locked clock. A 1/2 divider must be used to make the synchronous clock. Therefore, since the high frequency from the VCO is to be oscillated, it becomes a problem for a signal having a high frequency as in the case of DVD_ROM 4x speed, and there is a problem that a 1/2 divider must be additionally provided in front of the phase detector.

Accordingly, an object of the present invention is to provide a PLL system capable of performing frequency detection through fine counting even when oscillating only a frequency corresponding to an original phase locked clock from a VCO.

1 is a block diagram of a conventional phase locked loop system for an optical disc;

2 is a circuit diagram of a conventional charge pump,

3 is a waveform diagram for recovering a phase difference between a conventional phase synchronization clock and an IFM signal;

4 is a processing flowchart at the time of normal frequency detection;

FIG. 5 is an exemplary diagram of counting a frame synchronization pattern section of an EMP signal as a phase synchronized clock oscillated twice;

6 is a block diagram of a phase locked loop system for an optical disc according to an embodiment of the present invention;

7 is a block diagram illustrating a counter unit provided in a frequency detector according to an embodiment of the present invention;

FIG. 8 is an exemplary diagram of counting a frame synchronization pattern section of an EMP signal according to the rising edge and falling edge of the phase synchronization clock according to an embodiment of the present invention;

9 is a block diagram of a phase synchronization loop system for an optical disc according to another embodiment of the present invention;

The present invention for achieving the above object is provided with a counter for counting the phase synchronization clock generated and input from the VCO to both the rising edge and the falling edge of the frequency detection unit of the PLL system for optical discs by using the counter Accurate counting in the frequency detector without counting the oscillation frequency of the VCO by counting every frame sync pattern of a predetermined data stream signal input from the optical disc at the rising and falling edges of the phase-locked clock to detect the frequency It is characterized in that the frequency detection can be made by.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

6 is a detailed block diagram of an optical disc PLL system for playback in accordance with an embodiment of the present invention. In the PLL system of FIG. 6, as the oscillation frequency of the VCO 100 is oscillated to the frequency of the original EFM signal, the 1/2 divider 114 of FIG. 1 is removed, and the frequency detector 600 of FIG. The frequency detection unit 104 has a counter configured to count the frame synchronization pattern of the EFM signal inputted at each of the rising and falling edges of the phase synchronization clock generated from the VCO 100. It is possible to perform precise count operation while using synchronous clock.

FIG. 7 is a detailed block diagram of a counter unit included in a frequency detector of a PLL system capable of performing a count operation on a rising edge of a phase locked clock from a VCO and a falling edge according to an exemplary embodiment of the present invention. Referring to FIG. 7, the first and second counters 700 and 702 are counters for counting a low section of the EFM signal. The first counter 700 outputs a VCO of the low section as shown in FIG. 8. Counting when the rising edge of the phase lock clock of (100), the second counter 702 counts when the falling edge of the phase lock clock generated from the VCO (100) the low-frequency EFM signal as shown in FIG. To print. The first adder 708 is connected to the first and second counters 700 and 702 and is added to the multiplexer 712 by adding the count value of the low section EFM signal output from the first and second counters 700 and 702. Let's do it. Unlike the first and second counters 700 and 702, the third and fourth counters 704 and 706 are counters that count a high section of the EFM signal. The third and fourth counters 704 are shown in FIG. 8. The high section EFM signal is counted when the phase synchronization clock generated from the VCO 100 rises, and the fourth counter 706 generates the high section EFM signal from the VCO 100 as shown in FIG. Counts and outputs the falling edge of the phase-locked clock. The second adder 710 is connected to the third and fourth counters 704 and 706 and adds the count value of the high section EFM signal output from the third and fourth counters 704 and 706 to the multiplexer 712. Output The multiplexer 712 receives the EFM signal as a selection signal and receives the output of the second adder 710 in the high section of the EFM signal, and outputs the first adder in the low section of the EFM signal. 708) output is received.

Therefore, as shown in FIG. 8, the rising edge and the falling edge of the phase-locked clock are detected to count the EFM signal, thereby oscillating the frequency of the phase-locked clock twice as shown in FIG. By precisely counting the frame synchronization pattern of the EFM signal, the oscillation frequency of the phase synchronization clock of the VCO can be lowered, and the phase synchronization clock need not be divided by 1/2 at the front end of the phase detection unit. You don't need a 1/2 divider.

9 is a block diagram of an optical disc PLL system for recording and reproduction according to another embodiment of the present invention. The PLL system of FIG. 9 records a DVD-RAM in the PLL system of FIG. 6 including a frequency detector 600, a phase detector 112, a charge pump 106, an LPF 108, and a VCO 100. And a phase detector 902, a charge pump 904, an LPF 906, a VCO 908, and a 1/186 divider 910 using wobble and header signals for a PLL during recording to correspond to a reproducible optical disc. And 3T-14T generator 900 is provided. The phase detection unit 902 using the wobble and header signals detects a difference between the phases of the phase synchronization clocks oscillated from the VCO 908 and divided into 1/186 with respect to the reference phase of the input wobble signal. Generates a pulse width modulated signal for adjusting the oscillation frequency. The 1/186 frequency divider 910 divides the phase synchronization clock generated from the VCO 908 by 186 by inputting the phase detection unit 902 to the phase detection unit 902 by using the fact that 186 times the wobble signal is equal to the original phase synchronization clock. Used for. The LPF 906 filters the voltage VDD input in the form of a pulse to the VCO 908 through the charge pump 904 according to the pulse width modulated signal generated from the phase detector 902 and supplies the same to the VCO 908. The 3T to 14T generators 900 convert the synchronously adjusted phase-locked clock into 3T, 4T,... Like EFM signals. The pseudo EFM signal PS_EFM is generated by dividing the signal into 14T, and the pseudo EFM signal is input to the frequency detector 600 to record the frequency.

Therefore, even during recording, the channel bit clock CH_clock can be generated using the wobble clock signal WB_clock and the pseudo EFM signal using the wobble signal, thereby performing phase locked loop.

As described above, the present invention can perform precise frequency detection while lowering the oscillation frequency of the voltage controlled oscillator of the phase synchronization loop circuit for an optical disc in half, and by reducing the oscillation frequency in half, 1/2 minute of the front end of the phase detector. There is an advantage of not having to provide an additional period.

In addition, by using a circuit for generating a pseudo EFM signal using a header signal and a wobble signal, phase synchronization loops can be performed even during recording, thereby supporting the DVD-RAM.

Claims (5)

In a phase locked loop system for an optical disc, The frame sync pattern section of the EFM signal reproduced and inputted from the optical disc is counted by a phase sync clock of a voltage controlled oscillator and compared with a count value preset in the frame sync pattern. A frequency detector for generating a pulse width modulated signal for up or down the oscillation frequency of the oscillator; And a microcomputer for applying a pulse width control signal for adjusting the pulse width so that the pulse width of the pulse width modulated signal is set according to the error. The method of claim 1, wherein the frequency detector, And if the error does not occur, generates a frequency lock signal for maintaining the oscillation frequency of the voltage controlled oscillator as it is. The method of claim 1, wherein the frequency detector, And a counter unit for counting a frame synchronization pattern section of the EFM signal for each rising edge and falling edge of the phase synchronization clock. The method of claim 3, wherein the counter unit, A first counter for counting a frame synchronization pattern of an EFM signal reproduced and inputted from the optical disc at every rising edge of the phase synchronization clock of the voltage controlled oscillator; A second counter for counting a frame synchronization pattern of an EFM signal reproduced and inputted from the optical disc at every falling edge of the phase synchronization clock of the voltage controlled oscillator; And an adder for adding and outputting count values output from the first counter and the second counter. The method of claim 1, A voltage controlled oscillator for varying the oscillation frequency by a predetermined input voltage; 1/186 divider for dividing the frequency of the phase locked clock generated from the voltage controlled oscillator by 1/186, A phase detection unit for detecting a phase difference by comparing a phase of a wobble signal input from the optical disk with a phase of a 1/186 divided phase synchronization clock input from the 1/186 divider, and outputting a predetermined pulse width modulation signal; A charge pump for adjusting an input voltage of the voltage controlled oscillator according to the predetermined pulse width modulation signal input from the phase detector; A low pass filter for low pass filtering the voltage applied from the charge pump to the voltage controlled oscillator; 3 T for distributing the phase locked clock generated from the voltage controlled oscillator phase synchronized with the wobble signal in the form of an EFM signal to generate a pseudo EFM signal and apply it to the frequency detector. A phase synchronization loop system for an optical disc, characterized by further comprising a ~ 14 T (T) generator.