JPH09252293A - Phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an immediate lock characteristic at the start of burst and high accuracy and highly stable steady phase lock characteristic for a demodulation period in common. SOLUTION: The circuit compares a burst signal (a) with a recovered clock (b) being an output of a frequency divider 13 and controls an up-down counter 12 corresponding to lead/lag of the phase of the recovered clock (b) to eliminate or add a pulse in an output pulse train of a stationary frequency oscillator 35 in response to the lead or lag thereby applying negative feedback control to match the phase difference. In this case, a preset device 16 is provided to preset the frequency divider at an initial change point of the burst signal (a) so as to immediately establish the phase lock state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop system, and more particularly to a phase locked loop circuit used for clock recovery in transmission of burst mode signals.

[0002]

2. Description of the Related Art In a transmission system in which communication is performed by a burst mode signal, a reference clock signal of transmission data is required for demodulation in a receiver. For reproducing such a reference clock signal, for example, Japanese Patent Laid-Open No. 2-5
A phase locked loop circuit as described in Japanese Patent No. 6134 is used.

FIG. 3 is a block diagram of the conventional phase locked loop circuit. This circuit detects the input of a burst signal in addition to the basic configuration of a phase locked loop including a binary quantization phase comparator 31, an up / down counter 32, a frequency divider 33, a pulse removal adder 34, and a fixed frequency oscillator 35. It has a detection circuit 36 and a control circuit 37 for controlling the up / down counter and the pulse removal adder.

The operation of the conventional phase locked loop circuit is performed as follows.

The binary quantization phase comparator 31 compares the phases of the binary input signal a and the reproduced clock b, and advances (+1) and delays (-1) the reproduced clock b with respect to the input signal a.
The signal of is output. The up / down counter 32 counts +1 and −1 according to the lead / lag, and when the count value matches the set values + N and −N, notifies the pulse removal adder 34 of the lead / lag. The pulse removal adder 34 removes or adds a pulse of a set value M bits to the output pulse train of the fixed frequency oscillator 35 according to the advance or delay and outputs the pulse. This output becomes the reproduction clock b which is frequency-divided by the frequency divider and phase-locked and controlled.

Then, the detection circuit 36 detects the burst of the input signal and notifies the control circuit 7 of it. Control circuit 37
Is an up / down counter 32 and a pulse removal adder 34.
The set values N and M of are controlled. The set values N and M determine the speed of synchronization pull-in of phase synchronization and synchronization accuracy. That is, the smaller N is, the more sensitive the operation is to the phase difference, and the larger M is, the larger the correction amount for one phase difference is and the faster the synchronous pull-in operation is performed.

Therefore, the control circuit 37 detects the burst signal of the input signal and sets the set values N and M so that the high-speed synchronous pull-in can be performed. In the subsequent data demodulation period, it is set so that the synchronization pull-in can be performed with high stability and high accuracy. As the burst signal detection circuit, a frame synchronization signal, a preamble signal, a phase difference between the input signal and the reproduction clock, and a reception level detection means are used.

[0008]

SUMMARY OF THE INVENTION In the above-described conventional example, in the transmission system handling a burst mode signal, in order to generate a highly accurate and stable recovered clock for performing a demodulation operation with few errors, the burst initial stage is used. The switching control of the set values N and M of the up-down counter and the pulse elimination adder is performed so as to have both the high-speed synchronization pull-in characteristic and the high stable phase synchronization characteristic of the data signal period.

However, in the above-mentioned conventional example, since the initial synchronous pull-in operation of the burst signal is performed by the negative feedback operation of the phase locked loop, the pull-in delay time due to the synchronous pull-in operation cannot be avoided. Therefore, with this method, it is difficult to shorten the preamble signal period in the burst signal and the burst transmission efficiency cannot be improved. Therefore, the conventional example has a drawback that it is not suitable for a transmission method of a burst signal having a short signal length.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase locked loop circuit having an instantaneous pull-in characteristic at the initial stage of burst and a highly accurate and stable phase locked characteristic in the demodulation period.

[0011]

According to the phase locked loop circuit of the present invention, in a phase locked loop circuit for reproducing a clock for a burst mode signal, a change point of an initial pulse signal of the burst mode signal is detected to detect a phase locked output. It is characterized by having a presetter for presetting a phase.

Further, the phase locked loop circuit can be configured to have a phase locked loop for comparing the phases of the burst mode signal and the oscillation output of the voltage controlled oscillator and controlling the voltage controlled oscillator according to the phase difference.

Further, the phase locked loop circuit comprises a phase comparator for comparing the phases of the burst mode signal and the phase locked output, an up / down counter controlled by the phase error output of the phase comparator, and the up / down counter. A pulse removal adder for removing or adding a pulse to the output of the fixed frequency oscillator controlled by the output of, and a divider for dividing the output of the pulse removal adder to generate the phase-locked output, The presetter is preferably configured to preset the frequency divider.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described. FIG. 1 is a block diagram of a phase locked loop circuit showing the present embodiment.

In the present embodiment, as the phase synchronization circuit,
Binary quantization phase comparator 11, up-down counter 1
2, a frequency divider 13, a pulse removal adder 14, a fixed frequency oscillator 15, and a setter 17 have a basic configuration of a phase-locked loop, and the up-down counter 12 as a loop filter of the phase-locked loop, A fixed frequency oscillator 15, a pulse removal adder 14 and a frequency divider 13 are used as an oscillation circuit (voltage controlled oscillator) capable of frequency control, and the frequency divider 13 outputs a reproduced clock.

Further, the present embodiment has a presetter 37 which is controlled by the inter-burst signal. The presetter 16 is a first preamplifier for burst signals.
The second pulse change point is detected, and the frequency divider 13 is preset by the detection output signal.

Next, the clock reproducing operation in this embodiment will be described.

The binary quantization phase comparator 11 compares the phase of the input signal a and the phase of the reproduced clock b which is the output of the frequency divider 13, and responds to the advance or delay of the phase of the reproduced clock b with respect to the input signal a. And outputs a +1 or -1 signal, respectively. The up / down counter 12 performs addition and subtraction operations of other reference pulses and the like according to the outputs +1 and −1 of the lead and lag, and the count value is one of the set values + N and −N preset by the setter 17. When they match, a signal indicating the advance or delay of the reproduced clock is output, and the pulse removal adder 14 is controlled by the signal. The pulse removal adder 14 removes or adds a pulse of the number of bits of the set value M preset by the setter 17 in the output pulse train of the fixed frequency oscillator 15 according to the lead or lag signal and outputs it. This output pulse train is frequency-divided by a frequency divider to become the reproduction clock b. The reproduced clock b is phase-locked with the input signal a by the negative feedback control of the phase lock circuit described above.

Next, the presetter 16 is provided to set the first reproduced clock in the burst period to the optimum phase. The output phase of the frequency divider 13 is instantaneously set at the rising edge of the preamble of the burst signal. The input signal a and the inter-burst signal c that gates the burst signal of the input signal a are input, and the burst signal of the input signal a is extracted by the inter-burst signal c. Then, the first change point of the first pattern pulse in the preamble period is detected, and the frequency divider 13 is preset by the detection output. The frequency divider 13 can output an output in which the phase of the reproduced clock is synchronized with the phase of the input signal a in a constant phase relationship from the initial point.

As can be seen from the above operation, in this embodiment, the pull-in operation of the phase locked loop can be instantaneously performed directly by the preamble pulse of the burst signal, so that the operation characteristics of the phase locked loop are stable and highly accurate. N and M can be set in advance by the setter 17 so as to perform the phase synchronization operation. That is, in the pulse elimination adder 14, the sensitivity to the phase difference is reduced and the correction amount per time is reduced to slow the control of the repetition frequency of the output signal, so that the error of the output of the phase comparator due to noise or the like may be pulsed. Increase N by M to reduce the influence on the removal adder.
Is reduced to improve synchronization accuracy and perform stable and highly accurate clock reproduction.

The operation flow of the above embodiment is shown in FIG.

The inter-burst signal c is a signal for extracting the burst signal by changing the logical level during the burst signal which is the input signal. In step 21, it is judged whether or not the above-mentioned logic level of the inter-burst signal c has just been input. If just after the input, in step 22, the output pulse of the frequency divider is changed by the first pulse of the received burst signal. Preset to match the phase. If it is the period of the burst signal, the phase comparison between the input signal and the reproduced clock is performed in step 23. If the reproduction clock b is delayed from the input signal a, the up / down counter subtracts and counts with another clock pulse in step 24, and when the count value becomes -N, in step 25, the output pulse train of the fixed frequency oscillator has M bits. Add a pulse to advance the phase of the recovered clock. If the reproduction clock is advanced, step 27
The up / down counter counts up with + N
Then, in step 28, the M-bit pulse is removed and the phase of the reproduction clock is delayed.

In the above embodiments, the present invention has been described by using a circuit having a loop filter function by using an up-down counter, a pulse removal adder, etc. as the phase synchronizing circuit. The phase locked loop circuit can be configured by an analog circuit in which the output of the phase comparator controls the voltage controlled oscillator through the filter.

Since the present invention is intended for a burst mode signal as an input signal and uses the changing point of the first pulse signal of the burst signal, it is of a system in which time slots are fixed, such as a time division communication system. Thus, it is effective when the input time of the burst signal can be predicted to some extent. Also, it is normally used that the noise of the signal can be ignored during the burst signal period.

Further, the present invention is not limited to the case where the target burst mode signal is a baseband type signal, but it is easy to use a demodulator for a carrier type signal for performing phase modulation (PSK) or the like. Applicable to In addition,
The first change point of the preamble pattern pulse of the burst mode signal can be instantly detected by using the delay detection means even in the case of phase modulation. That is, the present invention can be applied to any case of optical communication, wired and wireless communication.

[0026]

According to the present invention, since the phase-locked loop is pulled in by utilizing the first change point of the baseband timing signal in the burst signal period, the characteristics of the clock recovery in the burst signal period are initially set. It is possible to achieve immediate synchronization pull-in at the time of inputting a burst signal while sufficiently maintaining the necessary stability without being restricted by the synchronization pull-in.

This is because the synchronization pull-in means when the burst signal is input and the synchronization pull-in means in the burst period are switched by different principles.

Further, since it is possible to instantly establish the phase synchronization when the burst signal is input, the number of bits of the preamble pattern of the burst signal can be reduced to several bits in principle, and the transmission efficiency of communication data is improved. It is possible to realize a very high burst mode data communication method.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a diagram illustrating a flow chart of the operation of the present embodiment.

FIG. 3 is a diagram illustrating a conventional example.

[Explanation of symbols]

 11,31 Binary quantization phase comparator 12,32 Up-down counter 13,33 Frequency divider 14,34 Pulse removal adder 15,35 Fixed frequency oscillator 16 Presetter 17 Setter

Claims (3)

[Claims] 1. A phase synchronization circuit for reproducing a clock for a burst mode signal, comprising a presetter for detecting a change point of an initial pulse signal of the burst mode signal and presetting a phase of a phase synchronization output. A phase synchronization circuit. 2. The phase-locked loop circuit includes a phase-locked loop that compares the phases of the burst mode signal and the oscillation output of the voltage-controlled oscillator and controls the voltage-controlled oscillator according to the phase difference. Item 2. The phase locked loop circuit according to item 1. 3. The phase lock circuit includes a phase comparator for comparing the phases of a burst mode signal and a phase lock output, an up / down counter controlled by a phase error output of the phase comparator, and the up / down counter. A pulse removal adder for removing or adding a pulse to the output of the fixed frequency oscillator controlled by the output of, and a divider for dividing the output of the pulse removal adder to generate the phase-locked output, 2. The phase locked loop circuit according to claim 1, wherein the presetter presets a frequency divider.