JP2586694B2 - Digital signal receiving circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a receiving circuit in digital transmission.

〔Overview〕

According to the present invention, in a receiving circuit of a digital signal to be trained, training can be sped up by controlling a sampling phase so as to quickly fall within a synchronization pull-in range after setting an initial phase. is there.

[Conventional technology]

In a digital signal receiving circuit, a training time is required for automatic equalization of a received signal and timing signal extraction. It is important to speed up the training and realize a short synchronization pull-in time. In particular, as a conventional example regarding training of reception timing, Japanese Patent Application No. 62-288940
There is a method for realizing high speed by starting training near an optimum sampling phase using an initial phase setting circuit as described in (Reference 1).

[Problems to be solved by the invention]

FIG. 4 shows a conventional method using the initial phase setting. This figure shows the relationship between various phases centering on the optimum sampling phase. (A) shows the range of the initial phase set by the initial phase setting circuit. If the error in calculating the initial phase or the degree of freedom in setting the phase is low and there is a setting error,
The set values of the initial phase are distributed. (B) shows a range of phases in which identification determination is normally performed and synchronization can be performed. In general, even if the initial phase (A) is inside the range (B) of the phase that can be pulled in, the reception sampling phase moves after the initial phase is set, and the phase is outside the range (B) before the pull-in is completed. In some cases, making synchronization impossible. The reason why the reception sampling phase moves after the initial phase is set is usually due to a frequency shift between the reception signal and the oscillator in the reception circuit. (C) shows the movement of the reception sampling phase within the time until the synchronization pull-in is completed. If the sum of the range (A) and the range (C) exceeds the range (B), Cannot guarantee that synchronization is achieved within the synchronization pull-in time. in this way,
When the receiving sampling phase is set as close as possible to the optimal sampling phase using the initial phase setting circuit,
Under the condition that the range of (A) and (C) exceeds the range of (B), there is a drawback that the guaranteed value of the synchronization pull-in time becomes extremely long.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital signal receiving circuit which eliminates such a drawback and can perform stable high-speed synchronization pull-in.

[Means for solving the problem]

The present invention provides an equalization determination circuit that filters a received signal and discriminates and filters the filtered received signal with an optimal sampling phase, and a synchronization pull-in detection circuit that detects a synchronization pull-in state of the equalization determination circuit. A digital signal receiving circuit provided with: an initial phase setting circuit for obtaining an optimal sampling phase of a received signal, and initial setting an initial sampling phase to a phase shifted by a predetermined amount from the optimal sampling phase in a predetermined direction; Starting from an initial sampling phase initialized by the initial phase setting circuit, the initial sampling phase is shifted in a direction opposite to the predetermined direction as time elapses, and the synchronization pull-in detection circuit performs synchronization pull-in of the equalization determination circuit. The shift is stopped at the time when the state is detected, and thereafter, supplied from the equalization determination circuit. And a timing control circuit for holding the sampling phase based on that timing information.

Here, the timing control circuit may have a configuration including a voltage-controlled oscillator that can variably set a voltage input.

[Action]

A phase in which a predetermined amount of phase is shifted from the optimum sampling phase in advance is set as an initial phase, and the sampling phase is shifted in one direction during a period from setting of the initial phase to synchronization pull-in. As a result, the synchronization pull-in time can be shortened.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of this embodiment.
In this embodiment, as shown in FIG.
An initial phase setting circuit 2, a timing control circuit 3,
A synchronization pull-in detection circuit 4, wherein the equalization determination circuit 1 includes a reception signal equalization circuit 11, an identification determination circuit 12, a determination feedback equalization / timing information generation circuit 13, and a reception signal sampling circuit. And a circuit 14. In this embodiment, the sampling circuit 14 controls the equalization circuit 11 for the received signal.
However, the present invention can be implemented even if it is disposed after the equalization circuit 11.

In this embodiment, as shown in FIG. 1, an equalization determination circuit 1 that filters a received signal and discriminates and filters the filtered received signal with an optimal sampling phase.
A synchronization pull-in detection circuit 4 for detecting a synchronization pull-in state of the equalization determination circuit 1; further, as a characteristic feature of the present invention, an optimum sampling phase of a received signal is obtained;
An initial phase setting circuit 2 for initially setting an initial sampling phase to a phase shifted by a predetermined amount from the optimum sampling phase in a predetermined direction; and an initial sampling phase initially set by the initial phase setting circuit 2 during reception training. The initial sampling phase is shifted in the direction opposite to the predetermined direction as
Has a timing control circuit 3 which stops the shift when detecting the pull-in state of the equalization determination circuit 1 and thereafter holds a sampling phase based on the timing information supplied from the equalization determination circuit 1.

Next, the operation of this embodiment will be described with reference to FIGS.

The timing information created by the decision feedback equalization / timing information creation circuit 13 is information indicating whether the current sampling phase is advanced or delayed with respect to the optimal sampling phase. . The initial phase setting circuit 2 calculates the optimum sampling phase using the received light waveform in the equalization circuit 11 or the timing information from the decision feedback equalization / timing information generation circuit 13, but calculates the optimum sampling phase from the received waveform in the equalization circuit 11. A method for performing this is disclosed in Reference 1. The timing control circuit 3 has a function of bringing the sampling phase closer to the optimum sampling phase in accordance with the timing information from the decision feedback equalization / timing information creation circuit 13 after the synchronization pull-in, and a function of the initial phase setting circuit 2 at the time of initial phase setting.
Has the function of setting the sampling phase as the determination phase based on the instruction of (1). These two functions of the timing control circuit 3 are already known. The features of the present invention are that the timing control circuit 3 is provided with a function of shifting the sampling phase in one direction until the synchronization is pulled in after the initial phase is set, and that the initial phase setting circuit 2 has an optimum sampling phase. That is, the phase shifted by a certain amount in one direction is set as the initial phase.

As shown in FIG. 2, (A ') is a sampling phase initial phase setting circuit 2 sets are offset by phi ₁ in the direction of advanced phase relative to shown in FIG. 4 (A) . (B ') and (C') are the same as (B) and (C) in FIG. 4, respectively. In this example,
The sampling phase is shifted after the initial phase is set, and this is shown in (D '). Although the arrow is in the lower right, downward component shows the progress of time, which means that the phase from the time of the initial phase set in the normal time to pull-in is completed is shifted by phi ₂ .
Due to (D '), the sampling phase which was in the range of (A') at the time of setting the initial phase is normally changed to the range of (A ') + (C') + (D ') within the time until the completion of synchronization pull-in. Go to Here, the range of (A ') + (C') + (D ') exceeds the range of (B') at the left end. The amount of shift increases and the sampling phase falls within the range of (B '). Thus, as shown in FIG. 3, (A) +
Even when the range of (C) exceeds the range of (B), the synchronization pull-in time is slightly increased by shifting (A) to (A ') and adding a phase shift (D'). Just by doing so, a high-speed synchronization pull-in time can be guaranteed.

Next, a method for realizing the features of the present invention will be described.
First, regarding the function of the timing control circuit 3 that shifts the sampling phase in one direction from the initial phase setting to the synchronization pull-in, the timing control circuit is configured using a VCO (Voltage Controlled Oscillator), and the VCO voltage input is performed. Or the phase is shifted by forcibly shifting the oscillation frequency to shift the phase, or the clock higher than the reception baud rate is divided by N to be the reception sampling clock, and the division ratio is sometimes set to N-1 or N + 1 to shift the phase. There are various methods such as methods. Further, as for a method in which the initial phase setting circuit 2 sets a phase shifted by a certain amount in one direction from the optimum sampling phase as an initial phase, a method described in Reference 1 is used for each of a plurality of phases every 2π / M (M is an integer). There are various methods, such as a method of calculating a power to obtain an optimum sampling point and then skipping the phase by correcting the N value only once from the current phase to the optimum sampling phase. .

〔The invention's effect〕

As described above, the present invention shifts the range of the initial phase and shifts the sampling phase after setting the initial phase, thereby stably achieving high-speed synchronization.

[Brief description of the drawings]

FIG. 1 is a clock configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is an explanatory diagram showing the operation of the embodiment of the present invention. FIG. 3 is a flowchart showing the operation of the embodiment of the present invention. FIG. 4 is an explanatory diagram showing a conventional operation. 1 ... Equalization determination circuit, 2 ... Initial phase setting circuit, 3 ...
Timing control circuit, 4 ... Synchronization pull-in detection circuit, 11 ...
... Equalization circuit, 12 ... Identification judgment circuit, 13 ... Judgment feedback equalization / timing information creation circuit, 14 ... Sampling circuit.

Claims (1)

(57) [Claims] An equalization judging circuit for filtering a received signal and discriminating the filtered received signal with an optimum sampling phase, and a synchronization pull-in detection circuit for detecting a bit synchronization pull-in state of the equalization judging circuit. A digital signal receiving circuit comprising: an initial phase setting circuit that obtains an optimal sampling phase of a received signal, and initializes an initial sampling phase to a phase shifted by a predetermined amount in a predetermined direction from the optimal sampling phase; Starting from an initial sampling phase initially set by the initial phase setting circuit, and shifting the initial sampling phase in a direction opposite to the predetermined direction with the passage of time. This shift is stopped when the synchronization pull-in state is detected. And a timing control circuit for holding the sampling phase based on the timing information et supplied, the timing control circuit, the digital signal receiving circuit, comprising the voltage controlled oscillator capable of variably setting the voltage input.