JPH06152669A - Clock recovery circuit - Google Patents

Abstract

PURPOSE:To detect a data conversion point of reception data efficiently with simple configuration by providing an offset circuit offsetting a phase angle signal of an output of a demodulator by a prescribed angle. CONSTITUTION:An offset circuit 3 offsets a phase angle signal theta of an output of a demodulator 100 by a prescribed angle. An edge detection circuit 4 detects a prescribed data conversion point of reception data based on an output thetas of the offset circuit 3. A phase comparator circuit 5 compares a phase of the data conversion point detected by the edge detection circuit 4 with a phase of a recovered clock signal. A clock generating circuit 6 generates the recovered clock signal so as to make the phase difference constant based on the phase difference detected by the phase comparator circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit, and more particularly to a clock recovery circuit of a demodulator of the type which detects a PSK modulated wave and generates a corresponding phase angle signal θ. In the field of wireless communication, digital modulation schemes are being actively introduced for the purpose of improving frequency utilization efficiency. In digital wireless communication, a frequency shift due to a temperature change of a local oscillator for timing of a transmitter / receiver becomes a problem, and it is necessary to provide a clock recovery circuit for compensating for such frequency fluctuation.

Nowadays, digital modulation / demodulation methods are diversified, and for example, a demodulator of a type which detects an n-phase PSK modulated wave and generates a corresponding phase angle signal θ is provided.
This type of demodulator also requires a clock recovery circuit,
Unlike the conventional quadrature component data I and Q, the phase angle signal θ is output to the outside of this demodulator, which causes a problem in detecting the data conversion point of the received data.

Therefore, it is desired to provide a clock recovery circuit for efficiently detecting the data conversion point of the received data based on the phase angle signal θ with a simple structure.

[0004]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional clock recovery circuit. In the figure, 7 is a phase detection circuit, 7 ₁ is a carrier wave oscillator, 7 ₂ is a quadrature detection circuit, and 7 ₃ and 7 ₄ are A / D converters. (A / D), 7 ₅ baseband differential detection calculating circuit (B
DD), 2 is a data determination circuit, 4 is an edge detection circuit, 4
₁ flip-flop circuit (FF), 4 ₂ is EX-OR
Circuit (E), 8 is a phase comparison circuit, 8 ₁ is a 2-bit counter circuit (CTR), A is an AND gate circuit, 9 is a clock generation circuit, and 9 ₁ is a random walk filter (RW).
F), 9 ₂ frequency divider, 10 and 11 is a delay circuit (D).

[0005] After the IF signal inputs are orthogonal detection by orthogonal detection circuits 7 _2, A sampling clock signal SCLK
/ D converted, and further baseband differential detection arithmetic circuit 7 ₅
Is differentially detected by and converted into quadrature component data I and Q.
The edge detection circuit 4 detects a data conversion point Y on the I axis by differentiating a signal obtained by making a hard decision on the data I with a predetermined threshold value, for example. The phase comparison circuit 8 determines the lead / lag of the phase of the reproduction clock signal 1CLK with respect to the data conversion point Y by performing a phase comparison between the data conversion point Y and the rising edge of the reproduction clock signal 1CLK. That is, when the data conversion point Y is detected after the reproduction clock signal 1CLK rises, it is determined that the phase advances (X = 1, Y = 1), and the data conversion point Y is detected before the reproduction clock signal 1CLK rises. Then, the phase delay (X = 0, Y =
Determined as 1).

The random walk filter 9 ₁ of the clock generation circuit 9 raises / lowers an internal up / down counter (not shown) according to the lead / lag of the phase judged by the phase comparator circuit 8. When the count output of the down counter exceeds the internally controlled threshold value, the variable ± x is output. Then, the frequency divider 9 ₂ divides the high-speed (64 times speed of 1CLK) master clock signal MCLK into 1 / (16 ± x) by using the variable ± x as a control input, and generates the reproduced clock signal 4CLK.

Thus, the phase difference between the data conversion point Y and the reproduced clock signal 1CLK is controlled to be always constant, whereby the clock signal 1CLKD output from the delay circuit 11 is at the center of the eye of the data I and Q. Is adjusted to come to. As described above, conventionally, the clock phase of the reproduced clock signal 1CLK is adjusted by performing the phase comparison between the data conversion point Y of the I (or Q) component and the reproduced clock signal 1CLK.

[0008]

However, in a demodulator of the type that detects an n-phase PSK modulated wave and generates a corresponding phase angle signal θ, only the phase angle signal θ can be taken out, so that reception is possible. There is a problem in detecting the data conversion point of the data. If this is explained by a BPSK modulation method in which data “0” = 0 ° and data “1” = 180 °, for example, the detected phase angle signal θ is 0 ° and 360 °.
It will be concentrated in two poles, near and 180 degrees. Therefore, if it is attempted to detect the same data conversion point as in the conventional case from such a phase angle signal θ, the hard decision is 90 ° and 2
Since two threshold values of 70 ° are required, there is a drawback that the hard decision circuit becomes complicated.

Further, a method may be considered in which the phase angle signal θ is decomposed again into quadrature component data of I and Q and a conventional clock recovery circuit is connected to this, but for this purpose, sin θ and cos θ are externally provided. There is a drawback that an arithmetic circuit for multiplying by is required, and the circuit scale increases. An object of the present invention is to provide a clock recovery circuit that efficiently detects a data conversion point of received data based on the phase angle signal θ with a simple configuration.

[0010]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the clock recovery circuit of the present invention is a clock recovery circuit of a demodulator of the type that detects a PSK modulated wave and generates a corresponding phase angle signal θ, and offsets the phase angle signal θ of the output of the demodulator by a predetermined angle. An offset circuit 3, an edge detection circuit 4 that detects a predetermined data conversion point of received data based on the output of the offset circuit 3, and a phase comparison between the data conversion point detected by the edge detection circuit 4 and the reproduced clock signal are performed. Phase comparison circuit 5
And a clock generation circuit 6 for generating a reproduced clock signal so as to make the phase difference constant based on the phase difference detected by the phase comparison circuit 5.

[0011]

In FIG. 1A, the offset circuit 3 converts the phase angle signal θ of the output of the demodulator into a phase angle signal θ _{S in} which the data conversion point can be easily detected by offsetting it by a predetermined angle θ _OFS. There is. That is, for example, when this is explained by the BPSK modulation method of FIG. 1B, the detected phase angle signal θ on the left side of the figure is near 0 ° and 360 ° depending on “0” and “1” of the transmission data. It concentrates on two poles, around 180 °. Therefore, if it is attempted to detect the same data conversion point as in the conventional case from such a phase angle signal θ, two thresholds of 90 ° and 270 ° are required for the hard decision.

In the present invention, the offset circuit 3 adds an offset of, for example, θ _OFS = 90 ° to the phase angle signal θ. By doing so, the offset phase angle signal θ _S is concentrated on the two poles near 90 ° and around 270 °. Therefore, these can be easily hard-decided with a single threshold value of θ _S ≧ 180 °. Moreover, since the offset circuit 3 can be configured by an adder, the configuration is simple.

Preferably, the phase comparison circuit 5 divides the reproduction clock cycle into four or more time slots, and
Two or more types of phase difference signals having different sizes are output according to the correspondence between each of the divided time slots and the detected data conversion point. Also preferably, the clock generation circuit 6 is
A first path for filtering a detection signal with a small phase difference and inputting it to the post-selection means 6 ₃ , a second path for directly inputting a detection signal with a large phase difference to the selection means 6 ₃ , and a selection means 6 ₃ and a frequency divider 6 ₂ for variably controlling the frequency division ratio of the high-speed reference clock signal in response to the output, the selection means 6 ₃ normally selects the first path, and second at the time of high-speed pull-in clock phase Is controlled to select the route.

[0014]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. Figure 2 is a block diagram of the clock recovery circuit of Embodiment 1 is a phase detection circuit in FIG, 1 ₁ is a carrier oscillator, 1 ₂ quadrature detector, 1 _3,
1 ₄ A / D converter (A / D), 1 ₅ the angle transformer, 1
₆ is a differential detection circuit, ₁₇ is a shift register (SR) for one symbol, ₁₈ is a subtraction circuit, 2 is a data determination circuit, 3
Offset circuit (OFSC), 3 ₁ is summing circuit, the edge detection circuit 4, 4 ₁ flip-flop circuit (F
F), 4 ₂ is EX-OR circuit (E), the phase comparator circuit 5, 5 ₁ 2-bit counter circuit (CTR), A is A
ND gate circuit, E is EX-OR circuit, I is inverter circuit, 6 is clock generation circuit, 6 ₁ is random walk filter (RWF), 6 ₂ is frequency divider, 6 ₃ is selector (SEL), 10, 11 Is a delay circuit (D).

[0015] After the IF signal inputs are orthogonal detection by orthogonal detection circuits 1 _2, [theta] & apos at an angle transducer 1 ₅ = tan ^-1 (Q /
In step I), the local coordinates are converted, and further, the delay detection circuit ₁₆ delay-detects them to convert them into a phase angle signal θ corresponding to the transmission data. The offset circuit 3 adds a predetermined angle θ to the phase angle signal θ.
By adding _OFS , the phase angle signal θ is offset by θ _{OFS, and the} phase angle signal θ _S that makes it easy to detect the data conversion point
Convert to.

FIGS. 3 and 4 are diagrams for explaining the method of detecting the data conversion points according to the embodiment. FIG. 3A shows the case of the BPSK modulation method, in which the transmission data is “0” or “1”.
The phase angle signal θ detected by these signals is 0 ° and 36
They are concentrated in two poles, around 0 ° and around 180 °. Note that T represents one symbol section. FIG. 3B shows an offset angle θ _OFS = 9 for the phase angle signal θ of FIG.
The figure shows the case where 0 ° is added, and the phase angle signal θ _S after the offset comes to concentrate on two poles near 90 ° and around 270 °. Therefore, the data conversion point is θ _S ≧ 180 °
Hard decision can be easily made with a single threshold of whether or not.

FIG. 3C shows the case of the QPSK modulation method, and the phase angle signal θ detected by these in accordance with the transmission data has four poles near 45 °, 135 °, 225 ° and 315 °. focusing. In this case, the offset angle θ
_OFS = 0 ° may be added, and the data conversion point can be easily hard-decided with a single threshold value whether or not θ _S ≧ 180 ° in the same manner as above.

FIG. 4A shows the case of the 8PSK modulation method, and the phase angle signals θ detected from these in accordance with the transmission data are 45 °, 90 °, 135 °, 180 °, 22.
It is concentrated in 8 poles near 5 °, 270 °, 315 ° and 360 ° (0 °). FIG. 4B shows the case where the offset angle θ _OFS = 22.5 ° is added to the phase angle signal θ of FIG. 4A, and the phase angle signal θ _S after offset is 6
7.5 °, 112.5 °, 157.5 °, 202.5
°, 247.5 °, 292.5 °, 337.5 ° and 2
It comes to concentrate on 8 poles around 2.5 °. Therefore, also in this case, the data conversion point can be easily hard-decided with a single threshold value of θ _S ≧ 180 °. Hereinafter, the same can be applied to any 2 ⁿ PSK modulation method.

Returning to FIG. 2, the edge detection circuit 4 detects the data conversion point Y by differentiating a predetermined bit signal of the phase angle signal θ _S. For example, when the phase angle signal θ _S is represented by an 8-bit signal, 0 ° = “00000000”, 180 ° =
“10000000”, 359 ° = “1111111
It can be represented by a code system such as "1". Therefore, the edge detection circuit 4 need only pay attention to the most significant bit signal B of the phase angle signal θ _S.

The phase comparison circuit 8 compares the phase of the data conversion point Y with the rising edge of the reproduction clock signal 1CLK to obtain the reproduction clock signal 1C for the data conversion point Y.
The lead / lag of the LK phase is determined. That is, in the present embodiment, the reproduction clock cycle is divided into four time slots, and "X, Y" and "K" having different sizes according to the correspondence between the divided time slots and the detected data conversion points. _X , _KY , _KZ ".

The clock generation circuit 6 filters the detection signals X and Y having a small phase difference by the random walk filter 9 ₁ and inputs them to the rear selector 6 ₃ , and the detection signal K _X having a large phase difference, A second path for directly inputting K _Y and K _Z to the selector 6 ₃ and a frequency division for variably controlling the frequency division ratio of the high-speed (64 times the speed of 1 CLK) reference clock signal MCLK according to the output x of the selector 6 _3. and a vessel 6 _2. The selector 6 ₃ normally selects the first path by the control signal BST from the outside, but is controlled to select the second path when the clock phase is pulled in at high speed such as when a burst is detected.

Thus, the phase difference between the data conversion point Y and the reproduced clock signal 1CLK is controlled so as to be always constant, and the clock signal 1CLKD output from the delay circuit 11 is adjusted so as to come to the center of the eye of the phase angle signal θ. To be done. Figure 5
3 is an operation timing chart of the clock recovery circuit of the embodiment. The phase is compared between the data change point Y of the hard decision signal B and the rising edge of the reproduction clock signal 1CLK. 1
Since four sample signals SCLK are generated in the symbol period, the rising edge of the clock signal 1CLK and the data change point Y
There are four cases of cases (1) to (4) in the phase relationship with. In either case, the clock signal 1CLKD is reproduced so that the rising edge of the clock signal 1CLKD hits the position where the eye of the phase angle signal θ is most opened. In this example, in consideration of the delay amount due to the delay circuits 10 and 11, the rising edge of the clock signal 1CLK is controlled so as to come around the time slot 1.

In case (1), the phase of the clock signal 1CLK is slightly delayed. In this case, the phase comparison circuit 5 outputs X = 0 and Y = 1, and the up / down counter (not shown) of the random walk filter 6 ₁ is set to 1 by this.
Count down. And if this is up /
When the count output of the down counter exceeds the internal control threshold is a random walk filter ₆₁ outputs the variable -x (e.g. -1). Accordingly, the frequency divider 9 ₂ the master clock signal MCLK 1 / (16-
The frequency division is performed in 1), which causes the phase of the clock signal 1CLK to slightly advance.

In the case (2), the phase of the clock signal 1CLK is slightly advanced. In this case, the phase comparison circuit 5 outputs X = 1 and Y = 1, which causes the up / down counter of the random walk filter 6 ₁ to count up by one. Then, if this causes the count output of the up / down counter to exceed the internally controlled threshold, the random walk filter 6 ₁ outputs a variable x (eg, 1). As a result, the frequency divider 9 ₂ frequency-divides the master clock signal MCLK by 1 / (16 + 1), whereby the phase of the clock signal 1CLK is slightly delayed.

In case (3), the phase of the clock signal 1CLK is greatly advanced. Such a state occurs at the time of high-speed pulling in of the clock phase at the time of burst detection. The phase comparison circuit 5 outputs X = 1 and Y = 1 and also outputs K _X and K.
_Y and K _Z = 1 are output. As a result, the up / down counter of the random walk filter 6 ₁ is incremented by 1, and K _X , K _Y , and K _Z = 1 are assigned to the selector 6.
It is converted into a variable x (for example +6) by inputting ₃ . Then, if the control signal BST selects the second path, the frequency divider 9 ₂ divides the master clock signal MCLK by 1 / (16 + 6), which causes the phase of the clock signal 1CLK. Will be greatly delayed. Then K
_{When X} , K _Y , K _Z = 1 disappears and the control signal BST is returned to select the first path, the steady synchronization state is entered.

In case (4), the phase of the clock signal 1CLK is greatly delayed. In this case, the phase comparison circuit 5 outputs X = 0 and Y = 1 and outputs K _Y and K _Z = 1. As a result, the up / down counter of the random walk filter 6 ₁ is counted down by 1 and K _Y , K _Z = 1 is converted into a variable x (for example, -6) at the input of the selector 6 ₃ . And if the control signal BST
There if you select the second path, the divider 9 ₂ becomes possible to divide the master clock signal MCLK 1 / (16-6), thereby the clock signal 1CLK phase proceeds significantly. After that, when K _Y and K _Z = 1 are not output and the control signal BST is returned to select the first path, the steady synchronization state is entered.

[0027] In the above embodiment, by adding the offset angle theta _OFS in theta phase angle signal after delay detection may be configured to add an offset angle theta _OFS to delay detection prior to the phase angle signal θ' . In addition, although the demodulator of the differential detection system is described in the above embodiment, the present invention can be applied to the demodulator of the synchronous detection system as it is.

In the above embodiment, the reproduction clock cycle is divided into four time slots, but the reproduction clock phase control may be extended by dividing the reproduction clock cycle into four or more time slots.

[0029]

As described above, according to the present invention, PSK
In a clock recovery circuit of a demodulator of a type that detects a modulated wave and generates a corresponding phase angle signal θ, an offset circuit for offsetting the phase angle signal θ of the demodulator by a predetermined angle is provided. The points can be detected efficiently with a simple configuration.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a clock recovery circuit according to an embodiment.

FIG. 3 is a diagram illustrating a method of detecting a data conversion point according to the embodiment.

FIG. 4 is a diagram illustrating a method of detecting a data conversion point according to the embodiment.

FIG. 5 is an operation timing chart of the clock recovery circuit according to the embodiment.

FIG. 6 is a block diagram of a conventional clock recovery circuit.

[Explanation of symbols]

 100 Demodulator 3 Offset circuit 4 Edge detection circuit 5 Phase comparison circuit 6 Clock generation circuit

Claims (3)

[Claims] 1. A clock recovery circuit of a demodulator of a type that detects a PSK modulated wave and generates a corresponding phase angle signal (θ), an offset for offsetting the phase angle signal (θ) of the demodulator by a predetermined angle. A circuit (3), an edge detection circuit (4) for detecting a predetermined data conversion point of received data based on an output of the offset circuit (3), a data conversion point detected by the edge detection circuit (4) and a reproduction clock A phase comparison circuit (5) for performing phase comparison with a signal, and a clock generation circuit (6) for generating a regenerated clock signal so as to make the phase difference constant based on the phase difference detected by the phase comparison circuit (5). And a clock recovery circuit. 2. The phase comparison circuit (5) divides the reproduction clock cycle into four or more time slots, and the size is different according to the correspondence between each divided time slot and the detected data conversion point. The clock recovery circuit according to claim 1, wherein two or more types of phase difference signals are output. 3. A clock generation circuit (6) filters post-detection signals having a small phase difference and selects them as post-selection means (6 ₃ ).
Minute high-speed reference clock signal in response to the output of the first path to be input, a second path entering the direct selection means a detection signal of greater phase difference (6 _3), selection means (6 ₃₎ A frequency divider (6 ₂ ) for variably controlling the frequency ratio, and the selecting means (6 ₃ ) normally selects the first path, and selects the second path when the clock phase is fast pulled in. The clock recovery circuit according to claim 2, wherein the clock recovery circuit is controlled.