JPH06252965A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To ensure the initial synchronization of clock phases by a short redun dant bit in a digital radio communications. CONSTITUTION:A demodulating circuit for digital phase modulated signals is provided with a modulated signal phase detecting circuit 10 which outputs the phase of a received phase modulated signal, a k-time difference circuit 12 which outputs the difference between the phase modulates signal and a signal delayed by a single symbol period by k (k>=2) times, the clock phase estimating integration circuits 60 and 61 which acquire the signals used for estimation of the clock phase based on the output of the circuit 12, a clock phase estimating circuit 70 which estimates the initial clock phase based on the outputs of the circuits 60 and 61, and a clock timing selecting circuit 80 which selects the clock timing based on the clock phase information estimated by the circuit 70.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase modulation signal clock recovery circuit suitable for digital radio communication.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional baseband digital clock recovery circuit for a .pi. / 4 shift QPSK modulated signal. Also, the case where the received signal sample rate is the double symbol rate is taken as an example. The modulation signal phase detection circuit 10 detects the modulation signal phase of the received π / 4 shift QPSK modulation signal A.

An example of the modulation signal phase detection will be described with reference to FIG. First, the modulation signal A is converted into an intermediate frequency in the modulation signal phase detection circuit 10, band-limited through a band filter, and then amplitude-limited. FIG. 8A shows an intermediate frequency signal waveform, and FIG. 8B shows an amplitude-limited intermediate frequency signal waveform. By the way, π / 4 shift Q
In the PSK modulation method, the carrier wave envelope has a baud timing frequency component. Therefore, the baud timing is obtained by detecting this baud timing frequency component and inputting it to the phase locked loop. A baud timing signal which rises at this baud timing t ₀ is shown in FIG.

Next, the modulation signal phase detection circuit 10 is provided with a phase counter that is reset in synchronization with the baud timing t ₀ and counts a predetermined clock signal. ). In the modulation signal phase detection circuit 10, after detecting the baud timing t ₀ , the closest rising time t ₁ of the baud timing signal is detected. Then, the time from the baud timing t ₀ to the rising time t ₁ , that is, the relative phase of the intermediate frequency signal is detected based on the phase counter output.

The above-mentioned modulation signal phase detection technique is
For example, "Tomita et al.," Digital intermediate frequency demodulation method ",
B-299, 1990 Autumn National Conference of the Institute of Electronics, Information and Communication Engineers ". Instead of this, the one described in "Yamamoto et al.," A study on π / 4 shift QPSK baseband differential detector ", B-342, 1992 Spring National Convention of the Institute of Electronics, Information and Communication Engineers" may be used. .

The modulation signal phase detection circuit 10 outputs the modulation signal phase B at a double symbol rate with the clock signal L2 and a clock having a phase difference of only half symbols. However, here, the clock phase has a uniformly random value. The 1-symbol difference circuit 20 outputs a difference signal C between the signal B and a signal obtained by delaying the signal B by 1 symbol period. Next, zero cross detection type clock phase advance /
The delay detection circuit 90 performs zero-cross detection using the signal C and outputs a signal Q corresponding to the advance or delay from the clock phase identification point.

Here, the time series of the signal C is Ci = C (i ^*
T / 2), (i = 0,1,2, ...), T is a symbol period, and an even number of the subscript i is a signal to be the discrimination point timing. First, the zero-cross Ci ^* Ci + 2 <0 equation (1) of the signals Ci and Ci + 2 is detected. Next, the relationship between the polarity of the signal Ci and the polarity of the signal Ci + 1 between Ci and Ci + 2 is examined,

Ci + 1 ^* Ci> 0 In the case of Expression (2), a clock phase lead is output, and when Ci + 1 ^* Ci <0 (3) is detected, a signal Q indicating a clock phase delay is output. .

The signal Q is input to the variable filter stage digital filter 101 and filtered to become a signal R2 which gives a clock correction direction. The frequency division variable clock signal generator performs clock reproduction by advancing or delaying the clock phase according to the signal R2. In the case of clock initial synchronization, the number of filter stages of the digital filter is reduced to increase the frequency of generation of the signal R2 that gives the clock correction direction, or the division ratio of the reference signal U is decreased to increase the clock phase correction width. A method of accelerating the clock initial synchronization by doing so.

[0010]

However, in the conventional clock recovery method, clock recovery is performed by feedback in principle, and it is necessary for the clock initial synchronization even when the method of accelerating the clock initial synchronization is used. There was a limit to the reduction of redundant bits. In addition, when there is a carrier frequency error, the zero-cross method increases the jitter at the zero-cross point and increases the recovered clock error. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a clock recovery circuit capable of performing clock phase initial synchronization with a short redundant bit.

[0011]

In order to solve the above problems, according to the structure of claim 1, a modulation signal phase detection circuit for outputting the phase of the received phase modulation signal in the demodulation circuit of the digital phase modulation signal is provided. A k-time difference circuit that outputs a difference from a signal delayed by one symbol period k (k ≧ 2) times, and a clock-phase estimation integration circuit that obtains a signal used for clock phase estimation based on the k-time difference circuit output A clock phase estimation circuit that estimates the initial clock phase from the output of the clock phase estimation integration circuit; and a clock timing selection circuit that selects clock timing based on the clock phase information estimated by the clock phase estimation circuit. It is characterized by doing. Further, in the configuration according to the second aspect, a zero cross detection type clock phase lead / lag detection circuit and a digital filter are further provided to detect lead or lag of the clock timing of the clock reproduced by this. However, the clock timing is adjusted according to the detection result.

[0012]

In the structure according to the first aspect, in the demodulation circuit for the digital phase modulation signal, the modulation signal phase detection circuit outputs the phase of the reception phase modulation signal, and the k-time difference circuit outputs 1 phase.
The difference from the signal delayed by the symbol period is k (k ≧ 2) times and output. Next, in the clock phase estimation integrating circuit, a signal used for clock phase estimation is obtained based on the k-times difference circuit output. Also, the clock phase estimation circuit
The initial clock phase is estimated from the output of the clock phase estimation integration circuit. Then, the clock timing selection circuit selects the clock timing based on the clock phase information estimated by the clock phase estimation circuit. Further, in the configuration according to the second aspect, the zero-cross detection type clock phase advance / delay detection circuit detects the phase advance / delay, and the digital filter performs filtering. As a result, the advance or delay of the clock timing of the reproduced clock is detected, and the clock timing is adjusted according to the detection result.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention for a .pi. / 4 shift QPSK modulated signal. The case where the received signal sample rate is the double symbol rate and the k-time difference circuit is a two-time difference circuit is taken as an example. Receive π / 4
The shift QPSK modulation signal A is a modulation signal phase detection circuit 10
The modulation signal phase is detected at (see the prior art section). The modulation signal phase detection circuit 10 uses the clock signal L1.
Further, the modulation phase signal B is output at a double symbol rate by a clock having a clock phase difference of half symbol from L1 and L1. However, here, the clock phase has a uniformly random value.

The signal B is a differential signal Ci = C from the signal delayed by one symbol period by the one-symbol difference circuit 20.
(I ^* T / 2), (i = 0,1,2, ...), and in the case of performing the clock initial synchronization, the signal is sent by the switch 30 to the 1-symbol difference circuit 40 and further delayed by 1-symbol cycle. The difference signal Di = D (i ^* T / 2), (i = 0,1,
2, ...) The two-time difference signal Di is SP-converted by the serial-parallel converter 50 to be Ej = D2j, Fj = D2j + 1, (j = 0,1,2, ...) (See FIG. 3). The signals Ej and Fj are input to the clock phase estimating integration circuits 60 and 61, respectively, and the signals Ej and Fj are inverted every other number of M symbols, integrated, and then divided by M to obtain signals G and H. That is, the signals G and H are expressed by the following equations (4) and (5).
It becomes the street.

[0015]

[Equation 1]

[Equation 2]

The clock phase estimation circuit 70 uses the signals G and H.
The clock phase is estimated based on. π / 4 shift QPSK
In the modulation method, the values of the signals G and H when the (1,0,0,1,1,0, ..) series alternating signal (see FIG. 3) is input are shown in FIG.
Shown in. As can be seen from this figure, the clock phase can be uniquely determined by the combination of the signals G and H. The clock phase estimation circuit 70 can be realized by calculating the values of the signals G and H corresponding to the clock phase and writing them in the ROM having the signals G and H as addresses, but a method effective for reducing the ROM capacity will be described. As an example, the clock timing is estimated with an accuracy of 1/32 of one symbol period (N = 32).

First, the absolute values of the signals G and H are compared and the smaller one is selected, and then the k value corresponding to the selected value is selected according to the rule shown in FIG. Further, using the k value, the calculation shown in FIG. 7 is performed by the magnitude relationship and the sign relationship between the signals G and H to estimate the clock phase. In this method, the clock phase is estimated using the values in the thick line portion in FIG. 4, and the selection of the k value can be easily realized by a ROM having a small capacity as compared with the method using the signals G and H as addresses. The sampling timing selection circuit 80 selects a clock signal corresponding to the signal J indicating the clock phase output from the clock phase estimation circuit 70 among the clock signals having different phases generated by the oscillator of N times the symbol rate. The reproduction clock L1 is output. An example of the clock phase estimation error is shown in FIG.

After the clock initial synchronization, when the clock phase error gradually occurs due to the symbol rate of the received signal and the frequency error of the clock signal generated by the reference signal generator, the zero-cross detection type clock phase advance / delay described in the conventional method. A detection circuit and a circuit using a digital filter are added, and a sampling timing selection circuit 80 selects a clock signal having a lead / lag of a clock phase compared with the clock signal reproduced by the above method, and holds clock synchronization. To do. In this embodiment, the π / 4 shift QPSK modulation signal has been described as an example, but it is also applicable to other phase modulation methods such as QPSK.

As described above, according to the clock recovery circuit of the present invention, it is possible to perform the clock phase initial synchronization with a redundant bit shorter than the conventional one by estimating the clock phase during the clock phase initial synchronization. Is. The clock initial phase estimation circuit enables stable clock phase initial synchronization regardless of the presence or absence of the carrier phase frequency error of the received signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an example.

FIG. 2 is a block diagram of a conventional clock recovery circuit.

FIG. 3 is an explanatory diagram of a clock phase signal.

FIG. 4 is an explanatory diagram of an estimated clock phase.

FIG. 5 is a diagram showing a clock phase estimation error.

FIG. 6 is a diagram showing a phase estimation rule.

FIG. 7 is a diagram showing a phase estimation rule.

FIG. 8 is an operation explanatory diagram of a conventional clock recovery circuit.

[Explanation of symbols]

10 modulation signal phase detection circuit 20 1-symbol difference circuit 30 switch 40 1-symbol difference circuit 50 serial-parallel conversion 61, 62 clock phase estimation integration circuit 70 clock phase estimation circuit 80 clock timing selection circuit 90 zero-cross detection type clock phase lead / lag Detection circuit 100 Digital filter 101 Variable number of filter stages Digital filter 110 Variable division ratio Clock signal generator 120 Reference signal generator

Claims (2)

[Claims] 1. A digital phase modulation signal demodulation circuit that outputs a phase of a reception phase modulation signal by a modulation signal phase detection circuit and a signal delayed by one symbol period k times (k ≧ 2) times and outputs k Time difference circuit, a clock phase estimation integration circuit that obtains a signal used for clock phase estimation based on the k-time difference circuit output, and a clock phase estimation circuit that estimates the initial clock phase from the clock phase estimation integration circuit output And a clock timing selection circuit that selects a clock timing based on the clock phase information estimated by the clock phase estimation circuit. 2. A zero-cross detection type clock phase advance / delay detection circuit and a digital filter are provided to detect the advance or delay of the clock timing of the reproduced clock, and the clock timing is detected according to the detection result. The clock recovery circuit according to claim 1, wherein