JP3228395B2 - Clock recovery circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for phase modulation in digital radio communication.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration example of a conventional baseband digital clock recovery circuit for a π / 4 shift QPSK modulation signal. Hereinafter, a case where the received signal sample rate is the double symbol rate will be described as an example. Modulation signal phase detection circuit 10 detects a modulation signal phase of received π / 4 shift QPSK modulation signal A (hereinafter, referred to as modulation signal A).

[0003] An example of the modulation signal phase detection performed by the modulation signal phase detection circuit 10 will be described below with reference to FIG. First, the modulation signal A is converted into an intermediate frequency signal in the modulation signal phase detection circuit 10 (see FIG. 6A). Then, the intermediate frequency signal is band-limited via a band-pass filter built in the modulation signal phase detection circuit 10 and then amplitude-limited (see FIG. 6B).

Further, the modulation signal phase detecting circuit 10 is provided with a phase counter, and the phase counter counts the carrier phase of the intermediate frequency signal in synchronization with the intermediate frequency signal. FIG. 6C shows how the count value changes. On the other hand, the clock generation circuit 260 (see FIG. 5) inputs the reproduced clock signal rising at the symbol timing t0 to the modulation signal phase detection circuit 10, as shown in FIG. After detecting the symbol timing t0, the modulation signal phase detection circuit 10 captures the first rising point t1 of the intermediate frequency signal, and determines the count value of the phase counter at the rising point t1 as the relative phase of the intermediate frequency signal (that is, the modulation phase). (The phase of the signal A).

[0005] The above-described modulation signal phase detection technique uses:
For example, Tomita et al., “Digital Intermediate Frequency Demodulation Method”,
B-299, 1990 IEICE Autumn National Convention ". Alternatively, the technology described in “Yamamoto et al.,“ Study of π / 4 shift QPSK baseband delay detector ”, B-342, 1992 IEICE Spring National Convention” may be used.

The modulation signal phase detection circuit 10 shown in FIG. 5 outputs the phase signal B at a double symbol rate by using the clock signal L1 and a clock having a clock phase difference of a half symbol from the clock signal L1. However, here, the clock phase has a uniformly random value. Next, the one-symbol difference circuit 210 outputs a difference signal C between the signal B and a signal obtained by delaying the signal B by one symbol period. Further, one symbol difference circuit 220
Calculates the difference of the one-time difference signal C and performs the two-time difference signal D
And

[0007] The serial-parallel converter 230 is based on the above 2
The time difference signal D is subjected to serial-parallel conversion, and the respective values are input to clock phase estimation integration circuits 240 and 241. The clock phase estimating integration circuit 240 integrates the input signal from the serial / parallel converter 230 after inverting the sign for each sample and then dividing it by the number of input samples to output the signal G. Similarly, clock phase estimating integration circuit 241
Converts the input signal from the serial / parallel converter 230 to 1
After sign-inverting and integrating for each sample, the signal is divided by the number of input samples and output as a signal H.

The ROM 250 outputs an estimated value of the clock phase based on the signals G and H. π / 4 shift Q
In the PSK modulation method, (10, 01, 10, 0
1. . FIG. 7 shows the values of the signals G and H when the alternating signal of the series is input. In FIG. 7, the absolute value (| G |) of the signal G and the absolute value (| H |) of the signal H are compared, and the minimum value, that is, min (| G |, |
H |) is indicated by a thick line. As can be seen from the bold line shown in this figure, the combination of the signals G and H and the clock phase correspond one-to-one. Accordingly, in the ROM 250, the signals G and H are stored in an area having the signals G and H as addresses.
May be written in advance.

Next, a clock generation circuit 260 shown in FIG.
Divides the output signal of the reference signal generator 110 to generate clock signals having different phases. Then, the clock generation circuit 260 selects the clock phase J output from the ROM 250 from the clock signals having different phases.
And outputs the clock signal as the reproduction clock L1. By the above operation,
A reproduction clock L1 is obtained.

After the initial clock synchronization, the symbol rate of the received signal and the frequency error of the reference signal generator 110 cause
A clock phase error may gradually occur. On the other hand, a clock generation circuit 260 is provided by adding a zero-cross detection type clock phase advance / delay detection circuit 90 and a digital filter 100 to the above-described clock recovery circuit.
In comparison with the clock signal reproduced in the above, a clock signal having a lead / lag of the clock phase is selected, and the clock synchronization is maintained.

At this time, the zero-cross detection type clock phase advance / delay detection circuit 90 includes a one-symbol difference circuit 210.
Performs a zero-crossing detection using the one-time difference signal C output by the controller, and outputs a signal Q corresponding to the advance or delay from the discrimination point of the clock phase. Here, it is assumed that the time sequence of the one-time difference signal C is Ci = C (i * T / 2). Where i =
0, 1, 2,. . . Where T is the symbol period, and the even-numbered subscript i is the signal to be the identification point timing.

First, the zero crossing of the signals Ci and Ci + 2 is detected so that the following equation (1) holds. Ci * Ci + 2 <0 (1) Next, the zero-cross detection type clock phase advance / delay detection circuit 90 outputs the signal Ci. Polarity and the polarity of signal Ci + 1 (signal C
(i + 1 is the signal between the signals Ci and Ci + 2). When the following equation (2) holds, the output signal Q is used as a signal indicating the advance of the clock phase.
When the following equation (3) holds, the output signal Q is output as a signal indicating a clock phase delay. Ci + 1 * Ci> 0 (2) Ci + 1 * Ci <0・ ・ ・ ・ ・ ・ ・ ・ ・ (3)

The signal Q is supplied to the digital filter 100
And a signal R1 for providing a clock correction direction. The clock generation circuit 260 corrects the phase of the reproduced clock L1 based on the signal R1. In addition,
The above-described clock recovery technique is described in a patent application "Clock recovery circuit, Japanese Patent Laid-Open No. 6-252964".

[0014]

However, the conventional clock recovery circuit described above has a problem that sufficient clock phase estimation accuracy cannot be obtained in a frequency selective fading line in which a plurality of delayed waves exist. Was. In the frequency-selective fading channel, the amplitude of the differential signal C once and the differential signal D twice greatly fluctuate due to distortion of the transmission line frequency characteristic caused by the delay wave. In the conventional circuit, the method of converting the amplitude value of the difference signal D twice into the clock phase estimation value is used, so that a clock phase estimation error occurs due to the amplitude fluctuation.

The present invention has been made under such a background, and it is possible to estimate a clock initial phase with short redundant bits, and to obtain a highly accurate clock phase estimation characteristic even in a frequency selective fading channel. It is an object of the present invention to provide a clock recovery circuit having the same.

[0016]

According to the first aspect of the present invention,
A demodulation circuit for a digital phase modulation signal, a modulation signal phase detection means for detecting a phase of the received digital phase modulation signal, and a phase detected by the modulation signal phase detection means after one symbol period of the digital phase modulation signal. K (k ≧ 1) times to calculate the difference between the calculated phase and the k-th difference value, a correlation value between the k-th difference value and the cosine waveform, and a k-th difference value. Based on clock phase estimation correlation means for obtaining a correlation value with a sine waveform, and based on an arc tangent of a ratio of the two correlation values,
A clock phase estimating unit for obtaining a clock phase of the digital phase modulation signal; and a clock generating unit for outputting a clock signal having a phase equal to the clock phase obtained by the clock phase estimating unit.

According to a second aspect of the present invention, in the clock recovery circuit according to the first aspect, the clock phase estimating correlating means converts the k-th differential value into two k-th differential values having different half symbol period phases. Serial-parallel conversion means for serial-to-parallel conversion, code alternation means for alternately inverting the signs of the two k-time difference values output by the serial-parallel conversion means, and two k times output from the code alternation means. After integrating each of the difference values over a predetermined section, each integral value is divided by the length of the section,
It is characterized by comprising a correlation value with the cosine waveform and integration means for outputting as a correlation value with the sine waveform.

According to a third aspect of the present invention, in the clock recovery circuit according to the first or second aspect, the clock signal output by the clock generation means is based on the k-time difference value output by the k-time difference means. A clock phase advance / delay detection circuit for detecting a phase advance or delay of the phase; and a digital filter for filtering an output signal of the zero cross detection type clock phase advance / delay detection circuit; Generating means based on an output value of the digital filter;
It is characterized in that the phase of the clock signal output by the clock generation means is adjusted.

[0019]

According to the first aspect of the invention, the k-th difference means calculates the difference between the phase detected by the modulation signal phase detection means and the phase detected one symbol period after the digital phase modulation signal by k ( k ≧ 1) times to obtain a difference value k times. Then, the correlation means for estimating the clock phase obtains a correlation value between the k-th difference value and the cosine waveform and a correlation value between the k-th difference value and the sine waveform. Further, the clock phase estimating means may calculate, based on an arctangent of a ratio of the two correlation values,
The clock phase of the digital phase modulation signal is obtained.

According to the second aspect of the present invention, the serial / parallel conversion means serially / parallel converts the k-time difference value into two k-time difference values having mutually different half symbol period phases. The code alternation means alternately inverts the signs of the two k-time difference values output by the serial / parallel conversion means. Further, the integrating means integrates each of the two k-time difference values output by the code alternation means over a predetermined section, and divides each integrated value by the length of the section.

According to the third aspect of the present invention, the zero-cross detection type clock phase advance / delay detection circuit detects the advance or delay of the phase of the clock signal output from the clock generation means. Then, the clock generator adjusts the phase of the clock signal output by the clock generator based on the detection result.

[0022]

【Example】

§1. First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a clock recovery circuit according to one embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG.
The description is omitted. Hereinafter, the received signal sample rate is 2
The case where the symbol rate is a double symbol rate and a one-time difference circuit is used as the k-time difference circuit will be described as an example.

In FIG. 1, reference numeral 10 denotes a modulation signal phase detection circuit, and reference numeral 20 denotes a one-symbol difference circuit, which are the same as those used in the conventional example. The clock phase estimation correlation circuit 30 includes a cosine waveform generation circuit 40, a sine waveform generation circuit 41, multiplication circuits 50 and 51, and integration circuits 60 and 61. At each address of the ROM 70, a clock phase calculated by a calculation formula described later is written in advance. The clock generation circuit 80 divides the input reference clock signal into clock signals having different phases, selects one of the clock signals, and outputs the selected clock signal as a reproduction clock L1. The reference signal generator 110 generates a clock signal having an N-times symbol rate. Reference numeral 90 denotes a zero-cross detection type clock phase advance / delay detection circuit, and reference numeral 100 denotes a digital filter, which is the same as that used in the conventional example.

Next, the operation of the clock recovery circuit having the above configuration will be described. The modulation signal phase detection circuit 10 detects the modulation signal phase of the modulation signal A (the received π / 4 shift QPSK modulation signal A) using the same method as in the related art. Then, the modulation signal phase detection circuit 10 outputs the modulation phase signal B at a double symbol rate using the clock signal L1 and a clock having a clock phase difference of a half symbol from the clock signal L1. However, here, the clock phase has a uniformly random value. Next, the one-symbol difference circuit 20 calculates a one-time difference signal Ci = C (i * T / i) between the signal B and a signal obtained by delaying the signal B by one symbol period.
Find 2). Here, i = 0, 1, 2,. . .
And T is the symbol period.

FIG. 2 is a graph showing the value of the one-time difference signal Ci when a (10,01,10,01 ...) sequence of alternating signals is input in the π / 4 shift QPSK modulation system. is there. As is apparent from FIG.
The time difference signal Ci is approximated by a sine wave having a period of two symbols. Therefore, the clock phase can be estimated by detecting the phase θ of the sine wave. In order to determine the phase θ of the sine wave, the correlation value E between the one-time difference signal Ci and the cosine waveform having the same cycle and the correlation value F between the one-time difference signal Ci and the sine waveform having the same cycle are calculated as follows. Expressions (4) and (5)
And the inverse tangent of the ratio of the values E and F may be calculated as in equation (6).

(Equation 1)

(Equation 2) θ = tan ⁻¹ (F / E) (6) where M is the length of the section for performing the clock phase estimation calculation ( (Unit: symbol).

Therefore, the clock phase estimating correlation circuit 30 shown in FIG. 1 calculates the above equations (4) and (5) according to the following procedure. First, the multiplication circuit 50
The one-time difference signal Ci is multiplied by a cosine value supplied from the cosine waveform generation circuit 40. Next, the integration circuit 6
0 integrates the multiplication result of the multiplication circuit 50, divides it by M, and outputs the division result as a signal E. Similarly, the multiplication circuit 51 multiplies the one-time difference signal Ci by the sine value supplied from the sine waveform generation circuit 41. Next, the integration circuit 61 integrates the multiplication result of the multiplication circuit 51,
The signal is divided by M, and the result of the division is output as a signal F.

As shown in FIG. 2, the one-time difference signal C
The average value of i changes depending on the presence or absence of the carrier frequency deviation, but the change does not affect the values of E and F. In the frequency selective fading channel, the differential signal C
Although the amplitude of i fluctuates, the amplitude fluctuation is canceled by the numerator and the denominator when performing the calculation of Expression (6), so that it does not affect the estimation result of the clock phase.

The values E and F calculated by the clock phase estimation correlation circuit 30 are stored in the ROM 70 shown in FIG.
Entered as an address. As described above, the ROM 7
At each address of 0, the clock phase value θ corresponding to the address values E and F is calculated and written based on the above equation (6). Therefore, the ROM 70 outputs the clock phase value θ corresponding to the addresses E and F as a signal J.

The clock generation circuit 80 divides the frequency of the output signal of the reference signal generator 110 to generate clock signals having different phases. Then, the clock generation circuit 80
Is the ROM 70 out of the clock signals having different phases.
A clock signal having the same phase as the output signal J (clock phase θ) is selected, and the clock signal is output as the reproduced clock L1. By the above operation, the reproduced clock L1 is obtained. If a clock phase error occurs due to the symbol rate of the received signal and the frequency error of the reference signal generator 110 after the initial clock synchronization, the zero-crossing detection type clock phase lead / lag detection circuit 90 and the digital filter 100 To maintain clock synchronization in the same manner as in the conventional example.

FIG. 3 is a graph showing the bit error rate characteristics of a demodulator using the clock recovery circuit according to the present embodiment and the bit error rate characteristics of a conventional demodulator obtained by experiments. In this experiment, the transmission rate was 384 kbps, the modulation scheme was a π / 4 shift QPSK scheme, the demodulation scheme was synchronous detection, and the fading was a fading frequency of 16 Hz.
Assuming two-wave equal-level Rayleigh fading with a delay time difference of 500 ns, the number of symbols M used for clock phase estimation
Is 16 symbols. From FIG. 3, it can be seen that the present invention improves the error floor of the bit error rate characteristic to about １ ／.

Finally, the correspondence between the first embodiment and the present embodiment will be described. Modulation signal phase detection means ... Modulation signal phase detection circuit 10 k times difference means ... 1 symbol difference circuit 20 Clock phase estimation correlation means ... Clock phase estimation correlation circuit 30 Clock phase estimation means ... ROM 70 Clock generation means ... ... Clock generation circuit 80, reference signal generator 110

§2. Second Embodiment Next, a second embodiment of the present invention will be described. In the clock recovery circuit according to the present embodiment, in the clock recovery circuit shown in FIG. 1, the clock phase estimation correlation circuit 30 is replaced with the clock phase estimation correlation circuit 31 shown in FIG. Note that the clock recovery circuit shown in this embodiment
This circuit can be applied as a means for easily calculating the correlation values E and F only when the circuit operates at the double symbol rate. When the clock recovery circuit operates at a symbol rate other than the double symbol rate, Cannot be applied.

That is, when the circuit operates at the double symbol rate, the time t in the above equations (4) and (5)
i is ti = 0, T / 2, T, 3T / 2,. . . It changes like Therefore, cos (πti / T) in equation (4)
Are 1,0, -1,0,1,. . . And the equation (5)
Sin (πti / T) at 0, 1, 0, −1,
0,. . . And change. Therefore, the above equation (4),
(5) can be modified as in the following equations (7) and (8).

(Equation 3)

(Equation 4) The clock phase estimation correlation circuit 31 shown in FIG. 4 is a circuit that performs the calculations of the above equations (7) and (8).

Next, the operation of the clock reproducing apparatus having the above configuration will be described. As in the first embodiment, when the modulation phase detection circuit 10 outputs the modulation phase signal B and the one-symbol difference circuit 20 calculates the one-time difference signal C based on the modulation phase signal B, the one-time difference The signal C is input to the clock phase estimation correlation circuit 31 (see FIG. 4). Then, the one-time difference signal C is subjected to serial-parallel conversion by the serial / parallel converter 42, and then the sign is inverted by the code alternation circuits 52 and 53 every two symbol periods. Next, the integration circuits 60 and 61
, And are divided by M to obtain signals E and F. The signals E and F are supplied to the ROM shown in FIG.
70 is input. Subsequent processing is the same as the operation of the first embodiment, and a description thereof will be omitted.

Finally, the correspondence between the second aspect of the present invention and this embodiment will be described. Clock phase estimating correlating means Clock phase estimating correlating circuit 31 Serial / parallel converting means Serial / parallel converter 42 Code alternation means Code alternation circuits 52, 53 Integrating means Integrating circuits 60, 61

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and changes in design and the like can be made without departing from the gist of the present invention. Even if there is, it is included in the present invention. For example, in the above-described embodiment, a description has been given of a π / 4 shift QPSK modulation signal as an example, but the present invention is similarly applicable to other phase modulation methods such as the QPSK method.

[0037]

As described above, according to the clock recovery circuit of the present invention, the clock phase is estimated by using the correlation value between the cosine waveform and the sine waveform during the initial synchronization of the clock phase, so that the frequency selective fading is performed. Even in a line, initial clock phase synchronization can be accurately performed in a short time. Also, stable initial clock phase synchronization can be performed regardless of the presence or absence of a carrier phase frequency deviation of the received modulation signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing a value of a one-time difference signal Ci according to the embodiment.

FIG. 3 is a graph showing a bit error rate characteristic of a demodulator using the clock recovery circuit according to the embodiment and a bit error rate characteristic of a conventional demodulator.

FIG. 4 is a block diagram showing a configuration of a clock phase estimation correlation circuit 31 according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a conventional clock recovery circuit.

FIG. 6 is an explanatory diagram illustrating a phase detection method of the modulation signal phase detection circuit 10.

FIG. 7 is an explanatory diagram showing a clock phase estimation rule in a conventional clock recovery circuit.

[Explanation of symbols]

10: Modulation signal phase detection circuit, 20, 210, 220
... 1-symbol difference circuit, 30, 31 ... correlation circuit for clock phase estimation, 40 ... cosine waveform generation circuit, 4
1 ... sine waveform generation circuit, 42, 230 ... serial-parallel converter, 50, 51 ... multiplication circuit, 52, 5
3 ... Alternating circuit, 60, 61 ... Integrating circuit, 7
0, 250 ROM, 80, 260 clock generation circuit 90 90 clock phase lead / lag detection circuit of zero cross detection type 100 digital filter 110
…… Reference signal generator, 240, 241 …… Integration circuit for clock phase estimation

Continuation of the front page (56) References JP-A-6-252964 (JP, A) JP-A-6-252965 (JP, A) JP-A-8-331191 (JP, A) Yoichi Matsumoto, Shuji Kubota, Shuzo Kato , Π / 4 shift QPSK modulation clock recovery circuit, 1993 IEICE Spring Conference Proceedings, Japan, The Institute of Electronics, Information and Communication Engineers, March 15, 1993, Volume 2, p. 318 (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (3)

(57) [Claims] 1. A demodulation circuit for a digital phase modulation signal, comprising: a modulation signal phase detection means for detecting a phase of a received digital phase modulation signal; and a demodulation circuit for detecting the phase detected by the modulation signal phase detection means. A k-th difference means for performing a difference calculation with a phase detected after one symbol period (k ≧ 1) times to obtain a k-th difference value; a correlation value between the k-th difference value and a cosine waveform; clock phase estimating correlation means for obtaining a correlation value between a k-th difference value and a sine waveform; and clock phase estimating means for obtaining a clock phase of the digital phase modulation signal based on an arctangent of a ratio of the two correlation values. Clock generating means for outputting a clock signal having a phase equal to the clock phase obtained by the clock phase estimating means. Click regeneration circuit. 2. The clock recovery circuit according to claim 1, wherein the clock phase estimating correlator serially / parallel converts the k-th difference value into two k-th difference values having mutually different half symbol cycle phases. Parallel conversion means, code alternation means for alternately inverting the signs of the two k-times difference values output by the serial-parallel conversion means, and predetermined two k-times difference values output by the code alternation means, respectively. And integrating means for dividing each integral value by the length of the section and outputting as a correlation value with the cosine waveform and a correlation value with the sine waveform. And a clock recovery circuit. 3. The clock recovery circuit according to claim 1, wherein a phase of a clock signal output by said clock generation means is determined based on a k-time difference value output by said k-time difference means. A zero-cross detection type clock phase advance / delay detection circuit for detecting advance / delay; and a digital filter for filtering an output signal of the zero-cross detection type clock phase advance / delay detection circuit; A clock recovery circuit for adjusting a phase of a clock signal output by said clock generation means based on an output value of a filter.