JPH0766843A - Carrier recovery system - Google Patents

Abstract

PURPOSE:To obtain the carrier recovery system by entire digital processing applicable to even a communication system with a high transmission rate by forming a phase locked loop with quick response. CONSTITUTION:A discrimination feedback equalizer 102 is separated into a forward equalizer 21 and a backward equalizer 22 and a complex multiplier 18 is arranged between them. Since the backward equalizer 22 is a backward type transversal filter in which a signal filtering output discrimination signals from discrimination devices 9, 10 and a synchronization detection signal from the complex multiplier 18 are added by an adder and the sum is outputted to the discrimination devices 9, 10, the output synchronization detection signal of the complex multiplier 18 is directly outputted without being delayed in the backward equalizer 22. Thus, the delay of the carrier in the phase locked loop is not large. Furthermore, the discrimination feedback loop consists of the discrimination devices 9,10 and the backward equalizer 22 and does not include the complex multiplier 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier recovery system,
In particular, the present invention relates to a carrier recovery system used in combination with a decision feedback equalizer on the receiving side of a digital wireless communication system using a multi-valued quadrature amplitude modulation system or a multi-phase modulation system.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional carrier recovery system. In the figure, the intermediate frequency band digital modulation signal input from the input terminal 1 is branched into two,
It is supplied to multipliers 4 and 5, respectively. The multiplier 4 multiplies the input digital modulated signal in the intermediate frequency band and the output reproduction carrier of the voltage controlled oscillator (VCO) 17, and outputs the P-channel analog baseband signal subjected to synchronous detection. On the other hand, the multiplier 5 multiplies the input digital modulated signal in the intermediate frequency band by the signal obtained by phase-shifting the output signal of the VCO 17 by π / 2 by the phase shifter 3 to synchronously detect the Q channel analog baseband. Output a signal.

The P-channel analog baseband signal extracted from the multiplier 4 is supplied to the A / D converter 6 where it is sampled and quantized. The Q channel analog baseband signal extracted from the multiplier 5 is supplied to the A / D converter 7 where it is sampled and quantized.

The output digital signals of the A / D converters 6 and 7 are supplied to a decision feedback equalizer 31, where equalization of intersymbol interference is performed. This decision feedback equalizer 3
The equalized P-channel digital signal sequence and the equalized Q-channel digital signal sequence output from 1 are input to the determiners 9 and 10, respectively, and their logical values are determined.

The P-channel determination signal output from the determiner 9 is output to the output terminal 14 and the phase error detector 1
The P-channel error signal input to 1 and also output from the determiner 9 is input to the phase error detector 11. Similarly, the Q channel determination signal output from the determiner 10 is output to the output terminal 15 and the phase error detector 11, and the Q channel error signal output from the determiner 10 is also the phase error detector. 11 is input.

The phase error detector 11 receives the carrier wave of the input digital modulation signal in the intermediate frequency band and the output signal of the VCO 17 based on the P channel judgment signal, the P channel error signal, the Q channel judgment signal and the Q channel error signal. , And outputs a phase error signal of a level corresponding to the detected phase error. This phase error signal is smoothed by the loop filter 16 and then applied to the VCO 17 as a control voltage. As a result, a signal phase-locked with the carrier wave of the input digital modulation signal in the intermediate frequency band, that is, a reproduced carrier wave is taken out from the VCO 17.

As described above, in this conventional carrier recovery system, the decision feedback equalizer 31 is included in the phase locked loop (PLL) from the detection of the phase error to the control of the phase of the reproduced carrier. It is said that.

The decision feedback equalizer 31 is a circuit used to equalize intersymbol interference due to frequency selective fading that occurs in a propagation path of a digital radio communication system, and is conventionally known (eg Muroya).・ Yamamoto, "Digital radio communication", Chapter 6, Industrial books). That is, as an example of the decision feedback equalizer, the one-dimensional 5
To explain the tap decision feedback equalizer 200,
The decision feedback equalizer 200 includes a front equalizer 201, a rear equalizer 202, and a decider 54.

The front equalizer 201 first multiplies the first and second delay circuits 42 and 43 each having a delay time of the symbol interval T by a predetermined tap coefficient.
Through third multipliers 44, 45 and 46 and the forward equalizer 2
The first adder 47 outputs an output signal of 01.

The operation of the forward equalizer 201 will be described. The demodulated digital signal sequence input to the input terminal 41 is branched into two, and the first delay circuit 42 and the first multiplier 44 respectively. Is entered. The input digital signal sequence delayed by the first delay circuit 42 by the time equal to the symbol interval T is input to the second multiplier 45, while the second digital signal sequence is input to the second multiplier 45.
Is further delayed by the delay circuit 43 for a time equal to the symbol interval T and input to the third multiplier 46.

The multiplier 44 multiplies the undelayed input digital signal sequence by the first tap coefficient C _-2 supplied from the control signal generating circuit (not shown) to obtain the first multiplication signal m. Outputs _-2 . Similarly, the multiplier 45 multiplies the input digital signal sequence delayed by the time T by the second tap coefficient C ₋₁ from the control signal generating circuit, and the multiplier 4
Reference numeral 6 multiplies the input digital signal sequence delayed by 2T by the third tap coefficient C ₀ from the control signal generating circuit to obtain the second multiplication signal m _-1 and the third multiplication signal m ₀ , respectively. Output. The first adder 47 adds and synthesizes these first to third multiplication signals m _-2 , m _-1 and m ₀ and outputs the result.

The backward equalizer 202 multiplies the third and fourth delay circuits 48 and 49 each having a delay time of the symbol interval T by a predetermined tap coefficient, and fourth.
And the fifth multipliers 50 and 51, and the second and third adders 52 and 53 have a backward structure.

To explain the operation of the rear equalizer 202, the signal obtained by judging the equalized digital signal sequence by the judging device 54 is output to the output terminal 55, while the third delay circuit 48 is output. Is delayed by a time equal to the symbol interval T and then supplied to the fourth multiplier 50, and further delayed by a time equal to the symbol interval T by the fourth delay circuit 49 and input to the fifth multiplier 51.

The multiplier 50 multiplies the output determination signal delayed by the time T by the fourth tap coefficient C ₊₁ from the control signal generating circuit and outputs a fourth multiplication signal m _+1. ,
The multiplier 51 multiplies the output determination signal delayed by 2T by the fifth tap coefficient C ₊₂ from the control signal generating circuit and outputs the fifth multiplication signal m ₊₂ . The second adder 52 receives these fourth and fifth multiplication signals m ₊₁ and m _+2.
Is added and synthesized.

The third adder 53 is the first adder 47.
To the first adder signal extracted from the second adder 52.
The second added signal extracted from is added to generate a third added signal, which is output to the determiner 54 as an equalized digital signal.

Next, another example of the conventional carrier recovery system will be described. FIG. 3 shows a block diagram of another example of the conventional carrier recovery system. 2, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 3, a quadrature quasi-synchronous detector 101 includes a local oscillator 2, a π / 2 phase shifter 3, and multipliers 4 and 5, and frequency-converts a digital modulation signal in the intermediate frequency band into a complex modulation signal in the baseband. . The local oscillator 2 fixedly oscillates and outputs a predetermined frequency.

The complex multiplier 8 is a decision feedback equalizer 3
The real part digital signal sequence and the imaginary part digital signal sequence from 1 are multiplied in parallel. The carrier wave regenerator 103 comprises a phase error detector 11, a loop filter 12 and a digital voltage controlled oscillator (VCO) 13.

Next, the operation will be described. The input digital modulation signal in the intermediate frequency band inputted from the input terminal 1 is branched into two and inputted to the multipliers 4 and 5, respectively. The multiplier 4 multiplies the input digital modulation signal in the intermediate frequency band by a local signal from the local oscillator 2 whose frequency is substantially equal to that of the carrier of the digital modulation signal in the intermediate frequency band. It outputs the real part of the complex modulation signal in the band.

On the other hand, the multiplier 5 converts the input digital modulated signal into a local signal from the local oscillator 2 by π / 2.
The imaginary part signal of the complex modulation signal in the quasi-coherently detected baseband band is output by multiplying the signal shifted by π / 2 by the phase shifter 3. The real part signal of the baseband analog complex modulation signal output from the multiplier 4 is supplied to the A / D converter 6 to be sampled and quantized. Further, the imaginary part signal of the analog complex modulation signal in the baseband output from the multiplier 5 is supplied to the A / D converter 7 and is sampled and quantized.

The output real part digital signal sequence of the A / D converter 6 and the output imaginary part digital signal sequence of the A / D converter 7 are supplied to the decision feedback equalizer 31 having the configuration described with reference to FIG. Intersymbol interference is equalized. The equalized real part digital signal sequence and imaginary part digital signal sequence output from the decision feedback equalizer 31 are respectively supplied to the complex multiplier 8, where the digital VCO in the carrier regenerator 103 is supplied.
Synchronous detection is not carried out until it is multiplied by the reproduced carrier in the base band from 13.

The equalized P-channel digital signal sequence and Q-channel digital signal sequence output from the complex multiplier 8 are input to the determiners 9 and 10, respectively, and are determined to be a P-channel determination signal and a Q-channel determination signal. After being processed, the signal is output to the output terminals 14 and 15, and is also supplied to the phase error detector 11 and the decision feedback equalizer 31.

The decision devices 9 and 10 output the P channel error signal and the Q channel error signal to the phase error detector 11, respectively. The phase error detector 11 receives the above-mentioned input P-channel decision signal, Q-channel decision signal, P-channel error signal and Q-channel error signal as input signals, and outputs from the carrier of the baseband complex modulation signal and the digital VCO 13. The phase error from the reproduced carrier wave is detected.

The phase error detection signal output from the phase error detector 11 is input to the loop filter 12, integrated and smoothed, and then applied to the digital VCO 13 as a control voltage. Control is performed so as to synchronize with the carrier wave of the complex modulation signal of the band. Therefore, the reproduced carrier wave synchronized with the carrier wave of the baseband complex modulation signal is output from the digital VCO 13.

As described above, in another example of the conventional carrier recovery system shown in FIG. 3, the complex multiplier 8 for synchronous detection is provided at the output side of the decision feedback equalizer 31 and the decision devices 9 and 1.
It is placed between the input side of 0. This is because synchronous detection must be performed before inputting to the determiners 9 and 10 in order to make a correct determination.

[0025]

Among the conventional carrier recovery systems described above, the former carrier recovery system shown in FIG. 2 includes a decision feedback equalizer 31 in the phase-locked loop, so that the loop The internal delay becomes large, and a phase-locked loop with fast response cannot be formed. Further, since the VCO 17 is composed of an analog circuit, it is necessary to adjust the circuit.

On the other hand, in the latter carrier recovery system shown in FIG. 3, the synchronous detection by the reproduced carrier is used as the decision feedback equalizer 31.
Of the decision feedback type equalizer 31 to determine between the output side and the input side of the decision devices 9 and 10, the decision signal obtained by determining the signals equalized by the decision feedback type equalizer 31 in the decision feedback type. The complex multiplier 8 for synchronous detection is arranged in the loop that returns to the equalizer 31.

However, since the decision feedback equalizer 31 needs to output the equalized signal and perform equalization using the signal to be decision-feedback at the symbol interval T, this decision feedback loop. The latter conventional method, in which the delay of the complex multiplier 8 is added, makes it difficult to operate at high speed and cannot be applied to a communication method having a high transmission rate. The present invention has been made in view of the above points, and an object of the present invention is to provide a carrier recovery method by an all-digital process that constitutes a phase-locked loop with a fast response and is applicable to a communication method with a high transmission rate. .

[0028]

In order to achieve the above object, the present invention frequency-converts an input digital modulation signal into a baseband complex modulation signal by a local signal having a frequency substantially equal to the carrier of the input digital modulation signal. A quadrature quasi-synchronous detector, an A / D converter for converting the output complex modulated signal of the quadrature quasi-synchronous detector into a digital signal, a forward equalizer for performing a forward equalization process on this digital signal, a forward equalizer, etc. A complex multiplier that performs synchronous detection by multiplying the output digital signal of the equalizer with the reproduced carrier wave, a backward equalizer that inputs the synchronous detection signal together with the determination signal, and performs equalization processing on the synchronous detection signal, and a backward equalizer A decision unit that produces and outputs the decision signal based on the equalized signal taken out from the equalizer and produces and outputs an error signal, and a decision signal taken out from the decision unit Based on the fine error signal to generate a recovered carrier which is synchronized with the carrier of the digital signal input to the complex multiplier, in which a structure having a carrier regenerator for inputting reproduced carrier to the complex multiplier.

[0029]

As described with reference to FIG. 4, the decision feedback equalizer comprises a front equalizer and a rear equalizer, and a digital signal forward-equalized by the front equalizer is converted into a rear equalizer. This is a configuration that is input and equalized. Therefore, in the present invention, the decision feedback equalizer is divided into a forward equalizer and a backward equalizer, and a complex multiplier for synchronous detection is arranged between the forward equalizer and the backward equalizer. It was done.

Here, the backward equalizer is a backward type transversal filter which outputs the signal obtained by filtering the decision signal and the synchronous detection signal from the complex multiplier by the adder to the decision unit. Therefore, the output synchronous detection signal of the complex multiplier is output to the decision unit immediately after being combined by the adder without being delayed in the backward equalizer. Therefore, the delay in the phase locked loop of the carrier does not increase. Further, since the decision signal is directly input to the backward equalizer, it is possible to prevent delay such as a complex multiplier from being added to the decision feedback loop.

[0031]

1 is a block diagram of an embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted. In FIG. 1, the decision feedback equalizer 102 is divided into a front equalizer 21 and a rear equalizer 22, and a complex multiplier 18 is arranged between them. Also,
The rear equalizer 22 is configured to receive the output determination signals of the determiners 9 and 10.

Next, the operation of this embodiment will be described.
The real part digital signal sequence and the imaginary part digital signal sequence extracted from the A / D converters 6 and 7 are input to the front equalizer 21. The front equalizer 21 has a two-dimensional structure, but basically, the one-dimensional front equalizer 2 shown in FIG. 4 is used.
Similarly to 01, a forward composed of a plurality of delay units with a symbol interval T, a plurality of multipliers for multiplying the output signals of the delay units and the tap coefficient, and an adder for synthesizing the output signals of the plurality of multipliers, respectively. Shape transversal filter.

The real part digital signal sequence and the imaginary part digital signal sequence which have been forward-equalized by the forward equalizer 21 are supplied to the complex multiplier 18 where the carrier wave regenerator 10 is supplied.
The signal is synchronously detected by being multiplied by the reproduced carrier wave from the digital VCO 13 in 3 and converted into a P channel digital signal sequence and a Q channel digital signal sequence.
The P-channel digital signal sequence and the Q-channel digital signal sequence synchronously detected by the complex multiplier 18 and extracted are input to the rear equalizer 22.

The backward equalizer 22 has a two-dimensional structure, but basically, the one-dimensional backward equalizer 202 shown in FIG. 4 is used.
Similarly, a plurality of delay units having a symbol interval T, a plurality of multipliers that multiply the output signal of the delay unit and the tap coefficient, and a first adder that combines the output signals of the plurality of multipliers, respectively. A signal obtained by filtering the determination signal extracted from the first adder and the P-channel digital signal sequence and the Q-channel digital signal sequence synchronously detected by the complex multiplier 18 are added by the second adder and output. The transversal filter performs a backward equalization process, and outputs a digital signal sequence that has been subjected to an equalization process of intersymbol interference together with the forward equalization process.

The equalized P-channel digital signal sequence and Q-channel digital signal sequence extracted from the backward equalizer 22 are input to the decision units 9 and 10, respectively, and are determined to be P-channel decision signal and Q-channel decision signal. Then, while being output to the output terminals 14 and 15, they are supplied to the phase error detector 11 and the rear equalizer 22, respectively.

Further, the error signals of the P channel and the Q channel extracted from the judging devices 9 and 10 (this is the judging device 9).
And 10 are signals indicating an error between the input signal and the output determination signal. ) Is a phase error detector 1 in the carrier regenerator 103.
1 is supplied. Then, a reproduced carrier wave that is synchronized with the carrier wave of the signal input to the complex multiplier 18 is generated from the digital VCO 13 and output to the complex multiplier 18.

As described above, according to this embodiment, the judging device 9
And 10, the carrier wave regenerator 103, the complex multiplier 18 and the backward equalizer 22, the carrier wave phase locked loop (PLL).
Is configured to reproduce the carrier wave, the backward equalizer 22 is included in the phase locked loop of the carrier wave.

However, as described above, the backward equalizer 22 filters the decision signals from the decision devices 9 and 10 and the P-channel digital signal sequence and the Q-channel digital signal which are synchronously detected by the complex multiplier 18. The P-channel digital signal sequence and the Q-channel digital signal sequence that have been synchronously detected by the transversal filter that adds the column and the second column by the second adder and outputs the same after the intersymbol interference is equalized by the second adder. It is immediately output as a signal after equalization.

Therefore, since it does not pass through the delay unit in the rear equalizer 22, the delay of the carrier wave in the phase locked loop does not become large. Therefore, according to the present embodiment, the first shown in FIG.
It is of course possible to form a phase-locked loop having a quicker response than the conventional method described in (1) above, and the delay of the rear equalizer 22 does not increase even when compared to the second conventional method shown in FIG. Therefore, according to this embodiment, it is possible to form a phase-locked loop having a fast response.

Further, the decision feedback loop which decides the equalized signal by the decision devices 9 and 10 and feeds the decision signal back to the decision feedback type equalizer is, in the present embodiment, the decision devices 9 and 10 and the backward and so on. 3 is different from the conventional system in FIG. 3, there is no complex multiplier in the decision feedback loop. Therefore, in the present embodiment, the delay of the complex multiplier 18 is not added, so that the conventional one in FIG. High-speed operation is possible compared to the system. Therefore, according to the present embodiment, it can be applied to a communication system having a high transmission rate.

Further, according to this embodiment, the decision feedback equalizer 102, the complex multiplier 18, the carrier wave regenerator 103, the deciders 9 and 10, etc. can all be implemented by digital signal processing. Large-scale integrated circuit (LSI
It is easy to make it possible, and when it is made into an LSI, it can be downsized and no adjustment is required.

[0042]

As described above, according to the present invention,
The decision feedback equalizer is divided into a forward equalizer and a backward equalizer, and a complex multiplier for synchronous detection is arranged between the forward equalizer and the backward equalizer. The delay in the phase-locked loop can be prevented from increasing, and the delay such as the complex multiplier can be prevented from being added in the decision feedback loop. Therefore, a phase-locked loop with fast response can be configured and combined. It is possible to realize a carrier recovery method applicable to a communication method having a high transmission rate without reducing the operation speed of the decision feedback equalizer. Further, according to the present invention, since it is easy to make an LSI, there is a feature that miniaturization and no adjustment can be easily made by making an LSI.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a carrier recovery system according to the present invention.

FIG. 2 is a block diagram of an example of a conventional method.

FIG. 3 is a block diagram of another example of the conventional method.

FIG. 4 is a diagram showing a basic circuit for explaining the operation of the decision feedback equalizer.

[Explanation of symbols]

 1 Input Terminal 2 Local Oscillator 3 Phase Shifter 4, 5 Multiplier 6, 7 A / D Converter 9, 10 Judgmentor 11 Phase Error Detector 13 Digital Voltage Controlled Oscillator (VCO) 18 Complex Multiplier 21 Forward Equalizer 22 Back Equalizer 101 Quadrature Quasi-Synchronous Detector 102 Decision Feedback Equalizer 103 Carrier Regenerator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04B 3/06 C 7741-5K H04L 27/38

Claims (2)

[Claims] 1. An orthogonal quasi-synchronization which receives an input digital modulation signal as an input signal and frequency-converts the input digital modulation signal into a baseband complex modulation signal by a local signal having a frequency substantially equal to the carrier of the input digital modulation signal. A detector, an A / D converter that converts the output complex modulated signal of the quadrature quasi-synchronous detector into a digital signal, and a forward equalization process that performs forward equalization processing on the output digital signal of the A / D converter. , A complex multiplier for performing synchronous detection by multiplying the output digital signal of the forward equalizer with a reproduced carrier wave, and an output synchronous detection signal of the complex multiplier together with a determination signal, which is input to the synchronous detection signal. A rear equalizer for performing equalization processing, and the above-mentioned determination signal is generated and output based on the equalized signal extracted from the rear equalizer, and an error signal is generated and output. Based on the decision signal and the error signal extracted from the decision unit, a reproduction carrier synchronized with the carrier of the digital signal input to the complex multiplier is generated, and the reproduction carrier is transmitted to the complex multiplier. A carrier wave reproducing system having an input carrier wave reproducing device. 2. The forward equalizer is a forward-type transversal filter, and the backward equalizer adds a signal obtained by filtering the determination signal and a synchronous detection signal from the complex multiplier, respectively. 2. The carrier recovery method according to claim 1, wherein the transversal filter is a backward type transversal filter which is output to the judging device after being synthesized by.