JPH0430220B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing information extraction device, and particularly to a timing information extraction device applied to a receiving device including a demodulator that receives and demodulates a data signal such as a facsimile.

In general, such receivers execute a predetermined training sequence prior to receiving a data signal, perform carrier phase control and initial timing settings, and adapt automatic gain control circuits and automatic equalizers to the signal level and line characteristics. and converge. The receiving device should initialize the timing as early as possible in this training sequence, and after that, the system including timing extraction, a phase-locked loop (PLL) for carrier phase control, and an automatic equalizer should quickly and stably converge. is required.

Conventionally, as a timing information extraction method, for example, DLLyon's document “Envelope-Derived
Timing Recovery in QAM and SQAM
Systems” IEEE Trans.Commun.
Paper), COM-25, No. 11, 1327-1331
Page (November 1975) describes a well-known method for extracting the sampling timing that ultimately maximizes the frequency component half the baud frequency _b , that is, the frequency component b/2 at the edge of the band. The method is described. However, since the frequency components at the edge of the band are generally small, this method cannot be used unless the Q of the bandpass filter (BPF) used is sufficiently large.
The extracted timing information contains strong jitter,
It cannot be used satisfactorily. On the other hand, increasing Q reduces the jitter in timing information, but
It takes longer for the system to stabilize. Furthermore, since this method inputs the baseband signal, the amount of calculation in the waveform shaping filter after demodulation is extremely large.

Another example is a method that uses a phase-locked loop (PLL) in a demodulator to directly or indirectly determine an appropriate sampling timing from the tap coefficients of an equalizer, and then feeds it back to the symbol sampler. In this method, the amount of computation of the waveform shaping filter is small, but depending on the initial conditions, the convergence of the system may be extremely poor. For example, if sampling is initially started at the worst timing of a symbol, not only the timing extraction PLL but also the automatic equalizer and carrier phase control PLL will not be able to converge well.

As an example, see G. Schollmeier's document “Carrier
and Timing Recovery in Data Receivers
with Adaptive Equalization”ICC 77
(Chicago) Conference Record 1977, No. 21.4.96
~21.4.99 (1977) states that the coefficient C ₀ of the central tap of a transversal (acyclic) filter as an automatic equalizer is always set to 1 (or its imaginary part
Imag (C ₀ ) is always fixed at 0) or controlled in this way, and then the real part Real (C 1 ) of the coefficient C ₁ of the tap near the postcursor is set to 0 for one tap from the center tap, that is, for _one symbol period. A method for controlling the timing so that In order to control C ₀ to 1 or Imag (C ₀ ) to 0, the phase of the carrier wave may be controlled. In other words, in synchronous detection of the receiver, if the phase of the local oscillator (regenerated carrier wave) is shifted by θ with respect to the received carrier wave, the baseband signal after synchronous detection (i.e., the line signal demodulated to the baseband) is received in a form rotated by θ in the complex plane.
The automatic equalizer performs equalization including this carrier phase error θ. Therefore, each of the tap coefficients of the automatic equalizer is - when θ=0.
The value is rotated by θ. It is well known that the absolute value of the central tap coefficient C ₀ of the automatic equalizer is approximately "1" if the automatic gain control circuit operates normally. That is, C ₀ ≒exp(−jθ).
Therefore, in order to make C ₀ “1” or Imag (C ₀ ) “0”, θ should be brought close to 0, and in this way, the phase of the carrier wave (regenerated on the receiving side) can be adjusted. Just control it.

During the initial training of the modulator/demodulator (MODEM), each tap coefficient of the equalizer is successively modified. C ₀
is fixed to 1, C ₀ in the equalizer
If the optimal value of is not 1 by chance, equalization performance deteriorates. Also, C ₀ becomes 1 (or Imag
In the method of controlling the phase of the carrier wave so that (C ₀ ) becomes 00), by chance during initial training
If Imag (C ₀ ) is not 0, a large error may be introduced into the timing information Real (C ₁ ). Also, until this Imag (C ₀ ) becomes 0,
The system will operate under imperfect conditions and transient responses will tend to be strong and long.

This phenomenon does not pose much of a problem under normal communication conditions, but during the initial training period, timing extraction PLL, carrier phase control PLL
and the stability and speed of convergence of the system containing the equalizer (these are closely related to each other).

The present invention solves these drawbacks of the prior art,
It is an object of the present invention to provide a timing information extraction device that can rapidly and stably converge the adaptive operations of a timing extraction PLL, a carrier phase control PLL, and an equalizer, and requires a short time for initial training.

According to the invention, this objective is to make the adjustment of the equalizer tap coefficient and the carrier phase control PLL independent,
This is achieved by allowing Imag(C ₀ ) to take on values other than zero. That is, the timing information extraction device according to the present invention includes an automatic equalizer including a plurality of taps, and a line signal that is connected to the input of the automatic equalizer and is demodulated to the baseband and is sampled and input to the automatic equalizer. The control circuit includes a sampling circuit and a control circuit for controlling the phase of sampling in the sampling circuit, and the control circuit controls a coefficient C ₀ of a center tap of the automatic equalizer and a coefficient C ₁ of a tap subsequent to the center tap by one symbol period. The optimum sampling point is obtained by advancing or delaying the sampling phase based on the .

Next, embodiments of a timing information extraction device according to the present invention will be described in detail with reference to the accompanying drawings.

The figure shows an embodiment in which the timing information extracting device according to the present invention is applied to a modem/modulator (MODEM) for telephone lines. In this embodiment, the modulation scheme may be a quadrature (two-dimensional) amplitude modulation (including phase modulation) scheme, and the symbol transmission rate is, for example, 1600 baud. Line signal input terminal 1 connected to the telephone line
0, an 8-phase modulated line signal (4800 bits/sec) with a carrier frequency of 1800 Hz is input.

The input line signal 10 is sampled by a sampler 14 with a sampling clock generated by a voltage controlled oscillator (VCO) 12. The frequency s of this sampling clock is 9600 Hz in this embodiment. The signal 16 sampled by the sampler 14 is converted into a digital signal 20 by an analog-to-digital (A/D) converter 18, and then converted to a digital signal 20 by a demodulator 2.
2 is input.

The demodulator 22 digitally demodulates the line signal by multiplying the carrier wave of frequency c (=1800 Hz), and the demodulated baseband signal 24 is supplied to the symbol sampler 30 via the waveform shaping filter 26. Note that in the figure, complex number signals are indicated by double lines. The waveform shaping filter 26 is a low-pass filter that removes unnecessary frequency band components from the output 24 of the demodulator 22 and shapes the waveform. Symbol sampler 30 is VCO1
In this example, a clock (=1600 Hz) obtained by dividing the clock s of 2 to 1/6 by the frequency divider 32 is supplied as a sampling pulse, and the sampling switch samples the output 28 of the filter 26 using this clock. Furthermore, the frequency of this clock
b is set equal to the baud frequency of the line signal.

The output 34 of the symbol sampler 30 is connected to an auto-adaptive equalizer 36. The equalizer 36 is preferably a transversal filter that automatically adapts to compensate for the line characteristics of the received line signal, ie, to have the inverse characteristics of the line connected to the input terminal 10. In this transversal filter, each tap is configured with a plurality of delay circuits (for example, 32) connected in cascade, and a delayed signal for each tap is multiplied by a tap coefficient, that is, a gain, by a multiplier and an accumulator. This is a normal combination using an adder. The combined output 38 is input to a carrier phase control circuit 40, and each tap coefficient is modified in response to an error signal output 42 of the carrier phase control circuit 40.

The output 44 of the carrier phase control circuit 40 is input to a quantizer 46, and the quantizer 46 is a circuit that determines symbols included in the line signal from the input 44 signal and quantizes the symbols. Input 44 of quantizer 46
The difference between the output 48 and the output 48 is fed back to the carrier phase control circuit 40 as an error signal 50, and is used for convergence of the system.

By the way, in this embodiment, input terminal 1 is connected from the line.
The signal received at zero is, for example, a scrambled, differentially encoded and quadrature amplitude modulated signal at the transmitting end. That is, a data signal, for example a facsimile signal, is averaged and randomized so that the symbol transmission pattern is uniform, forming a scrambled bit stream, which is then used to remove carrier phase ambiguities. The phase components of the bit stream are differentially encoded. Next, this is passed through a low-pass filter to shape the frequency spectrum of the symbol, and this baseband signal modulates a carrier wave of frequency c, and frequency components in unnecessary bands are removed by a bandpass filter or low-pass filter. and sent to the line.

Since the received signal at the input terminal 10 is differentially encoded and scrambled in this way,
In the device shown, the output 48 of the quantizer 46 is provided with a decoder 52 and a descrambler 54. Decoder 52 forms a bit stream from the symbols contained in quantized output 48. Its output 56
is connected to a descrambler 54 which has an inverse function to the scrambler at the transmitting end and restores the data signal from the bit stream on signal line 56 and outputs it to output terminal 58.

According to the invention, a voltage controlled oscillator (VCO) 1
The oscillation frequency s of 2 is controlled according to timing _{information te} extracted from the automatic adaptive equalizer 36 by the arithmetic unit 60.

This timing information _te is formed in the computing unit 60 as follows. The tap coefficients C ₀ and C ₁ are inputted to the arithmetic unit 60 from the automatic adaptive equalizer 36 . Tap coefficient C ₀ is the tap coefficient at the center tap of equalizer 36. Further, the tap coefficient C ₁ is a tap coefficient of a tap located one symbol period post-cursor from the center tap, that is, a later tap (that is, delayed by one symbol). These tap coefficients, or tap gains, are
It is expressed as a complex number containing in-phase and orthogonal components. The arithmetic unit 60 generates the conjugate complex number C ₀ ^* of the central tap coefficient C 0 by the arithmetic unit 62 , and this C ₀ ^* is multiplied by _{C 1 from} the equalizer 36 in the multiplier 64 .
The multiplication result C ₁ C ₀ ^* is converted to the real part Real in the calculation unit 66.
(C ₁ C ₀ ^* ) is extracted and input to the loop filter 70 as timing information _te .

By the way, as described in the above-mentioned Schollmeier literature, the central tap coefficient C ₀ is fixed to 1,
It is known to adjust the sampling timing, that is, the phase, so that Real (C ₀ ) becomes 0. In this case, if Real (C ₁ ) is 0, a sampling point close to the optimum timing can be obtained. When Real (C ₁ ) is positive, the sampling timing is advanced; when Real (C 1 ) is negative, the sampling timing is delayed. Also, near the optimal sampling time, the sampling time τ
It is known that Real (C ₁ (τ)), which is a function of , is monotone with respect to τ.

In the method described in Schollmeier's literature, C ₀ is set to 1 by carrier phase control in order to obtain information for carrier phase control from the center tap of the automatic equalizer. However, in the illustrated embodiment of the invention, carrier phase control circuit 40 does not receive carrier phase control information from the central tap and is configured independently of automatic equalizer 36. Therefore, the automatic adaptive equalizer 36 does not need to be controlled so that the center tap coefficient C ₀ is "1";
C ₀ does not become "1".

In the present invention, the value of the central tap coefficient C ₀ is “1”.
Instead of controlling the automatic adaptive equalizer ₃₆ itself so that Find the real part Real(C ₁ /C ₀ ) of C ₁ /C ₀ based on the coefficient C ₁ of the tap that is one symbol period after this) and the coefficient C 1 of the tap that is one symbol period after this.
Alternatively, multiply the conjugate complex number C ₀ ^* of the coefficient C ₀ by the coefficient C ₁ to obtain its real part Real (C ₁ C ₀ ^* ), and then calculate the real part (C ₁ /C ₀ ) or the real part real (C ₁ By controlling the sampling phase so that C ₀ ^* ) becomes “0”,
It is intended to perform control equivalent to control in which the center tap coefficient C ₀ is set to "1".

To describe the principle of the present invention in more detail, as described above, when there is a carrier phase error θ, each tap coefficient of the automatic adaptive equalizer 36 is
It is the value obtained by multiplying the value when = 0 by exp(jθ). Therefore, when θ is not “0” (general), multiplying each tap coefficient by exp(jθ)
This is equivalent to controlling the value of C ₀ to "1". Here, C ₀ ≒ exp(−jθ), so C ₁ has exp(jθ)
To get the product multiplied by C 1, divide C ₁ by C ₀ or C ₀
Multiply C ₁ by the conjugate C ₀ ^* of . In the former case,
This corresponds to controlling the sampling phase so that Real(C ₁ /C ₀ ) becomes “0”. In addition, the latter is
It can be obtained by transforming the expression Real(C ₁ /C ₀ ) as follows.

Real(C ₁ /C ₀ )=Real(C ₁ C ₀ ^* /C ₀ C ₀ ^* ) = Real(C ₁ C ₀ ^* )/｜C ₀ | ² (1) Here, |C ₀ |≒1 Real(C ₁ /C ₀ )≒Real(C ₁ C ₀ ^* ) (2) Therefore, the value of Real(C ₁ C ₀ ^* ) can be used as timing information.
It can be used as t _e .

For simplicity, Real (C ₀ ) = CI ₀ , Real (C ₁ ) = CI ₁ | Imag (C ₀ ) = CQ ₀ , Imag (C ₁ ) = CQ _{1 (} 3). C ₀ ^* ) is calculated as follows: Real(C ₁ C ₀ ^* ) = Real [(CI ₁ + jCQ ₁ ) (CI ₀ −
jCQ ₀ )〕 = Real〔(CI ₁・CI ₀ +CQ ₁・
CQ ₀ ) +j (CQ ₁・CQ ₀ −CI ₁・CQ ₀ )] = CI ₁・CI ₀ +CQ ₁・CQ ₀ (4). The arithmetic unit 60 performs this calculation and outputs the result of only the real part to the loop filter 70 as timing information _te . Therefore, in order to obtain the optimal sampling timing, if Real (C ₁ C ₀ ^* ) is positive, the sampling phase should be advanced, and if Real (C 1 C 0 *) is negative, it should be delayed. Although FIG. 1 shows a case where Real(C ₁ C ₀ ^* ) is calculated in the computing unit 60, the configuration of the computing unit 60 may be changed to Real(C ₁ /C ₀ ).
It can also be changed to ask for Also in this case, the value of Real(C ₁ /C ₀ ), which is equivalent to Real(C ₁ C ₀ ^* ), can be output as the timing information _te .

The timing information t _e is input as a control voltage signal 72 to the voltage controlled oscillator (VCO) 12 via the loop filter 70 . Therefore, automatic equalizer 3
6, arithmetic unit 60, loop filter 70, and
The VCO 12 forms a feedback loop for the timing extraction PLL. VCO12 is control voltage signal 7
This is an oscillator whose oscillation frequency s, that is, its oscillation period, can be varied according to 2. This requires relatively high stability, but since the variable range of the oscillation period is sufficient within a narrow range of, for example, ±0.1%, it can be configured with a simple digital circuit. For example, if you divide the fundamental frequency of 9.6MHz by 1/1000, you will get 9600Hz, but by dividing it by 1/999 or 1/1001, the oscillation period will be 0.1% each compared to 9600Hz. Become shorter or longer.

The loop filter 70 forms a control voltage signal 72 representing a change _Δt in the oscillation period of the VCO 12 from the timing information _te input from the arithmetic unit 60. Therefore, the VCO 12 shortens its oscillation period by 0.1% if _Δt is positive, lengthens it by 0.1% if it is negative, and outputs an accurate 9600 Hz clock s if Δt is 0. In this way, by making Δ _t positive or negative, the sampling time point, that is, the phase, in the symbol sampler 30 is adjusted, and when the sampling is synchronized, Δ _t is normally 0.
Note that each numerical value described here is only an example for explanation.

The timing information extraction device according to the present invention not only can obtain practically optimal sampling timing, but also has a very small amount of calculation for timing information extraction, and has a timing extraction PLL.
Adaptive operations such as carrier phase control PLL and equalizer can be converged stably and quickly. Therefore, the time required for initial training can be shortened. Note that the error from the optimum value at the sampling point can be absorbed and equalized by an equalizer.

[Brief explanation of drawings]

The figure is a block diagram showing an embodiment in which the timing information extraction device according to the present invention is applied to a telephone line MODEM. Explanation of symbols of main parts 12... Voltage controlled oscillator, 30... Symbol sampler, 36... Automatic adaptive equalizer, 60... Arithmetic unit, 70... Loop filter.

Claims (1)

[Claims] 1. An automatic equalizer including a plurality of taps, and a sampling device connected to the input of the automatic equalizer, which samples a line signal demodulated to the base band and inputs the sample to the automatic equalizer. circuit, and a control circuit for controlling the phase of sampling in the sampling circuit, wherein the coefficients of the plurality of taps are composed of complex numbers, and the control circuit is configured to control the coefficient C ₀ of the center tap of the automatic equalizer, and The sampling phase is controlled based on the coefficient _C1 of the tap located after the center tap by one symbol period, and the coefficient
Multiply the conjugate complex number C ₀ ^* of C ₀ by the coefficient C ₁ to calculate its real part Real (C ₁ C ₀ ^* ), and advance or slow the sampling phase based on the value of the real part. A timing information extraction device characterized in that it is adapted to obtain an optimal sampling point. 2. an automatic equalizer including a plurality of taps; a sampling circuit connected to the input of the automatic equalizer that samples the line signal demodulated to the baseband and inputs it to the automatic equalizer; and the sampling circuit. a control circuit for controlling the sampling phase of the taps, the coefficients of the plurality of taps are composed of complex numbers, and the control circuit controls the coefficient C ₀ of the center tap of the automatic equalizer, and It is configured to control the sampling phase based on the coefficient C ₁ of the subsequent tap for a period of time, and the sampling phase is controlled based on the coefficient C ₁ of the subsequent tap.
The optimum sampling point is obtained by calculating C ₀ , calculating its real part Real (C ₁ /C ₀ ), and advancing or slowing down the sampling phase based on the value of the real part. A timing information extraction device characterized in that: