JP2002198943A - Clock regenerating unit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock regenerating unit and its method which are more excellent in noise-proof characteristic than conventional ones, enable to synchronously pull in at high speed, and also can realize to save power at intermittent receiving. SOLUTION: This unit is a clock regenerating unit used at transmitting burst signals, and is provided with a circuit situation presumption part which presumes a circuit situation based on a threshold value decided beforehand, an up-and-down counter which performs count operation receiving the count value from the circuit situation presumption part, a variable frequency demultiplier which demultiplies based on the output of the up-and-down counter and outputs a regenerated clock, and a phase comparator which decides the count direction of the up-and-down counter comparing the signal-phase detected at the circuit situation presumption part and the output phase of the variable frequency demultiplier. In the unit of this invention, the threshold value doesn't vary if the circuit situation varies; the count value at the good circuit situation is larger than the count value at the bad circuit situation; and the counter performs larger count at fewer frequency than conventional method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to burst signal transmission, for example, spread spectrum / time division multiplexing (SS / T).
The present invention relates to a clock recovery device and method used in the DD) system.

[0002]

2. Description of the Related Art As a conventional technique, Japanese Patent Laid-Open Publication No.
No. 4 discloses a technique disclosed in Japanese Patent Application Laid-open No. 4 (1994). FIG. 5 shows a block diagram of a conventional clock recovery device.

In FIG. 5, a binary quantizing phase comparator 7
Then, the delay and advance of the phase of the input signal with respect to the phase of the reproduced clock are determined, and based on the result, "-1" (delay) and "1" (lead) are added to the up / down counter.

The up / down counter 8 has "-1" and "1".
Is counted, and when the counter value reaches the threshold value ± N, the advance / delay is notified to the pulse removal adder 10. The pulse elimination adder 10 applies ± M pulses to the output of the fixed frequency oscillator 11 according to the lead / lag. The output is frequency-divided by a frequency divider 9 and output as a reproduction clock.
At this time, the threshold value ± N of the up / down counter 8 and ± M representing a single correction amount with respect to the phase in the pulse elimination adder 10 are set by the control circuit 13, and the optimum value is obtained from the output of the reception level detector 15. M and N are determined.

That is, the smaller the value of N, the more sensitive to the phase difference, and the larger the value of M, the larger the amount of correction for the phase difference and the faster the synchronization operation. Conversely, if N is large and M is small, the error of the phase comparator 7 due to noise has little effect on the pulse rejection adder 10 and the synchronization accuracy is improved, so that it is suitable for highly stable and highly accurate clock reproduction. .

At the time of synchronization pull-in, the above constants are set for high-speed lock-in, and clock synchronization is performed at high speed with a short preamble. When the reception level detected by the reception level detector 15 exceeds a preset value, the constant is switched to a constant for high stability and high accuracy.

As a result, the reproduced clock used for demodulating the data portion is highly stable and highly accurate, so that demodulation with few errors can be performed.

As described above, high-speed burst synchronization can be obtained, and a highly stable clock can be used for demodulation of data. Therefore, high-rate and highly reliable burst data transmission can be realized.

[0009]

In wireless communication, bit synchronization between transmission and reception is required to demodulate received data. In the case of the TDD system, the slave side performs only reception continuously until the initial synchronization is established. Therefore, there is a time when the master side does not receive the frame data to be transmitted, and in that case, only the noise is received. are doing. Therefore, the initial synchronization pull-in time is a trade-off with the noise immunity characteristic. In the TDD system, the noise immunity characteristic greatly affects the initial synchronization pull-in.

An object of the present invention is to provide a clock reproducing apparatus and a clock reproducing method which are excellent in noise resistance.

[0011]

A clock recovery apparatus according to the present invention is a clock recovery apparatus used in burst signal transmission, wherein a line condition estimating unit for estimating a line condition based on a predetermined threshold value; An up / down counter that performs a count operation in response to a count value from a line status estimating unit; a variable frequency divider that performs frequency division based on the output of the up / down counter and outputs a recovered clock; A phase comparator that determines the count direction of the up / down counter by comparing the phase of the signal and the output phase of the variable frequency divider. The present invention is characterized in that the count value when the threshold is not changed and the line condition is good is made larger than the count value in other cases.

Preferably, the line condition estimating unit includes a peak detector for detecting a peak signal in a received signal, and a comparing unit for comparing the peak signal with the threshold, wherein the comparing unit includes the peak signal. Is larger than the threshold value, the count value is increased.

Preferably, the count value when the line condition is good is equal to or more than a predetermined value, and the count value in other cases is 1. Preferably, the threshold value and the count value are matched so that the phase is shifted by one symbol.

A clock recovery method according to the present invention is a clock recovery method used in burst signal transmission, wherein a step of estimating a line state based on a predetermined threshold value and a step of counting a count value when the line state is good are performed separately. Setting a value larger than the count value in the case of, determining the count direction by comparing the phase of the received signal with the output phase of the variable frequency divider; and performing a count operation based on the count value and the count direction. And a step of performing frequency division based on the count result and outputting a reproduced clock, wherein the threshold value does not change even if the line condition changes.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An apparatus / method according to an embodiment of the present invention will be described with reference to the drawings. FIG.
It is a block diagram of a device concerning an embodiment of the invention.
In the figure, reference numeral 1 denotes a digital matched filter for extracting a desired signal from received chip data, reference numeral 2 denotes a peak detecting unit for detecting a peak in an output signal of the digital matched filter 1, and reference numeral 3 denotes a peak detecting unit 2. A level comparator that compares the peak value detected by the control unit 7 with a predetermined threshold value A and sets a count value based on the comparison result. Reference numeral 4 denotes a phase of the peak detected by the peak detection unit 2 and a variable component. A phase comparator for comparing the output phase of the frequency divider 6 to determine the counting direction of the up / down counter 5;
Is a variable frequency divider that divides the output of the up / down counter 5 to generate a reproduced clock. Reference numeral 7 supplies a threshold A to the level comparator 3 and the up / down counter 5 and the variable Reference numeral 8 denotes a control unit that controls the frequency divider 6 and a data determination unit 8 that receives a reproduction clock from the variable frequency divider 6 and reproduces data in the output signal of the digital matched filter 1 based on the reproduction clock.

FIG. 2 is a flowchart of a processing method according to the embodiment of the present invention. An apparatus / method according to an embodiment of the present invention will be described with reference to FIG.

First, peak detection is performed on the output of the digital matched filter 1 (S1). Bad line condition (S
/ N is low), the digital matched filter 1
The correlation peak value output by (DMF) is a relatively small value. On the other hand, when the line condition is good (the S / N is high), the value becomes a large value near the maximum value. Therefore, the line condition can be estimated from the absolute value of the peak of the DMF output signal detected by the peak detection unit 2.

In the level comparator 3, a comparison is made with a threshold value A preset by the control section 7 (S2). When the peak level is larger than the threshold A, the line condition is estimated to be good. In this case, the process proceeds to step S4. When the peak level is smaller than the threshold A, the line condition is estimated to be bad. In this case, the process proceeds to step S3.

When the line condition is estimated to be good, the count value of the up / down counter 5 is increased to perform high-speed synchronization pull-in (S4).

On the other hand, when it is estimated that the line condition is bad,
The count value is set to 1 (S3). In this case, “−1” or “+1” is added by the up / down counter 5.

As described above, by switching the count value (instead of the threshold value A) according to the line condition, it is possible to realize a high-speed synchronization pull-in which is excellent in noise resistance. Here, the threshold value A cannot be switched. It should be noted that in the prior art, when the count value is switched, the threshold value is always switched.

In order to determine the sign (+,-) of the value counted by the up / down counter 5, the phase comparator 4 performs a phase comparison (S5). If the phase of the peak detected by the peak detector 2 is ahead of the phase of the reproduced clock ("advance" in S5), the count value is decremented (S6). On the other hand, when it is late ("delay" in S5), the count value is added (S7).

When the count value of the up / down counter 5 reaches the threshold value M ("if the value has reached M" in S8), the frequency is divided by one variable pulse in the variable frequency divider (S10). On the other hand, when it reaches -M ("when it has reached -M" in S8), one pulse is added and the frequency is divided (S9).

With the above processing, high-speed synchronization pull-in can be realized with excellent noise resistance.

FIG. 3 shows an apparatus according to an embodiment of the present invention.
The initial synchronization characteristics by the simulation of the method and the conventional method are shown. FIG. 3A shows a simulation result when BER = 1 × 10 ⁻² , and FIG. 3B shows a BER = 1 × 10 ⁻² .
The simulation result in the case of ^-3 is shown. Respectively,
The solid line shows the case of the apparatus / method according to the embodiment of the present invention, and the dotted line shows the case of the related art.

According to FIG. 3A, BER = 1 × 10
^{In the} case of 90% synchronization establishment at ^-2 , 5 to 6
On the other hand, in the method according to the embodiment of the present invention, three frames are established. Therefore, in this frame configuration, if BER = 1 × 10 ⁻² , 90
% Synchronization establishment time is improved by about 50%. According to FIG. 3B, similarly, when BER = 1 × 10 ⁻³ , 90%
It can be seen that the synchronization establishment time is improved by about 30%.

According to this simulation result, as a method for operating sensitively to the phase difference, the threshold value of the up / down counter is set to a fixed value, It can be seen that increasing the number of counts of the down counter improves noise resistance.

Referring to the graph shown in FIG. 4, the conventional method and the method according to the embodiment of the present invention will be compared for the up / down counter operation. FIG. 4A shows a case of an apparatus / method according to an embodiment of the present invention, and FIG. 4B shows a conventional method. 4A and 4B, from time TA to T
The period up to B is when data is not received or when the S / N is low. The period after time TB is when data is being received and when S / N is high,
The detection peak level becomes larger than the threshold value A.

In the conventional method shown in FIG. 4B, when the detected peak level becomes larger than the threshold value A, the threshold value is lowered to frequently count "+1" or "-1". On the other hand, in the apparatus / method according to the embodiment of the present invention in FIG. 4A, the threshold value is left as it is, but the count value is set to be large (= K) instead. That is, in the conventional method, the small count is frequently performed, but according to the embodiment of the present invention, the large count is performed less frequently than in the conventional method.

When data is not received, and when S / N
Is low, the probability of detecting a high-level peak at a phase different from the original level due to noise increases. Also,
In such a situation, the count value of the up / down counter fluctuates randomly near 0, so if the count is opposite to the desired phase, the threshold value of the counter is reduced to change the phase in the wrong direction. shift. Therefore, by using the method of increasing the count value, the noise resistance characteristic is improved, and a high-speed synchronization pull-in characteristic can be realized.

The method of determining a threshold value for estimating the line quality is as follows. The setting made in the simulation is such that when the BER is equal to or higher than the square point, the channel quality is determined to be good and K is increased. In this case, DMF
It is desirable to perform the high-speed tracking operation when the error is equal to or less than X chip with respect to the maximum value Y of the output (when the chip data matches at all taps). Therefore, the threshold value is set to YX = 14.

The method of determining the count number of the up / down counter is as follows. When the value set as described above is large, the reliability of the determination of the channel quality is improved, so that the phase is basically shifted by one symbol. Therefore, K = M is set in the simulation.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say, this is done.

In this specification, means does not necessarily mean physical means, but also includes a case where the function of each means is realized by software.
Further, the function of one unit may be realized by two or more physical units, or the function of two or more units may be realized by one physical unit.

[0035]

As described above, according to the present invention, a clock recovery apparatus which is more excellent in noise resistance than the conventional one, enables high-speed synchronization pull-in, and can realize power saving at the time of intermittent reception. And a method can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart of a method according to an embodiment of the invention.

FIG. 3 is a graph comparing the performance of synchronization establishment by the apparatus / method according to the embodiment of the present invention and the performance of conventional synchronization establishment.

FIG. 4 (a) shows an apparatus /
FIG. 4B is an operation explanatory diagram of the method, and FIG. 4B is an operation explanatory diagram of the conventional method.

FIG. 5 is a block diagram of a conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Digital matched filter 2 Peak detection part 3 Level comparator 4 Phase comparator 5 Up / down counter 6 Variable frequency divider 7 Control part 8 Data judgment part

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kazuhiko Seki 2-7-17 Hatchobori, Chuo-ku, Tokyo Uniden Corporation F-term (reference) 5J106 AA05 BB02 CC21 CC48 DD19 DD22 DD23 EE01 GG13 GG14 HH10 KK03 KK27 KK40 5K022 EE02 EE31 EE36 5K028 AA04 KK01 KK03 NN32 NN44 PP04 PP15 5K047 AA02 AA13 AA15 BB01 CC01 GG11 GG16 GG34 GG37 MM12 MM48 MM55 MM58 MM63

Claims (5)

[Claims] 1. A clock recovery device used in burst signal transmission, comprising: a line condition estimating unit for estimating a line condition based on a predetermined threshold; and a count operation receiving a count value from the line condition estimating unit. An up / down counter, a frequency divider that divides the frequency based on the output of the up / down counter, and outputs a recovered clock, a phase of a signal detected by the line status estimating unit, and an output of the variable frequency divider. A phase comparator for comparing the phase to determine the counting direction of the up / down counter, wherein the line condition estimating unit does not change the threshold even if the line condition changes, and when the line condition is good. A clock reproducing apparatus, wherein the count value is made larger than the count value in other cases. 2. The line condition estimating unit includes a peak detector that detects a peak signal in a received signal, and a comparing unit that compares the peak signal with the threshold value. 2. The clock reproducing apparatus according to claim 1, wherein the count value is increased when the count value is larger than the threshold value. 3. The clock recovery apparatus according to claim 1, wherein the count value when the line condition is good is equal to or more than a predetermined value, and the count value is 1 in other cases. 4. The clock reproducing apparatus according to claim 1, wherein the threshold value and the count value are matched so that the phase is shifted by one symbol. 5. A clock recovery method used in burst signal transmission, comprising: estimating a line condition based on a predetermined threshold value; and counting a count value when the line condition is good than a count value in other cases. Setting a larger value; determining the count direction by comparing the phase of the received signal with the output phase of the variable frequency divider; performing a count operation based on the count value and the count direction; Performing a frequency division on the basis of a frequency, and outputting a reproduced clock, wherein the threshold value does not change even if the line condition changes.