JP4309295B2 - Synchronous detector - Google Patents

Description

  The present invention relates to a synchronous detection apparatus for receiving a burst wave as typified by a TDMA (Time Division Multiple Access) system in digital wireless communication.

  As a detection method for demodulating a modulated signal in digital wireless communication, a delay detection method and a synchronous detection method are known, but in general, the latter can improve the quality of demodulation and hence the communication quality compared to the former. However, in mobile communication using the TDMA system, the delay detection system is often used for the following reasons.

  In other words, when the received signal is composed of burst waves as in the TDMA system, there is a non-signal time zone in which there is no data to be extracted in the received signal. , Phase inversion occurs. If you try to detect this using the synchronous detection method, the frequency acquisition and phase synchronization processing of the recovered carrier and recovered clock used for detection at the timing when the received signal is input from the no-signal time zone will not be in time, Cannot be accurately reproduced, increasing the error rate of the received data and degrading the reception characteristics.

  Therefore, when receiving a burst wave using synchronous detection, it has been a problem to increase the frequency of the recovered carrier wave and the recovered clock and the phase synchronization process. Conventionally, as a technique for solving this problem, the internal states of the carrier recovery circuit and the clock recovery circuit are recorded in a storage circuit, and the carrier recovery circuit and the clock recovery circuit refer to the frequency at the time of the next burst wave reception. The amount of error between the received signal to be corrected and the reproduction signal to be corrected in the phase synchronization processing is reduced, the time required for frequency acquisition and phase synchronization is shortened, and the speed is increased (for example, Patent Document 1). reference). In addition, in the case of erroneous detection of burst wave, refer to the reproduction circuit internal state information during normal operation that has been saved in advance in order to avoid erroneous information being recorded due to malfunction of synchronization processing of each reproduction signal. This is done by resetting.

JP2001-186207 (first page to fourth page, FIG. 1)

  However, in the above-described prior art, the internal state information of the carrier recovery circuit and the clock recovery circuit to be recorded / saved in the storage circuit needs to operate in a normal and stable state. There is a problem with choosing the timing to extract the state of.

  That is, noise is usually mixed in the received wave in actual communication. At this time, depending on the amount of noise, the frequency and phase may be shifted between the received signal and the reproduced signal. Therefore, the carrier wave and clock output from the reproducing circuit are corrected appropriately. However, depending on the set value of the loop band, the feedback sensitivity may be increased. It is too high and it always reacts to noise contamination, or because of low sensitivity, it takes time to pull in frequency and phase synchronization, and it takes time to return to a stable state. The state that is doing occurs.

  If such a state is recorded in the storage circuit, the difference between the reception signal and the reproduction signal may occur when referring to the recording information at the time of reception of the next burst wave, In some cases, the time required for processing the frequency acquisition and phase synchronization of the reproduction signal becomes long. As a result, it is not possible to obtain the benefits of pulling in the frequency of the original reproduction signal and speeding up the phase synchronization processing.

  Accordingly, an object of the present invention is to improve the stability of a reproduction signal synchronization state even when noise is mixed, to improve the accuracy of information to be recorded, and to reproduce the frequency of the reproduction signal and perform high-speed phase synchronization processing. An object of the present invention is to provide a synchronous detection circuit that can be realized.

  According to the first aspect of the present invention, in the synchronous detection apparatus for burst waves in digital wireless communication, the internal state information of the carrier recovery circuit for recovering the carrier wave and the clock recovery circuit for recovery of the reception clock is set for each section set arbitrarily. Means for performing cumulative addition at sufficiently short intervals, means for calculating an average value for each section after cumulative addition, means for comparing information on this average value with a preset reference value, and determining synchronization status And a means for correcting a loop band in the carrier recovery circuit and the clock recovery circuit as appropriate based on the determination result.

  According to a second aspect of the present invention, there is provided a burst wave synchronous detection device for digital radio communication, a monitoring / control circuit (1 in FIG. 1) for monitoring a received wave and controlling operations of each circuit in the subsequent stage; A carrier recovery circuit (2 in FIG. 1) that reproduces the carrier under the control of the control circuit, and a clock recovery circuit (3 in FIG. 1) that recovers the received clock under the control of the monitoring / control circuit And the carrier wave recovery circuit, the recovered carrier wave output from the clock recovery circuit, the received wave is detected using the recovered clock, the extracted data is output to the outside, and the detected received wave, the recovered carrier wave, the recovered clock, Detection circuit (4 in FIG. 1) that feeds back difference (error) information to the monitoring / control circuit, and the inside of the carrier recovery circuit and the clock recovery circuit under the control of the monitoring / control circuit A cumulative addition circuit (5 in FIG. 1) that sequentially adds state information for a preset number of times, and outputs the value of the addition result up to that time, and inputs from the cumulative addition circuit An average value calculation circuit (6 in FIG. 1) that calculates and outputs an average value in the addition section based on a preset number of additions value from the cumulative addition result, and an average input from the average value calculation circuit The value data is compared with the internal state information of the carrier recovery circuit and the clock recovery circuit in the case where the synchronization processing between each reproduction signal and the reception signal set in advance is stable, and from each difference, A synchronization determination circuit (7 in FIG. 1) for notifying the monitoring / control circuit of the switching of the loop band, and the inside of the carrier wave recovery circuit and the clock recovery circuit in the last section of the currently received burst wave And a storage circuit (8 in FIG. 1) for recording the average value of the state information, and the carrier recovery circuit and the clock recovery circuit reproduce the average value recorded in the storage circuit when the next burst wave is received. Is a synchronous detector characterized by being referred to as internal state information.

  According to a third aspect of the present invention, there is provided a synchronous detection method for burst waves in digital wireless communication, a procedure for monitoring received waves and controlling their operation, a carrier recovery circuit receiving a control, a carrier recovery circuit receiving a control, and a clock recovery circuit receiving a reception A procedure for regenerating the clock, a procedure for detecting the received wave using the recovered carrier and clock and outputting the extracted data to the outside, and a difference between the detected received wave, the recovered carrier and the recovered clock ( Error) The procedure for feeding back information for monitoring and control, and the internal state information of the carrier recovery circuit and the clock recovery circuit are sequentially added for a preset number of times under the control, and the addition for the set number of times is completed. Each time, the value of the addition result up to that time is output, and the result of the cumulative addition input from the cumulative addition circuit is based on the preset number of additions. An average value calculation circuit for calculating and outputting an average value in a calculation interval, a carrier wave recovery circuit and a clock recovery circuit when the average value data, and the synchronization processing of each preset reproduction signal and reception signal are stable The procedure for comparing the internal state information of the receiver and notifying the difference of the loop band switching in each reproduction circuit for monitoring and control, and the carrier recovery circuit and clock recovery in the last section of the currently received burst wave A procedure for recording an average value of the internal state information of the circuit, and the carrier wave recovery circuit and the clock recovery circuit refer to the recorded average value as internal state information for reproduction when the next burst wave is received. This is a synchronous detection method characterized by the above.

  By adopting the above configuration, the synchronization state of the regenerative circuit at the time of burst wave reception is a sequential loop band so that even if noise is mixed in the reception wave, it quickly transitions to a stable state. Therefore, a stable state can be maintained, and the internal state information of each reproduction circuit to be recorded can remain highly accurate.

  As a result, it is possible to minimize giving wrong information (or to increase the original difference) at the time of receiving the next burst wave. It will be possible to benefit.

  The synchronous detection device according to the present invention provides internal state information of the carrier recovery circuit and the clock recovery circuit to be referred to when receiving the next burst wave in the case of synchronous detection of the burst wave, and the received burst wave in several sections in time series. It is characterized in that it is divided and recorded, and the loop band of the reproduction circuit is corrected in accordance with the synchronization state as appropriate in each section.

  More specifically, the synchronous detection device of the present invention records the internal state information of the carrier recovery circuit and the clock recovery circuit to be referred to when receiving the next burst wave in the case of synchronous detection of the burst wave. A means for performing cumulative addition for each section in which the internal state information of the clock recovery circuit is arbitrarily set, a means for calculating an average value after cumulative addition, and comparing the average value information with a preset reference value, Means for determining the synchronization state and means for appropriately correcting the loop band in the reproduction circuit based on the determination result. With such a configuration, even when noise is mixed in the received wave, the stability of the synchronization state of each reproduction signal is improved, and the information that is referred to / recorded at the time of frequency acquisition and phase synchronization processing in the reproduction circuit is improved. Accuracy can be improved.

  FIG. 1 shows an embodiment of the synchronous detection apparatus of the present invention. In FIG. 1, reference numeral 1 is a monitoring / control circuit for monitoring a received wave input from an input terminal A and controlling the operation of each subsequent circuit. A carrier recovery circuit 3 for performing reproduction, a clock regeneration circuit for regenerating the received clock under the control of the monitoring / control circuit 1, and 4 a regenerated carrier wave and a reproduction clock output from the carrier recovery circuit 2 and the clock recovery circuit 3. This is a detection circuit that detects the received wave using and outputs the extracted data from the output terminal B to the outside.

  5. The control unit 5 receives the control from the monitoring / control circuit 1 and sequentially adds the internal state information of the carrier recovery circuit 2 and the clock recovery circuit 3 for a preset number of times (an arbitrarily divided section length). A cumulative addition circuit that outputs the value of the addition result up to that time to the subsequent circuit every time the addition of the minute is completed, and 6 is a preset addition number value (from the cumulative addition result input from the cumulative addition circuit 5 ( This is an average value calculation circuit that calculates an average value in the addition section based on the same as the number of times of cumulative addition in the cumulative addition circuit 5) and outputs the average value to the subsequent circuit.

  7 shows the inside of the carrier recovery circuit 2 and the clock recovery circuit 3 when the synchronization processing of the average value data input from the average value calculation circuit 6 and each preset reproduction signal and reception signal is stable. A synchronization determination circuit for comparing the status information and notifying the monitoring / control circuit 1 of the switching of the loop band in each reproduction circuit based on the difference; 8 is a carrier wave reproduction circuit 2 in the last section of the currently received burst wave; This is a storage circuit that records the average value of the internal state information of the clock recovery circuit 3.

  In the present invention, as shown in FIG. 2, the number of intervals in which the time during which the burst wave is present in the received wave, that is, the time during which the frequency of the recovered carrier and the recovered clock is operated and the phase synchronization process is operating, is arbitrarily set. The internal state information of the carrier recovery circuit 2 and the clock recovery circuit 3 is sequentially extracted at intervals sufficiently shorter than the time of the sections in each of the sections 1 to N. The cumulative addition circuit 5 performs cumulative addition 1 to N of the internal state information for each of the sections 1 to N, the average value calculation circuit 6 calculates the average values 1 to N for the cumulative additions 1 to N, and the synchronization determination circuit 7 Each of the average values 1 to N is compared with information on the internal state in the stable state of the reproduction circuits 2 and 3 set in advance.

  The synchronization determination circuit 7 controls the frequency pull-in and switching / holding of the phase synchronization loop band in the reproduction circuits 2 and 3 according to the degree of the difference at this time, and sets the loop band in the synchronization processing of each reproduction signal in the next section Reset every 1 to N. After the resetting, the above processing is performed for the period in which the currently received burst wave exists, and when the end of the burst wave is detected, the average value in the last section N is obtained as the reproduction circuits 2 and 3 when the next burst wave is received. Is recorded in the storage circuit 8 as a reference value. The reproduction circuits 2 and 3 read the average value in the last section N recorded in the storage circuit 8 at the time of reception of the next burst wave as the reproduction circuit internal state information and reflect it in the reproduction circuits 2 and 3 to thereby reproduce the reproduction circuit. It restores the state.

  Thus, during the time when the synchronization processing is performed, the loop band of the regenerated carrier wave and the regenerated clock is appropriately synchronized so as to synchronize quickly according to the difference from the received wave at that time, or to maintain a more stable state. Because it is corrected, the fluctuation of the synchronization process is reduced to the minimum, and it is possible to provide highly accurate information when the next burst wave is received, so that the frequency pull-in of each reproduction signal and the speed of the phase synchronization process are realized. Is possible.

  Next, the operation of the synchronous detection circuit shown in FIG. 1 will be described with reference to the flowchart of the process shown in FIG.

  The monitoring / control circuit 1 monitors the received wave at the input terminal A. When a burst wave (received signal) in the received wave as shown in FIG. 2 is detected (step S1 in FIG. 3), the carrier wave recovery at the subsequent stage is performed. An operation mode switching signal is output to the circuit 2 and the clock recovery circuit 3, and the circuit operation mode is notified to change the operation mode from maintaining the state to the normal processing (synchronization processing) (step S2). Further, the cumulative addition circuit 5 is notified of initialization (zero clear) by an initialization signal (step S3).

  The carrier recovery circuit 2 and the clock recovery circuit 3 read the internal state information of each reproduction circuit recorded at the previous burst wave recorded in the storage circuit 8 and reflect it in its own circuit in response to the operation mode switching signal. Thus, the reproduction circuit state is restored (step S4). Then, the state of processing up to that point is shifted to normal processing, and the carrier recovery circuit 2 outputs the recovered carrier and the clock recovery circuit 3 outputs the recovered clock to the detection circuit 4 (step S5). At this output timing, the carrier recovery circuit 2 and the clock recovery circuit 3 output the internal state information to the cumulative addition circuit 5 (step S5).

  The cumulative addition circuit 5 performs cumulative addition on the input internal state information of the reproduction circuits 2 and 3 in response to the start signal from the monitoring / control circuit 1 (steps S6 and S7), and sets the internal addition counter. After counting up, the system waits until the next input is performed. The addition counter counts the number of intervals sufficiently shorter than the interval time for extracting the internal state information of the carrier recovery circuit 2 and the clock recovery circuit 3.

  On the other hand, the detection circuit 4 detects the received wave input from the input terminal A using the recovered carrier wave and the recovered clock from the recovery circuits 2 and 3, and outputs the extracted data component to the output terminal B at the subsequent stage. At the same time, the difference (error) information between the detected received wave, the recovered carrier wave, and the recovered clock is fed back to the monitoring / control circuit 1 (step S8).

  The monitoring / control circuit 1 controls synchronization processing by outputting a synchronization control signal to the reproduction circuits 2 and 3 based on the error information fed back from the detection circuit 4. The reproduction circuits 2 and 3 operate so as to correct the frequency and phase of the reproduction signal output from its own circuit in response to the synchronization control signal, and to achieve frequency synchronization and phase synchronization (step S9).

  After shifting to the normal processing as described above, the above-described series of feedback processing excluding the initialization processing is cyclically performed for the current section in the received burst wave (steps S6 to S10).

  When the cumulative addition circuit 5 detects the end of the current processing interval from the counter value indicating the number of internal additions (Yes in step S10), the cumulative addition value up to that point is output to the average value calculation circuit 6 in the subsequent stage. After that, the register storing the added value is cleared and prepared for the next input (step S11).

  The average value calculation circuit 6 calculates an average value based on a preset cumulative addition interval (number of additions) for the input cumulative addition result, and outputs the average value to the synchronization determination circuit 7.

  The synchronization determination circuit 7 determines the synchronization state by comparing the input value with the internal state information of each reproduction circuit when the preset synchronization state is stable (step S12). As a result, if the difference is large, a loop band switching notification is sent to the monitoring / control circuit 1 so as to widen the loop band, and if the difference is small, the loop band is narrowed (step S12).

  Upon receiving this loop band switching notification, the monitoring / control circuit 1 changes the width (sensitivity) of the correction value to the reproduction circuits 2 and 3 to be output in accordance with the feedback from the detection circuit 4 (step S13). At this time, if the loop band setting value is too wide, the sensitivity to feedback becomes too sensitive and it is easy to cause loss of synchronization. Set upper and lower limits.

  After the correction of the loop band, the process up to the next loop band correction is repeated in the same manner for the remaining section of the current received burst wave (steps S5 to S14).

  When the monitoring / control circuit 1 detects the end of the burst wave that has been received so far (Yes in step S14), the monitoring / control circuit 1 notifies the carrier recovery circuit 2 and the clock recovery circuit 3 to switch from normal synchronization processing to state maintenance. In addition, the recording of information is notified to the average value calculation circuit 6.

  The reproduction circuits 2 and 3 enter a standby state in preparation for the input of the next burst wave while maintaining the circuit state (step S15), and the average value calculation circuit 6 stores the average value information in the last section of the burst wave. 8 is recorded (step S16).

  Thereafter, the processing from the detection of the burst wave (step S1) to the average value recording (step S16) in the monitoring / control circuit 1 described so far is repeated.

Block diagram of the synchronous detector of the invention The figure for demonstrating the average value calculation concept of the internal state information of the reproducing | regenerating circuit with respect to the burst wave in invention Process flowchart of synchronous detector of invention

Explanation of symbols

A input terminal B output terminal 1 monitoring / control circuit 2 carrier recovery circuit 3 clock recovery circuit 4 detection circuit 5 accumulative addition circuit 6 average value calculation circuit 7 synchronization determination circuit 8 storage circuit

Claims (3)

In a synchronous detection device for burst waves in digital wireless communication,
Means for performing cumulative addition at a sufficiently short interval for each section in which internal state information of a carrier recovery circuit for recovering a carrier and a clock recovery circuit for recovering a reception clock is arbitrarily set;
Means for calculating an average value for each section after cumulative addition;
Means for comparing the average value information with a preset reference value and determining the synchronization state, and means for correcting the loop band in the carrier recovery circuit and the clock recovery circuit as appropriate based on the determination result And a synchronous detector. In a synchronous detection device for burst waves in digital wireless communication,
A monitoring and control circuit for monitoring the received wave and controlling the operation of each circuit in the subsequent stage;
A carrier recovery circuit for recovering a carrier under control from the monitoring / control circuit;
A clock recovery circuit for recovering a received clock under the control of the monitoring / control circuit;
The carrier wave recovery circuit, the recovered carrier wave output from the clock recovery circuit, the received wave is detected using the recovered clock, the extracted data is output to the outside, and the detected received wave, the recovered carrier wave, the recovered clock, A detection circuit that feeds back the difference (error) information to the monitoring / control circuit;
Under the control of the monitoring / control circuit, the internal state information of the carrier wave recovery circuit and the clock recovery circuit is sequentially added for a preset number of times, and the addition up to that time is completed each time the set number of additions are completed. A cumulative adder that outputs the result value;
An average value calculation circuit for calculating and outputting an average value in the addition section based on a preset addition number value from the result of cumulative addition input from the cumulative addition circuit;
Average value data input from the average value calculation circuit, and internal state information of the carrier wave recovery circuit and the clock recovery circuit when synchronization processing between each reproduction signal and reception signal set in advance is stable A synchronization determination circuit that notifies the monitoring and control circuit of the switching of the loop band in each reproduction circuit from the difference,
A storage circuit that records an average value of internal state information of the carrier recovery circuit and the clock recovery circuit in the last section of the currently received burst wave;
The synchronous detection device, wherein the carrier recovery circuit and the clock recovery circuit refer to the average value recorded in the storage circuit as internal state information for reproduction when the next burst wave is received. A method for synchronous detection of burst waves in digital wireless communication,
Procedures for monitoring the received wave and controlling the operation;
Under the control, the carrier recovery circuit recovers the carrier wave, and the clock recovery circuit recovers the reception clock;
A procedure of detecting the received wave using the regenerated carrier wave and clock and outputting the extracted data to the outside;
A procedure for feeding back the difference (error) information between the detected received wave and the recovered carrier wave and the recovered clock for the monitoring and control;
Under the control, the internal state information of the carrier recovery circuit and the clock recovery circuit is sequentially added by a preset number of times, and the value of the addition result up to that time is output each time the addition for the set number of times is completed. Procedure and
An average value calculation circuit for calculating and outputting an average value in the addition section based on a preset addition number value from the result of cumulative addition input from the cumulative addition circuit;
The average value data is compared with the internal state information of the carrier recovery circuit and the clock recovery circuit when the synchronization processing between each reproduction signal and the reception signal set in advance is stable, A procedure for notifying the switching of the loop band in the reproduction circuit for the monitoring and control;
Recording the average value of the internal state information of the carrier recovery circuit and the clock recovery circuit in the last section of the currently received burst wave,
The synchronous detection method, wherein the carrier recovery circuit and the clock recovery circuit refer to the recorded average value as internal state information for reproduction at the time of reception of the next burst wave.

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