JP4427013B2 - Communication channel reception channel scan control apparatus and communication device reception channel scan control method - Google Patents

Description

  The present invention relates to a reception channel scan control apparatus, a reception channel scan control method, a reception channel scan control program, and a recording medium for a digital modulation type communication device.

2. Description of the Related Art A receiving device for a communication device is known which has a function of monitoring a receiving channel by sequentially switching a plurality of receiving channels. This function is generally called channel scan operation, and for each reception channel, it is instantaneously determined whether there is an incoming signal to be demodulated and output from a speaker or the like. It stays in the receiving channel until it disappears and is monitored while outputting sound, and when there is no incoming call, it shifts to the next receiving channel, and thereafter the same processing is successively continued.
FIG. 12 is a flowchart showing an example of conventional reception channel scan control.
In FIG. 12, when the channel change process (S101) is started, a count value of a timer for counting a preset time required for channel signal determination is initialized (S102), and an RSSI detection process is performed (S103). RSSI (Received Signal Strength Indicator) monitors the received field strength of a selected channel. For example, by monitoring the limiter level of an intermediate frequency amplifier circuit (IF) of a receiver, a desired signal can be obtained sufficiently. It is detected whether or not reception is performed with electric field strength. If the presence or absence of an incoming signal is determined based on the monitoring of RSSI, and it is determined that there is an incoming call (YES in S104), then noise detection is performed (S105), but if no incoming call is determined as a result of the RSSI monitoring in S104 (S104 NO), it is determined whether or not the count value of the timer has been set in advance, for example, 15 ms (S106). If not, the loop processing of S103, S104 and S106 is repeated (S106). NO). In the noise detection process, as known as normal noise squelch, it detects the amount of noise in the detected and demodulated received output. The smaller the received electric field strength, the higher the noise level in the detected and demodulated output. The presence or absence of an incoming signal can be determined. If there is no noise in this process or if it is smaller than a predetermined threshold, it is determined that there is an incoming signal (NO in S107), and the received and demodulated received audio signal is output from a speaker or the like ( S108). On the other hand, if it is determined that there is noise in the determination of the noise level in S107 (YES in S107), in order to confirm whether or not the noise is mixed in a pulse regardless of whether there is an incoming call, a timer is used for 30 ms. It is determined whether or not a period has elapsed (S109). If the timer count time is 30 ms or less in this process, the noise detection process setting in S105, the presence / absence determination of noise in S107, and the timer count value confirmation loop process in S109 are repeated. In the timer counting processes in S106 and S109, when the set time has elapsed, it is determined that there is no incoming signal in the reception channel, the process returns to the first process S101, and the processes described above are repeated. . As described above, in the conventional case where the reception channel scan is controlled based on the presence or absence of noise, it is necessary to confirm the continuity of noise over a time period of about 30 ms, for example. In particular, in mobile communications, the incoming field strength fluctuates significantly due to fading associated with movement, so that one-shot noise is frequently mixed. A means for confirming that the occurrence is continuously occurring is indispensable. Japanese Patent Application Laid-Open No. HEI 10-110826 discloses an invention in which hysteresis is given to a threshold level when performing squelch opening / closing control. In this example, RSSI that is an electric field strength level is also used. .
JP 2002-232306 A

However, in the conventional reception channel scan control apparatus and method described above, due to the use of RSSI and noise detection, in order to maintain the stability and certainty of scan control at a weak electric field strength, processing for a long time is required. There was a problem that it took. For example, in the above-described example, at least about 15 ms is required for RSSI monitoring, and further about 30 ms is required for noise detection, which requires a total of 45 ms. Also, if there is a high level interference wave in the vicinity of the reception channel, RSSI detection may be determined even if there is no incoming call on the reception channel, and scan stop processing is also performed for channels that do not require monitoring. May be. Furthermore, when scanning a plurality of reception channels in which a digital modulation signal and a conventional analog modulation signal which have been adopted in recent years are mixed, the stability and certainty of the scanning process may be further impaired.
FIG. 13 is a time chart for explaining the processing time in these conventional scanning methods. In FIG. 13A, it is determined that there is no incoming call in the RSSI detection (NO in S104), and when RSSI is not detected even after 15 ms in the timer count (S106), the process shifts to scanning to the next reception channel. In this case, the time required to move to the next channel is 15 ms.

FIG. 13B is a time chart when it is determined that there is an incoming call in RSSI detection in S103 of FIG. 12 and there is noise (no incoming call) in S105 and S107. In this case, since the presence / absence detection detection of noise is performed for 30 ms following the RSSI detection, in this case, a total of 45 ms is necessary as already described. FIG. 13C is a time chart when it is determined that there is an incoming call in RSSI detection in S103 and there is no noise (has incoming call) in S105. When receiving a digitally modulated signal, RSSI detection and noise detection are followed by frame synchronization word detection, and voice is output only after the frame synchronization word is detected. In this case, since the frame synchronization word is not detected in this processing, it is necessary to separately determine whether the modulation is digital modulation or analog modulation. In this example, when reception monitoring is not performed on the analog modulation channel, frame synchronization word detection is performed for a predetermined time, and then the next channel is shifted. Therefore, 180 ms required for frame synchronization word detection is added. A total of 225 ms is required.
SUMMARY OF THE INVENTION An object of the present invention is to solve such problems of the prior art, and a receiving channel scan control device and a receiving channel for a communication device capable of scanning a plurality of receiving channels quickly and stably. An object of the present invention is to provide a scan control method, a reception channel scan control program, and a recording medium.

In the present invention, in order to achieve the above object, the reception channel scan control apparatus according to claim 1 is provided in a communication device having a function of sequentially monitoring a plurality of reception channels and scanning the reception channels. A symbol timing detection unit for detecting a symbol timing from the received digital modulation signal, and determining whether the received channel is to be monitored based on whether the symbol timing is detected by the symbol timing detection unit The symbol timing detection unit oversamples the detection signal at a frequency that is three times or more the clock frequency of a reference oscillator included in the communication device. to obtain timing, each symbol data obtained sequentially Timing is, counts each case has progressed to the case where a delay with respect to the previous symbol timing, if the count value when the delayed exceeds a predetermined threshold value, the communication device detection unit When the count value in the case of advancing is shifted by +1 by one clock of the reference oscillator and exceeds a predetermined threshold, the detection timing in the detector of the communication device is set to one clock of the reference oscillator. The shift in symbol timing is corrected by shifting by −1.
The reception channel scan control device according to claim 2, when the symbol timing detection by the symbol timing detection unit is successful, or by detecting the frame synchronization word simultaneously with the symbol timing detection by the symbol timing detection unit. When the frame synchronization word is detected, scanning of the reception channel is stopped.

The reception channel scan control method according to claim 3 is a reception channel scan control method for a communication device having a function of sequentially monitoring a plurality of reception channels and scanning the reception channels. When the reception channel scan control is performed by determining whether the received channel is to be monitored based on whether or not the symbol timing is detected from the digital modulation signal, the reference oscillator included in the communication device is used as the detection signal. The symbol timing is obtained by oversampling at a frequency of three times or more of the clock frequency, and each of the sequentially obtained symbol timings is counted with respect to when it is delayed or advanced with respect to the previous symbol timing. If the count value in case of delay exceeds the predetermined threshold, When the detection value in the detection unit of the communication device is shifted by one clock of the reference oscillator by one clock and the count value in the case of advance exceeds a predetermined threshold, the detection timing in the detection unit of the communication device is set to the reference The shift of the symbol timing is corrected by shifting the oscillator by one clock minus one.
The reception channel scan control method according to claim 4 is the reception channel scan control method according to claim 3, wherein the frame synchronization word is detected when the detection of the symbol timing is successful or simultaneously with the detection of the symbol timing. If the frame synchronization word is detected, scanning of the reception channel is stopped.

Since the present invention is configured or processed as described above, it has the following effects.
The reception channel scan control apparatus according to claim 1 is configured to detect a clock signal superimposed on data in a reception signal and perform scan control of the reception channel based on the detection result of the clock signal. As described above, the reception channel scan can be controlled instead of or in combination with the RSSI detection and the noise detection, and quickness, stability and reliability are improved.
The symbol timing detection unit oversamples the detection signal at a frequency that is m times the clock frequency, and determines whether each sequentially obtained symbol value is the same as the previous symbol value. Since the clock is surely detected without performing detection, the clock signal detection indispensable in the reception channel scan control of the present invention can be surely executed.
In the reception channel scan control device according to claim 2, since the clock signal superimposed on the reception signal and the frame synchronization word are detected and the reception channel scan is controlled based on the detection result, the speed is further improved. Reception channel scan control is possible.
Since the reception channel scan control method according to claim 3 or 4 provides a method for implementing the reception channel scan control device according to claim 1 or 2 , each request is made as software processing using a CPU or DSP. It is useful for creating a program for carrying out the invention described in the section, or for carrying out the present invention using various functional blocks .

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the technical terms, components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are not intended to limit the scope of the present invention only to specific examples unless otherwise specified. Only.
As described above, the present invention regenerates a clock superimposed on data in a digital modulation signal in place of or in combination with conventional RSSI monitoring and noise detection, or a frame synchronization word when performing a reception channel scan. And receiving channel control based on the detection result. As will be described later, as similar means, it is possible to determine whether or not a desired signal has arrived by detecting an eye pattern of a received signal, or detecting a symbol clock and symbol timing, and these can be used. Hereinafter, the present invention will be specifically described, but prior to that, matters necessary for understanding the present invention will be briefly described.
In digital wireless communication, data to be transmitted is transmitted and received in units of frames, but a synchronization signal (Frame Sync Word) having a specific signal arrangement pattern at a predetermined position of each frame, for example, the beginning of the frame, on the transmitter side The receiver side demodulates the information bits after establishing synchronization by detecting the frame synchronization word in the detection output signal.

Also, in land mobile radio systems, fluctuations in received electric field strength due to movement become extremely large, so a frequency modulation method (FM: Frequency Modulation) with little fluctuation in demodulated sound output level relative to fluctuations in received electric field strength is used. Furthermore, in FM communication, in order to avoid the inconvenience that a very large noise is output from the speaker when there is no signal (no incoming signal), the audio output is conventionally blocked when noise of a certain level or more occurs. It is common to provide a squelch function.
In general, when a receiver reproduces a symbol clock from a baseband signal obtained by detection and reproduces a digital signal based on the symbol clock , a difference in reference oscillation frequency between the transmitter and the receiver or fading is caused. Due to the influence, a deviation between the Nyquist point and the symbol timing (symbol acquisition timing) occurs, and if this deviation becomes large, the bit error rate may deteriorate and data reproduction may become impossible. For this reason, it has been well known that the oscillation frequency of the reference oscillator that generates the clock signal of the receiver is synchronized with the symbol timing detected from the signal detected by reception.
There are various digital modulation methods, but a standard called US standard APCO Project 25 (hereinafter referred to as APCO P25) is known as a modulation method used in a land mobile communication system.

FIG. 1 is an eye pattern showing a relationship between a frequency shift value and a threshold value in a wireless receiver employing the APCO P25 method. The eye pattern is a digital signal waveform superimposed on a period of time and observed with an oscilloscope, and is called an eye pattern because it is rounded and shaped like an eye. As the state of the communication line is better, the electric field strength is sufficiently obtained and the SN (signal-to-noise ratio) is better, an aggregate of single curves is obtained as shown in FIG.
In APCO P25, a four-value FSK modulation scheme is adopted, and each symbol value corresponds to a frequency shift in the digital modulation signal, and the frequency shift is 600 [Hz], 1800 [Hz], −600 [Hz], and −1800 [Hz] has been subjected to any frequency shift, and each symbol represents a combination of 2 bits, “00”, “01”, “10”, or “11”. . In determining which value the sampled frequency shift amount corresponds to, 0 [Hz], 1200 [Hz], and -1200 [Hz] are used as threshold values.
In the present invention, in the reception channel scan, instead of RSSI monitoring and noise detection as in the prior art, the clock superimposed on the data is reproduced or the frame synchronization word is detected in the digital modulation signal , and the detection result is obtained. Based on this, reception channel control is performed. Therefore, when the present invention is applied when the symbol rate of the APCO P25 is 4800 bps, if the number of symbols to be detected is set to 60, the time required for detection may be 12.5 ms (dividing 60 symbols by 4800 bps). I understand. If a symbol can be detected within this period, that is, if an eye pattern can be detected, it is determined that there is an incoming signal, the channel scan is stopped and a frame synchronization word is detected, and if a frame synchronization word can be detected, reception monitoring processing When the eye pattern cannot be detected, it is determined that the digital modulation signal is not received, and the process proceeds to the next channel.

FIG. 2 is a flowchart of a reception channel scan process according to an embodiment of the present invention. When the process shown in this example proceeds to the reception channel change process (S1), the timer for counting the detection time is initialized (S2), the symbol detection process (S3) is started, and the process is based on a predetermined modulation method. It is determined whether or not a symbol can be detected. In this symbol detection process, if a symbol can be detected, it is determined that the signal to be received has arrived, scanning is stopped, a frame synchronization word is detected, a series of digital signal demodulation procedures are performed, and reception of the channel is performed. A monitor is executed (S5). On the other hand, when the symbol cannot be detected in the symbol detection process S4 (S4 NO), it is determined whether or not the time count by the timer has elapsed 12.5 ms, and if not (S6 NO), Returning to the symbol detection process S3, a loop process including a symbol detection determination process S4 and a timer counting process S6 is performed. If the symbol cannot be detected within 12.5 ms in this loop processing (YES in S6), it is determined that there is no incoming call to be received on the receiving channel, and scanning processing for the next receiving channel is to be started. The process returns to the channel change process start process S1 and the above-described flow is repeated. In this process, the eye pattern is detected by detecting symbols for a predetermined time, in this example, 12.5 ms for 60 symbols, and the same means as clock recovery in the sense of implementing the present invention. I can think about it. That is, since the frequency shift value of FSK in the communication system is known, if symbol detection is performed over a certain period, the arrival of a desired signal can be confirmed in the same manner as reproducing the clock. The same applies to the following description. Terms such as clock recovery , symbol timing detection, and eye pattern detection are used to determine whether or not a desired signal has arrived as a means used for reception channel scan control intended by the present invention. Then, it has almost the same meaning.

FIG. 3 is a time chart when the reception channel scan processing based on the present invention described above is performed. (A) shows the time required when the eye pattern cannot be detected as a result of eye pattern detection and the next reception channel is scanned. In the example in which the eye pattern is detected from 60 symbols in the APCOP 25, only 12 are shown. .5 ms is enough. (B) is a time chart when the eye pattern is successfully detected and then the frame synchronization word is detected. If the eye pattern detection (clock signal detection or symbol detection) is successful, the reception channel scan is stopped. In order to perform reception monitoring on the reception channel, the frame synchronization word is detected and synchronization is established. In this case, since it is confirmed that the signal to be demodulated is received by the eye pattern detection, the subsequent frame synchronization word processing is not wasted. In other words, since an eye pattern detection and a clock signal detection cannot be performed on an analog modulated incoming signal, it is found that there is no incoming desired signal on the channel, and it is possible to immediately shift to scan to the next channel. No frame synchronization word detection process is performed.
Thus, according to the present invention, since the incoming signal is confirmed by clock recovery (symbol detection, eye pattern detection), the conventional method described with reference to FIGS. 13 (a), (b), and (c) is used. It is clear that the time shortening effect can be greatly obtained as compared with the reception channel scanning process.
Note that although APCO P25 is 4-level FSK, since this frame synchronization word includes only binary values of ± 1800 Hz, it is relatively easy to detect other information frames. Therefore, the detection of the frame synchronization word may be performed at the same time, and the reception channel scan control may be performed based on the detection result of which frame synchronization word detection or clock signal detection is earlier. In addition, since frame synchronization word detection is an essential process in the receiver, if it is implemented in a block other than the reception channel scan control device according to the present invention, the entire configuration can be diverted. It will be useful from the point of simplification.

FIG. 4 is a flowchart showing another embodiment of the present invention. In this example, when a reception channel scan is started (S11), a channel change process is started (S12), a timer is reset (initialized) (S13), and symbol detection and frame synchronization word detection are executed (S14). ). In this process, it is first determined whether or not a symbol can be detected, that is, whether or not a clock can be reproduced (S15). In the embodiment described above, clock recovery (eye pattern detection) is performed by detecting 60 symbols. However, in this example, the number of symbols is not limited to 60, and a certain number of symbols are detected. When a symbol has been detected (S15 YES), the process proceeds to the next frame synchronization word detection process .

Although A PCO P25 is 4-value FSK, this frame synchronization word includes only 2 values of ± 1800 Hz and is only 5 ms. Therefore, for example, in the above (step S15), when a symbol of 5 ms or more can be detected, the process proceeds to the next frame synchronization word detection, and it is confirmed whether or not the detected symbol is a frame synchronization word. If it is confirmed, it is determined that the desired signal has arrived, and the reception channel scan is stopped (S16). Therefore, when the first detected symbol is a frame synchronization word, it is possible to determine the arrival of the desired signal and control the reception channel scan in the shortest time of 5 ms. On the other hand, if it is determined that there is no symbol in the symbol detection determination in step S15 (NO in S15), the frame synchronization word detection determination in step S18 is performed until the timer count value has passed 12.5 ms in step S16, If the frame synchronization word can be confirmed (S18 YES), it is determined that the desired signal has arrived, and scanning is stopped. However, if the frame synchronization word cannot be detected in this processing, the loop processing of steps S14, 15 and 17, 18 is performed. (S18 NO). If the symbol detection is confirmed in step S15 during the loop processing, the process proceeds to step S16, and if the detected symbol is a frame synchronization word, the scan control is immediately completed. If 12.5 ms elapses in step S17 during this loop process, it is determined that the desired signal does not arrive on the reception channel, the process proceeds to the next channel, and the same process is repeated (YES in S17). According to this method, scan control for each channel can be performed with processing of 5 ms at the shortest time and 12.5 ms at the maximum, and therefore, reception channel scan control can be performed much more quickly than the conventional method. .
It should be noted that some conventionally known methods may be applied to the eye pattern detection means, symbol detection means or clock recovery means performed in the present invention. For example, the invention described in Japanese Patent Application Laid-Open No. 2003-333113 “Clock Recovery Device, Clock Recovery Method and Program” already filed by the same applicant can be applied.
Further, although not disclosed, the same applicant has already filed “clock reproduction device, clock reproduction method, clock reproduction program and recording medium”, and it is more effective if this means is used in the present invention. Therefore, the present invention will be described.

FIG. 5 is described as FIG. 1 in the above-mentioned Japanese Patent Application Laid-Open No. 2003-333113 “Clock Recovery Device, Clock Recovery Method and Program”. Since this detail is described in detail in the above publication, it will be briefly described. This device acquires the symbol timing based on the synchronization word included in the detection signal, and voltage-controlled oscillation so as to synchronize with this. The circuit (VCO) 91 is controlled to generate a symbol clock. In this example, the terms “symbol clock detection” and “symbol timing detection (acquisition)” are used. However, as described above, from the viewpoint of achieving the object of the present invention, it is almost the same as symbol detection and clock recovery. Used in meaning.
In FIG. 5, 92 is a quaternary determination unit that generates a quaternary signal from the detected signal according to its frequency shift, and 93, 94, 95, 96, and 97 are clock delays that delay the input signal according to the symbol clock. Reference numerals 98, 100, 101, and 102 denote adders, which function as subtractors when a minus sign is present at the input end. 99 is an attenuator that converts the output value of the adder 98 into a half value thereof, 103 is a multiplier that multiplies the outputs of the adder 100 and the adder 101, and 104 is the output of the multiplier 103. Reference numeral 105 denotes a low-pass filter that controls the VCO 91 based on the output of the gate section 104. The gate section 105 passes when the output value of 102 is not zero and shuts off when the output value is zero.
Here, the function of the low-pass filter 105 is important. The initial value is M, and the counter 104 counts up in a predetermined cycle while the output of the gate unit 104 is positive, and counts down in the cycle while it is negative. As a result, when the count value reaches 2M, the VCO 91 is instructed to advance the symbol clock phase by a predetermined value (one sampling), and the count value is reset. On the contrary, when the count value reaches 0, the VCO 91 is instructed to delay the symbol clock phase by a predetermined value (one sampling), and the count value is reset.

Explaining the basic operation of the clock recovery apparatus configured as described above, the quaternary signal generated by the quaternary determination unit 92 is, for example, a frequency shift of ± 1.8 kHz in the APCO P25 system. , And four values of ± 1.8 and ± 0.6 corresponding to ± 0.6 kHz. This signal passes through the delay circuits 96 and 97, the adder 98, the attenuator 99, and the like, and generates a signal that is handled as a reference value of the quaternary signal in the route to the adder 100. That is, the output signal of the attenuation unit 99 is handled as a reference value of the quaternary signal.
The output of the adder 102 is zero (0) when the current 4-level signal is equal to the value before one sampling, and has a certain value when not equal. The gate unit 104 is gate-controlled by the output of the adder unit 102, and when the output is zero (0), that is, when the previous sampled value is equal to the current sampled value, the signal supplied from the multiplier unit 103 Is not output to the LPF, and conversely, when the output value of the adder 102 is not zero, the output of the multiplier 103 is supplied to the LPF 105. This means that if the previous sampling value (which may be replaced with a four-value signal) is the same as the current sampling value, the sampling timing (sampling value acquisition timing) and the Nyquist point for the two samplings The clock frequency is maintained as it is, but when the two values are different, the sampling timing is shifted, so that the frequency control signal supplied to the LPF is corrected. To do.
According to the above-described prior art, since the symbol timing is detected using the frame synchronization word, it may not be possible to determine whether or not there is a shift in the symbol clock until the synchronization word can be detected. In addition, if the accurate clock timing cannot be obtained in the synchronization word detection process, the correct symbol timing cannot be obtained. Therefore, even if the symbol clock regeneration process is performed, the symbol clock cannot be corrected. It was.

FIG. 6 is a block diagram of a clock recovery apparatus which is an improvement over the conventional apparatus described above.
In the figure, reference numeral 1 denotes a detector, which converts an instantaneous value of a frequency shift amount at each sampling timing from a received digital modulation signal (converted to an intermediate frequency IF signal if necessary) into a signal level and outputs the signal level. The number of samples is 5 samples per symbol, and oversampling is performed at a frequency five times the symbol clock.
6 in FIG. 6 is a quaternary determination unit. As described above, in the APCO 25 system, for example, ± 1.8, ± 0.6 corresponding to the frequency shift, ± 1.8 kHz, ± 0.6 kHz. One of the four values.
6 is a delay unit that holds the previous output in order to calculate the current output and the previous output of the quaternary determination unit 122, and 4 is the current value of the quaternary determination unit 2. An XOR operation circuit that calculates an exclusive OR of the output and the previous output, 5 is an accumulation unit that accumulates the operation results of the XOR operation circuit 4 in a buffer matrix and obtains an integrated value for each buffer column, and 6 is a buffer A gate unit 7 outputs an integrated value in the integrating unit 5 every time the matrix is filled. A symbol timing detecting unit 7 detects a symbol timing in the detecting unit 1 based on the integrated value from the gate unit 6.

FIG. 7 shows an eye pattern based on a digital modulation signal. FIG. 8 is a diagram showing a detection signal based on the digital modulation signal on the time axis. In these figures, the numbers, symbols, and symbols have the following meanings.
41: Dashed line 42 indicating sampling timing in the detection unit 1 42: Dashed line 43 indicating a threshold value for determining which symbol value each sampling value corresponds to: A quaternary signal output by the quaternary determination unit 2 2-bit value 44 indicating: output value 45 of XOR operation circuit 4 based on quaternary signal: column number of buffer in which each output value is stored Black circle: ideal symbol point White circle: sampling value at other sampling timing Although not shown in the figure, the buffer is composed of a buffer matrix of n rows × m columns used in the accumulating unit 5, and m corresponds to the number of sample points in one symbol section (m is an integer of 3 or more). n (n1 or an integer greater than or equal to 2) corresponds to the number of symbol intervals in which the operation result of the XOR operation circuit 4 should be stored for the buffer matrix in the accumulating unit 5. In this example, m is 5, and the number of each buffer column is 0-4.
The quaternary determination unit 2 performs a hard decision to determine to which range the sample value indicated by the detection signal belongs, and obtains a symbol value corresponding to the sample value. In this way, by storing each sample value in an n-row × m-column buffer memory to detect a deviation from the center position of adjacent sample values and controlling the voltage-controlled oscillator to correct it, The food back control is performed so that the Nyquist point and the symbol acquisition timing point in sampling coincide with each other.
As a result of examining this method in detail, there is a case where the Nyquist point lags behind the symbol acquisition timing and the case where the Nyquist point is advanced and the range in which the follow-up control can be performed by feedback control so that they coincide with each other, and there is a case where the balance becomes unbalanced. There was found. In order to improve this, the following means have been invented and filed.

FIG. 9 is a schematic block diagram of a clock recovery apparatus according to the improved invention. Note that the block diagram shown in this example is functionally represented, and is not necessarily limited to this example, and any configuration may be used as long as it functions as described below.
The clock recovery device 20 shown in this example detects a received signal and detects the original signal superimposed on the carrier signal on the transmission side, and 4 according to the frequency shift amount from the detection signal. A quaternary determination unit 22 that outputs two signals, a delay unit 23 that delays the output signal of the quaternary determination unit for a predetermined time, an output of the quaternary determination unit 22 and a delay unit 23 that delays the output of the quaternary determination unit 22 for a predetermined time An XOR operation circuit 24 that calculates the exclusive logical product of the outputs, an operation result of the XOR operation circuit 24 are accumulated in the buffer matrix, and an integration unit 25 that obtains an integration value for each buffer column, and integration every time the buffer matrix is filled The gate unit 26 that outputs the integrated value in the unit 25, and the switch unit 27 that includes terminals a, b, and c for dividing the integrated value signal from the gate unit 26 into three. The terminal a of the switch unit 27 is connected to a timing advance processing route including a counter up unit 28, a second gate unit 29, and a threshold unit 30 that supplies a threshold to the second gate unit 29. Then, it is connected to the symbol timing detection unit 31 via this route. The terminal b of the switch unit 27 is directly connected to the symbol timing detection unit 31. Further, a timing delay processing route including a counter-down unit 32, a third gate unit 33, and a threshold unit 34 for supplying a threshold to the third gate unit 33 is connected to the remaining terminal c of the switch unit 27. It is connected to the symbol timing detector 31 via this route. The output of the symbol timing detection unit 31 is supplied to the detection unit 21, and the timing deviation is corrected by correcting the detection timing.

FIG. 10 is a flowchart showing the control procedure of the embodiment of the present invention shown in FIG. The clock recovery apparatus according to the present invention will be described with reference to this figure.
In FIG. 10, when processing is started, clock recovery is first performed (S201), and it is determined whether or not the processing at that time is a change in symbol clock timing. If the processing is a change in symbol clock timing (YES in S202). The state of the symbol timing is detected (S203). The detection of the symbol timing state is detected, for example, by comparing adjacent sampling values of the sampling data stored in the memory in the integration unit 25, the first gate unit 26, the symbol timing detection unit 31, and the like. Note that the terminal 27 of the switch 27 is selected at the start of processing, and the output of the first gate unit 25 is directly supplied to the symbol timing detection unit 31 directly. As a result of this detection, when there is a deviation in the symbol clock timing, different processing is performed depending on whether it is delayed or advanced. First, in step S203, if there is a delay in the symbol clock (S203, S204), the switch 27 is switched to c to select a timing delay processing route. When there is a delay in the symbol acquisition timing, the count and value of the counter down unit 32 are decremented by one (S205). Further, the count value at that time is compared with the threshold value (threshold value) 34 in the third gate unit 33, and if it is equal to or exceeds the threshold value (YES in S206), the sampling timing is shifted by one clock plus one ( At the same time as S207, the counter value is reset and the series of processing ends (S208). In step S206, if the count value is not a threshold value, the process ends in the same manner.
On the other hand, if the symbol clock has advanced in step S203 for detecting the symbol timing state in step S203 (S203, S209), the switch 27 is switched to a to select the timing advance processing route. If there is progress in the symbol acquisition timing, the count and value of the counter up unit 28 are incremented by one (S210). Further, the count value at that time is compared with the threshold value (threshold value) 30 in the second gate unit 29, and if it is equal to or exceeds the threshold value (S211 YES), the sampling timing is shifted by -1 for 1 clock. Along with (S212), the counter value is reset, and a series of processing ends (S208). If the count value is not a threshold value in step S211, the process ends in the same manner.

FIG. 11 shows the state of the counter operation in the above processing. At steps S204 and S209, the counter value is decreased or increased based on the respective determination results, and when the counter value reaches the threshold value. The phase of the clock frequency for one sampling is corrected. That is, as shown in FIG. 11, as long as it is positioned between the upper and lower thresholds with the 0 level line as an ideal symbol timing as a boundary, accurate symbol data can be detected. Since correction is not necessary, only the counter value is increased or decreased. However, when the count value exceeds the threshold value, an accurate symbol value can no longer be acquired at the same symbol acquisition timing. As a result, even if the symbol rate is delayed or advanced, the width between the Nyquist point and the symbol acquisition timing can be secured as wide, so that both are balanced and consequently the tracking range is expanded. It will be a thing.
As described above, the detection signal is oversampled at a frequency of three times or more, the delay / advance state of the symbol acquisition timing at each sampling timing is detected, and the oscillation frequency of the oscillation means for clock recovery according to the situation Thus, even if the sync word cannot be detected, the clock can be recovered. In addition, since the interval between the symbol acquisition timing point and the Nyquist point is similarly increased on the timing advance side, and both are balanced, a stable clock recovery device can be obtained.
Further, since the symbol acquisition timing can be varied in this method even for a symbol rate deviation that cannot be followed by the normal symbol clock reproduction method, an accurate clock signal can be reproduced sufficiently following the symbol acquisition timing. .

The realization of the clock recovery means is not limited to the above-described embodiment, and can be implemented with appropriate modifications. For example, in the above description, the symbol clock is acquired using the sampling timing corresponding to the central buffer column as the symbol timing, and the symbol clock is corrected by adjusting the integrated value of the central buffer column to be the minimum. Yes. That is, although the center buffer string is used as a reference, symbol clock acquisition and correction may be similarly performed using a predetermined buffer string other than the center instead.
Therefore, if such a clock recovery means is applied, the reception channel scanning apparatus and method according to the present invention can be easily realized, and the reliability is improved. In implementing the present invention, it is also possible to use conventional RSSI monitoring means and noise detection means in a range that does not suffer from the adverse effects.
Furthermore, in the above description, a 4-level FSK modulation signal is used as the digital modulation signal, but the present invention is not limited to this, and can be applied to a digital modulation signal of any other system. However, the modulation method is not limited to FSK, and other modulation methods such as PSK can be widely applied to those in which a received signal includes a clock signal.

It is an eye pattern schematic diagram in APCO P25. 4 is a flowchart of reception channel scan control according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a time required for a reception channel scan in an embodiment of the present invention, where (a) is a time chart when an eye pattern cannot be detected, and (b) is a case where an eye pattern can be detected and scanning is stopped. It is a time chart. It is a flowchart which shows the other embodiment of this invention. It is a block block diagram which shows one Embodiment of the clock detection apparatus which can be utilized in this invention. 1 is a block configuration diagram showing an embodiment of a clock recovery device that can be used in the present invention. It is a figure which shows the example of the eye pattern in APCOP25. It is a symbol value transition diagram of a clock reproduction device. 1 is a block diagram of a clock recovery device that can be used in the present invention. It is a flowchart which shows the example of control of the clock reproducing | regenerating apparatus which can be utilized for this invention. It is a figure which shows the mode of operation | movement of the counter in one Embodiment of this invention. It is a flowchart which shows the example of the conventional reception channel scan control. It is a time chart in the conventional reception channel scan control.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 2: 1: Detection part 2, 22, 92: 4-value determination part 3, 23, 93, 94, 95, 96, 97: Delay part 4, 24: XOR operation circuit 5, 25: Accumulation part 6, 26, 29, 33: Gate section, 7, 31: Symbol timing detection section, 27: Switch, 28: Counter up section, 30, 32: Counter down section 34: Threshold section, 41: Sampling timing Broken line, 42: broken line indicating threshold, 43: symbol value, 44: output value of XOR operation circuit, 45: buffer column number, 91: voltage controlled oscillation circuit, 93: clock delay unit, 94 to 97: delay unit, 98: Adder, 99: Attenuator, 100-102: Adder, 103: Multiplier, 104: Gate, 105: Low-pass filter.

Claims (4)

  The symbol timing is provided in a communication device having a function of sequentially monitoring a plurality of reception channels and scanning the reception channels, and includes a symbol timing detection unit that detects a symbol timing from the received digital modulation signal. A reception channel scan control device that performs scan control of a reception channel by determining whether the reception channel is to be monitored based on whether or not symbol timing has been detected by a detection unit,
  The symbol timing detection unit obtains a symbol timing by oversampling the detection signal at a frequency that is three times or more the clock frequency of a reference oscillator included in the communication device, and sequentially obtains each symbol timing one before Counting is performed for each of the case where the timing is delayed and the timing where the timing is delayed. When the count value when the timing is delayed exceeds a predetermined threshold, the detection timing in the detection unit of the communication device is determined based on the reference timing. If the count value when the oscillator is advanced by one shift by one clock and exceeds the predetermined threshold, the detection timing in the detection unit of the communication device is shifted by one shift by one clock of the reference oscillator by one. A reception channel scan control device for correcting a timing shift.   The reception channel scan control apparatus according to claim 1, wherein when the symbol timing detection by the symbol timing detection unit is successful or when the symbol timing detection by the symbol timing detection unit is performed, a frame synchronization word is detected, A reception channel scan control device, which stops scanning of a reception channel when a frame synchronization word is detected.   A reception channel scan control method for a communication device having a function of sequentially monitoring a plurality of reception channels and scanning the reception channels,
  The communication device has a detection signal when performing scan control of the reception channel by determining whether the reception channel is to be monitored based on whether or not the symbol timing is detected from the received digital modulation signal. Symbol timing is obtained by oversampling at a frequency three times higher than the clock frequency of the reference oscillator, and each obtained symbol timing is delayed or advanced with respect to the previous symbol timing. Counting is performed, and when the count value in the case of delay exceeds a predetermined threshold, the detection timing in the detection unit of the communication device is shifted by one clock of the reference oscillator plus one and the count value in the case of advance Is over a predetermined threshold, the detection timing in the detection unit of the communication device Receiving channel scan control method characterized by correcting the deviation of the symbol timing by one clock -1 shift quasi oscillator.   4. The reception channel scan control method according to claim 3, wherein when the detection of the symbol timing is successful or when the frame synchronization word is detected simultaneously with the detection of the symbol timing, the reception channel is detected. A reception channel scan control method characterized by stopping scanning of the received channel.

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