JPH08288971A - Digital radio reception terminal equipment - Google Patents

Abstract

PURPOSE: To attain high speed synchronization and to obtain an excellent demodulation characteristic even when variance in delay of a received wave is high by selecting the extract method of a symbol clock and a time constant of a loop filter for a PLL depending on the reception state. CONSTITUTION: Timing extract circuits 62, 63 detect a symbol timing of a received phase modulation signal respectively by a zero crossing and a tri-state crossing and a timing detection changeover circuit 64 selects either of them. A PLL 65 has plural loop filters whose time constant differs from each other and selects any of them and generates a symbol clock synchronously with the selected timing. A controller 10 discriminates a reception state based on a reception level of a received wave and a decoding data error rate and controls the timing detection changeover circuit 64 and the PLL 65 so that the timing detection circuit 62 and the loop filter with a higher time constant are selected when large dispersion in delay of, e.g. the received wave is discriminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for a digital radio receiving terminal, and more particularly to a technique for recovering a symbol clock in a digital radio receiving terminal using a radio line in which delay dispersion can occur.

Here, the delay dispersion refers to the degree of spread of the arrival time of the plurality of reflected waves with respect to the preceding wave when a plurality of reflected waves are generated by the reflectors (buildings, mountains, etc.) in the propagation path.

[0003]

2. Description of the Related Art As a circuit for regenerating a symbol clock in a digital radio receiving terminal, for example, Japanese Unexamined Patent Publication (Kokai) No.
The circuit disclosed in Japanese Patent Publication No. 276206 is known. FIG. 11 is a block diagram of the circuit.
The operation of this conventional circuit will be described with reference to this figure.

In the figure, P input from the input terminal
The SK (Phase Shift Keying) modulated signal has its amplitude limited by the limiter amplifier 4, and is converted into a rectangular wave in which a plurality of phase components are superimposed. The phase data converter 61 quantizes the phase of the rectangular wave with a clock that is n times the symbol clock,
The difference between the phase and the phase one symbol before is calculated. The symbol timing extraction circuit 62 detects a point where the polarity of the phase difference changes (hereinafter referred to as zero cross), and outputs a pulse signal indicating the detection point. And a digital PLL
The (Phase-Locked Loop) 65 generates a clock synchronized with this output signal as a symbol clock. In this way, in the conventional circuit, the symbol clock used for determining the transmission timing of the symbol on the transmitting side is regenerated from the timing component of each symbol included in the PSK modulated signal.

[0005]

By the way, in the digital cellular communication using the π / 4 shift QPSK (Quadri-PSK) phase modulation system, the change in the phase difference of the received data has a plurality of patterns as shown in FIG. Take That is,
In this method, the polarity of the phase difference may not change even if the phase changes (for example, phase 3π / 4 to π /
4). For this reason, when the conventional circuit that reproduces the symbol clock at the zero-cross timing is applied to the above method, the number of timings that can be extracted becomes small, and it takes a long time to synchronize with the received wave.

Therefore, when it is necessary to perform high-speed symbol clock synchronization as in a handover in which the wireless zone is changed by the movement of the receiving terminal during communication, that is, when the base station is switched, the digital PLL 65 is previously set.
This problem was addressed by reducing the time constant of the loop filter of.

However, if the time constant is reduced, the PLL 65
The operation becomes unstable, and particularly when the reception condition is not good, the symbol clock to be reproduced has a large jitter, so that the demodulated data is deteriorated.

On the other hand, as shown in FIG. 3, two threshold levels other than the zero level are set, and the time when the phase difference crosses these three levels (hereinafter referred to as three-valued cross) is detected. If so, the number of detection timings can be increased, and thus high-speed synchronization can be achieved without reducing the time constant of the loop filter. However, the symbol timing extracted by ternary crossing has a larger jitter than the timing extracted by zero crossing in principle,
In particular, when the delay dispersion of the received wave is large, the jitter is further increased. Therefore, even when this ternary cross is used, the problem that the demodulated data deteriorates occurs.

Therefore, the present invention enables high-speed synchronization by switching the timing extraction method and the time constant of the PLL loop filter according to the reception state.
An object of the present invention is to provide a digital radio receiving terminal capable of performing good demodulation even when the delay dispersion of the received wave is large.

[0010]

According to a first aspect of the present invention, there is provided a digital radio receiving terminal for receiving a phase modulation signal for transmitting information according to a phase difference between symbols transmitted every symbol time. Phase difference measuring means for measuring the phase difference between the received phase modulated signal and the phase modulated signal received one symbol time before, and a first timing for detecting the timing when the phase difference measured by the phase difference measuring means becomes zero. Timing detection means, second timing detection means for detecting the timing when the phase difference measured by the phase difference measurement means becomes any one of a plurality of predetermined values, and timing detected by the first timing detection means. A timing detection switching unit that selects one of the timings detected by the second timing detection unit and a timing detection switching unit that selects the timing. A phase-locked loop that generates a symbol clock that is a clock that is synchronized with the clock, and demodulation means that generates demodulated data that demodulates the received phase-modulated signal using the symbol clock, and further, the received phase A signal strength measuring means for measuring the strength of the modulated signal, an error rate measuring means for measuring the error rate of the demodulated data, a strength measured by the signal strength measuring means is larger than a predetermined strength, and the error rate is measured. When the error rate measured by the means is larger than a predetermined error rate, the timing detection switching means is caused to select the timing detected by the first timing detection means, and in other cases, the timing detection switching means is operated by the timing detection switching means. And a control means for selecting the timing detected by the second timing detection means.

The invention described in claim 2 is the same as claim 1.
In the invention described, the phase-locked loop, a plurality of loop filters different in time constant from each other, a filter selection means for selecting one of the plurality of loop filters,
And a control unit for generating a symbol clock that is a clock synchronized with the timing selected by the timing detection switching unit with a response characteristic according to the time constant of the loop filter selected by the filter selection unit. When the strength measured by the signal strength measuring means is larger than the predetermined strength and the error rate measured by the error rate measuring means is larger than the predetermined error rate, the response characteristic of the phase locked loop becomes slow. The filter selection means is controlled so as to select a loop filter having a time constant, and the filter control means is controlled so as to select a loop filter having a time constant at which the response characteristic of the phase locked loop becomes high in other cases. It is characterized by

The invention described in claim 3 is the same as that of claim 2
In the invention described in, the frequency of the demodulation reference clock that follows the frequency of the received phase modulation signal, the automatic frequency control means for detecting that the error between the frequency of the received phase modulation signal has converged to a range, The control means is
The selection of the timing detection switching means and the response characteristic of the phase locked loop are controlled according to the detection result of the automatic frequency control means.

The invention according to claim 4 is the same as claim 3
In the invention described in (1), a frame formed by a plurality of demodulated data is identified, and a frame decoding unit that performs a decoding process in synchronization with the frame, and whether the frame decoding unit is in synchronization with the frame is detected. It is characterized in that it comprises a frame synchronization detecting means, and the control means controls the selection of the timing detection switching means and the response characteristic of the phase locked loop according to the detection result of the frame synchronization detecting means.

[0014]

In the invention described in claim 1, the control means is such that the strength measured by the signal strength measuring means is larger than the predetermined strength and the error rate measured by the error rate measuring means is higher than the predetermined error rate. Is larger, it is determined that the delay dispersion of the received phase modulation signal is large, and the timing detection switching means is caused to select the timing (zero cross) detected by the first timing detection means. By doing so, it is possible to generate a symbol clock using accurate timing, and therefore it is possible to reduce the jitter of the symbol clock, which is likely to occur when delay dispersion is large. In addition, in the cases other than the above, the control means determines that the delay dispersion is small, and causes the timing detection switching means to select the timing (for example, three-valued cross) detected by the second timing detection means. By doing so, it is possible to increase the number of timings that can be used for generating the symbol clock, and therefore it is possible to synchronize the symbol clock with the received phase modulation signal at high speed.

In the invention described in claim 2,
When the control means determines that the delay dispersion of the received phase-modulated signal is large, in addition to the above control, the filter is selected so as to select a loop filter having a time constant with which the response characteristic of the phase-locked loop becomes slow. Control the selection means. Thereby, the jitter of the symbol clock can be further reduced. When the control means determines that the delay dispersion of the received phase-modulated signal is small, the control means controls the filter control means so as to select a loop filter having a time constant with which the response characteristic of the phase-locked loop becomes high speed. To do. As a result, the symbol clock can be synchronized with the received phase modulation signal at a higher speed.

Further, in the invention described in claim 3,
When the automatic frequency control means does not detect that the frequency error converges to a certain range, the control means causes the timing detection switching means to select the timing detected by the first timing detection means, and causes the filter selection means to select the phase. Select a loop filter with a time constant that makes the response characteristics of the synchronous loop slow. As a result, the frequency drift value can be reliably converged.

According to the fourth aspect of the invention, when the frame synchronization detecting means does not detect the frame synchronization, the control means causes the timing detection switching means to detect the timing detected by the second timing detecting means. The filter selection means is caused to select a loop filter having a time constant with which the response characteristic of the phase-locked loop becomes fast. This allows
Frame synchronization is done at high speed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of the digital receiving terminal according to the present embodiment. In this figure, 1 is an antenna, 2 is a first IF section, 3 is a second IF section, 4 is a limiter amplifier, 5 is a digital demodulation circuit, 6 is a symbol clock recovery circuit, 7 is a channel codec, 8 is a voice codec, and 9 is a speaker. 10 is a system controller, 11
Is a reference oscillator, 61 is a phase data converter, 62 and 63 are symbol timing extraction circuits, 64 is a timing detection switching circuit, and 65 is a digital PLL (phase locked loop).

The outline of the operation of the above digital receiving terminal will be described below. The reception signal of the radio frequency received by the antenna 1 is frequency-converted into a first intermediate frequency by the first IF unit 2, band-limited by a first intermediate frequency filter (not shown), and then further by the second IF unit 3 and the drawing. The second intermediate frequency filter does not convert the signal into the band-limited second intermediate frequency signal. A log amplifier (not shown) of the limiter amplifier 4 amplifies the intermediate frequency signal and limits its amplitude to shape the intermediate frequency signal into a rectangular waveform, and then outputs it to the digital demodulator 5 and the symbol clock recovery circuit 6. To do. In addition, at the same time, the log amp receives RSSI (Received Signal Strength) proportional to the received signal strength.
th Indicator) signal is output to the system controller 10.

The phase data converter 61 of the symbol clock recovery circuit 6 generates a phase signal representing the phase of the rectangular wave output from the limiter amplifier 4 and outputs the phase signal of 1 and the phase represented by the signal.
The phase difference from the phase represented by the phase signal (reference phase signal) before the symbol time is measured. Symbol timing extraction circuit 6
Reference numerals 2 and 63 respectively detect the timing when the above-mentioned phase has a predetermined phase difference, and output it as a timing extraction signal.

The timing detection switching circuit 64 selects and outputs one of the two timing extraction signals according to the control of the system controller 10. Digital PL
L65 generates a symbol clock synchronized with the timing output from the timing detection switching circuit 64.

On the other hand, the digital demodulation circuit 5 demodulates the phase difference information from the rectangular wave output from the limiter amplifier 4, and samples the demodulated data at the timing of the symbol clock output from the symbol clock recovery circuit 6. The sampling data is subjected to processing such as interleaving and error correction in the channel codec 7, is converted into an audio signal by the audio codec 8, and is output as audio from the speaker 9. The demodulated data forms a frame, and a frame synchronization signal is attached to the head of the frame. In addition to the above processing, the channel codec 7 also detects frame synchronization and measures the error rate, and outputs the result to the system controller 10.

The case where the π / 4 shift QPSK modulation system used in the digital cellular for Japan is applied to the digital receiving terminal according to the present embodiment will be described below.

First, the QPSK modulation method will be described with reference to FIGS.

FIG. 2 shows a space diagram of the π / 4 shift QPSK system. In this method, information is added to the relative phase of data in two consecutive symbol periods, and four pieces of phase information (π / 4 [rad], 3π / 4 [rad], -π / 4 [ra] are used.
2 bits of information (I, Q) = (00, 01, 10, 11) are assigned to each of [d] and −3π / 4 [rad]). Therefore, the reference phase signal shown in FIG. 2 indicates the phase one symbol time before, and information is demodulated from the difference between this phase and the phase at the next symbol (hereinafter referred to as the differential phase). Further, the accuracy of the phase of the received rectangular wave is determined by the sampling rate of the rectangular wave, and when sampling is performed at a rate 32 times as fast as the symbol clock, for example, FIG.
A differential phase with an accuracy obtained by dividing the whole into 32 is obtained as shown in FIG. In this case, each differential phase can be represented by a value of 0 to 31 (5 bits).

FIG. 3 shows a differential phase eye pattern when the phase difference is plotted for each symbol. As can be seen from this figure, there are multiple points where the trajectory crosses in addition to the zero cross between each symbol, and the positions of these points have some variations compared to the zero cross, but on average the midpoint of the symbol clock is Show. That is, if the above-mentioned cross point is detected using two phase levels (π / 2, −π / 2), the symbol timing can be extracted although the variance is slightly larger than the zero cross.

Next, the above symbol clock recovery circuit 6
Will be described in detail with reference to FIGS. In these figures, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

FIG. 4 shows a block configuration of the phase data converter 61. In the configuration shown in this figure, the rectangular wave (for example, 21
The phase information of (kHz) is converted into N-bit (here, N = 5) phase data by the phase quantization circuit 611, and then supplied to the subtractor 613 and the 1-symbol delay unit 612. The subtractor 613 calculates the difference between this phase data and the phase data one symbol before which is delayed by one symbol in the one-symbol delay unit 612. As a result, the 5-bit differential phase data that is the calculation result is output to the symbol timing extraction circuits 62 and 63 (described later) via the terminal 61c. Here, the phase quantization circuit 611 and the 1-symbol delay device 612 are connected to the terminal 6
It operates at the timing of the reference clock (for example, 450 kHz) of the reference oscillator 11 supplied via 1b. The 1-symbol time is a predetermined time and is determined by the frequency of the rectangular wave (or the received phase modulation signal).

Next, the symbol timing extraction circuit 62 will be described with reference to FIGS. 5 and 6.

In FIG. 5, the differential phase data (1 bit) input from the terminal 62a is supplied to D type flip-flops (hereinafter abbreviated as D-FF) 621 and 622. On the other hand, the reference clock input from the terminal 62b is supplied to the D-FF 622 and the inverter 63
2 to the D-FF 621. D-FF62
The outputs of 1 and 622 are supplied to the comparator 624, and the mismatch signal of these two outputs is output to the terminal 62c. Figure 6
Shows the timing chart of this circuit. Terminal 62a
From this figure, it can be seen that a pulse is generated with a half cycle width of the reference clock at the rising and falling edges of the data input from.

The symbol timing extraction circuit 63, which is another timing detection means, has the same circuit configuration as the symbol timing extraction circuit 62 in this embodiment, but only the input data is different. Specifically, the symbol timing extraction circuit 62 has the most significant bit data (MSB) of the differential phase data, and the symbol timing extraction circuit 63 has the second most significant bit data (MSB-).
1) is supplied.

In the configuration described above, for example, when the differential phase data repeatedly changes from "0" to "31", the data of the above two bits changes as shown in FIG. The extraction timings of the symbol timing extraction circuits 62 and 63 are the extraction timings (a) and (b) of FIG. 7, respectively. Here, the extraction timing (a) indicates the zero-cross timing, and the extraction timing (b) indicates the ternary-cross timing. Further, in this case, the number of timings (three-valued crosses) that can be extracted by the symbol timing extraction circuit 63 is twice the number of timings (zero crossings) of the symbol timing extraction circuit 62.

In this embodiment, the timing detection switching circuit 64 is installed in the subsequent stage of the symbol timing extraction circuits 62 and 63. However, when the symbol timing extraction circuit has the same configuration and only the input phase data is different as in the case described above, the timing detection switching circuit 64 is placed in the preceding stage of the symbol timing extraction circuit and the phase data is extracted first. Can be selected. In this case, only one symbol timing extraction circuit is required, and the number of circuits is reduced.

Next, a specific example of the digital PLL 65 will be described in detail with reference to FIG.

In the configuration shown in FIG. 8, the phase comparator 65
1 compares the clock from the variable frequency divider 655 with the timing extraction signal supplied from the timing extraction switching circuit 64 via the terminal 65a, and outputs the digital information indicating the advance or delay of the reproduced clock to the loop filter 652 and Output to 653. The loop filter 652 having a relatively small time constant (short integration time) and the loop filter 653 having a relatively large time constant (long integration time) integrate information indicating advance or delay for a set period,
Individually output as integration information. The loop filter switching circuit 654 selects one of the integration results and outputs it to the variable frequency divider 655. This selection is performed according to the switching signal supplied from the system controller 10 via the terminal 65d. The variable frequency divider 655 performs processing such as frequency division or delay on the reference clock supplied via the terminal 65c based on the selected integration information so that the above-mentioned integration information becomes small. The generated reproduction clock is output to the phase comparator 651 and the terminal 65b.

By repeating the above closed loop processing, the clock output from the digital PLL 65 from the terminal 65b becomes a symbol clock synchronized with the timing of the signal input from the terminal 65a.

Next, a concrete example of the digital demodulation circuit 5 is shown in FIG.
Will be described in detail.

In the configuration shown in FIG. 9, the phase difference detection circuit 51 first phase-quantizes the modulation phase signal supplied from the limiter amplifier 4 with the reference clock supplied via the terminal 5c, and the phase and the reference phase. A phase difference from a reference signal (described later) supplied from the selector 54 is measured. Then, differential phase data is generated from the phase difference and the phase difference measured and stored one symbol time ago, and the differential phase data is output at the timing of the symbol clock input via the terminal 5b. The decoder 52 decodes the differential phase data from the correspondence between the differential phase difference information and the allocation data described with reference to FIG.

The automatic frequency control means 53 uses the differential phase data from the phase difference detection circuit 51 and its desired value (see FIG. 2).
The phase error data is measured from the difference with the phase data “4”, “12”, “20” or “28”) in step (4), and the data is integrated until it reaches a predetermined time constant (integration constant). At the same time, the reference clock from the terminal 5c is counted to obtain the time required to reach the time constant, and the average change rate (slope) of the integrated value is obtained from the counting time. This is the phase error value in the short section.

Further, the automatic frequency control means 53 successively outputs a phase selection signal corresponding to the magnitude of the phase error to the reference phase selector 54 to correct the frequency of the reference signal.
In addition, a new phase error is obtained for the received phase modulation signal each time, the current estimation result is updated, and the detected value of the frequency drift is converged. If the detected value of the frequency drift does not overflow by integrating the detected value of the frequency drift for a certain period of time, it is determined that the detected value of the frequency drift has converged (hereinafter, abbreviated as AFC lock), and information indicating the AFC lock is output via the output terminal 5d. Output to the system controller 10.

The reference phase selector 54 generates n reference signals having different phases based on the reference clock from the terminal 5c, and one of them is used as the automatic frequency control means 53.
It outputs to the phase difference detection circuit 51 according to the selection signal from. In this way, a reference signal matching the frequency and phase of the received phase modulation signal is created.

The processing of the system controller 10 will be described in detail below with reference to FIG.

First, in step S1, AFC is performed with a signal from the terminal 5d of the digital demodulation circuit 5 (see FIG. 9).
It is checked whether or not it is in the locked state, and if it is not in the AFC locked state, the process proceeds to step S8. In step S8, a switching signal instructing the selection of the output of the symbol timing extraction circuit 62 (see FIG. 1) is output to the timing detection switching circuit 64, and the PLL 65 is instructed to select the output of the loop filter 653 (see FIG. 8). A switching signal for switching is output. As a result, timing extraction is performed at zero cross, and the digital PLL 65 operates at a low speed with a loop filter having a large time constant, so that a stable symbol clock with a small jitter is generated. In this way, the synchronization and AFC lock to the received phase modulation signal are stably and reliably performed.

It should be noted that the above-mentioned processing is performed first because it is an important processing for canceling the frequency offset between the received signal and the reference phase signal by the automatic frequency control (AFC), and it is necessary to perform AFC lock with the highest priority. Because there is.

If the AFC lock is set (step S1 is "YES"), the process proceeds to step S2. In this step S2, it is checked whether or not the channel codec 7 detects the frame synchronization signal. If the frame synchronization is not achieved, it is determined that the handover is in progress, and the process proceeds to step S7. In step S7, a switching signal for instructing the selection of the symbol timing extraction circuit 63 is output to the timing detection switching circuit 64 in order to capture the frame synchronization at high speed, and at the same time,
A switching signal for instructing the selection of the loop filter 653 is output to the PLL 65. As a result, timing extraction is 3
The value crossing is performed so that the digital PLL 65 operates at high speed with a loop filter having a small time constant. As a result, a high-speed pull-in operation of the symbol clock timing is performed.

If frame synchronization is confirmed in step S2, the process proceeds to step S3. In step S3, the received electric field strength supplied from the limiter amplifier 4 is checked, and if the signal strength is larger than a certain value x, the process proceeds to step S4. In step S4, the channel codec 7
It is checked whether or not the value of the error rate of the demodulated data measured in is larger than y, and if it is larger, the process proceeds to step S5. At this time, the reception state is a state in which the demodulated data has a large error rate even though the reception electric field strength is high, and it is determined that the delay dispersion of the reception wave is large. Then, in step S5, the same processing as in step S8 described above is performed, so that the timing extraction is performed at zero cross, and the PLL 6
In 5, a loop filter with a large time constant is selected. That is, when the delay dispersion of the received signal is large,
The symbol clock recovery circuit 6 operates to reduce the jitter of the generated symbol clock, and as a result, the error rate of the demodulated data is reduced.

On the other hand, if the determinations in steps S3 and S4 are other than the above, that is, if either of the two determinations is "NO", the process proceeds to step S6. In step S6, the same processing as in step S7 described above is performed, and for high-speed timing synchronization, a ternary cross is selected and a loop filter with a small time constant is selected.

As described above, according to this embodiment, since the symbol timing extraction method and the response characteristic of the digital PLL are changed according to the reception state, the jitter is reduced even when the delay dispersion of the received wave is large. A small symbol clock can be generated, and high-speed synchronization can be performed at the time of handover. In addition, a flow chart (Fig. 1
In the description of the control using 0), both the timing reproduction system and the time constant of the loop filter of the digital PLL are switched and controlled, but the same effect can be obtained by the control of either one.

In this embodiment, the π / 4 shift QPSK modulation system is used as the modulation system, but it can be easily applied to other phase modulation systems. Also, the numbers of symbol timing extraction circuits and loop filters are not limited to those described above.

[0050]

As described above, according to the present invention, since the timing extraction method and the time constant of the PLL loop filter are switched according to the reception state, the symbol clock to be reproduced is synchronized with the received wave at high speed. In addition, it is possible to recover a stable symbol clock with a small jitter even when the delay dispersion of the received wave is large, and thus it is possible to obtain a good demodulation characteristic.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the symbol clock recovery circuit 6 of FIG.

FIG. 3 is a diagram for explaining the operation of the symbol clock recovery circuit 6.

4 is a block diagram showing a configuration of a phase data converter 61 of FIG.

FIG. 5 is a symbol timing extraction circuit 62, 6 of FIG.
3 is a block diagram showing the configuration of FIG.

FIG. 6 is a time chart of the symbol timing extraction circuit 62.

FIG. 7 is a time chart exemplifying the extraction timing of the symbol timing extraction circuits 62 and 63.

8 is a block diagram showing a configuration of a digital PLL 65 shown in FIG.

9 is a block diagram showing a configuration of a digital demodulation circuit 5 of FIG.

10 is a flowchart of the system controller 10 that controls the loop filter switching circuit 654 and the timing detection switching circuit 64 of FIG.

11 is a block diagram showing a conventional example of the symbol clock recovery circuit 6 of FIG.

[Explanation of symbols]

1 ... Antenna, 2 ... 1st IF part, 3 ... 2nd IF part, 4 ...
Limiter amplifier, 5 ... Digital demodulation circuit, 6 ... Symbol clock recovery circuit, 7 ... Channel codec, 8 ... Voice codec, 9 ... Speaker, 10 ... System controller, 11 ... Reference oscillator, 51 ... Phase difference detection circuit, 52 ...
Decoder, 53 ... Automatic frequency control means, 54 ... Reference phase selector, 61 ... Phase data converter, 62, 63 ... Symbol timing extraction circuit, 64 ... Timing detection switching circuit, 65 ... Digital PLL, 651 ... Phase comparator, 6
52, 653 ... Loop filter, 654 ... Loop filter switching circuit, 655 ... Variable frequency divider.

Claims (4)

[Claims] 1. A digital radio receiving terminal, which receives a phase-modulated signal for transmitting information by a phase difference between symbols transmitted every symbol time, receives the received phase-modulated signal and one symbol time before the received signal. Phase difference measuring means for measuring the phase difference with the phase-modulated signal, first timing detecting means for detecting the timing at which the phase difference measured by the phase difference measuring means becomes zero, and the position measured by the phase difference measuring means. Second timing detection means for detecting the timing at which the phase difference becomes one of a plurality of predetermined values, and one of the timing detected by the first timing detection means and the timing detected by the second timing detection means. The timing detection switching means for selecting either one, and the clock synchronized with the timing selected by the timing detection switching means. A phase locked loop for generating a symbol clock, demodulation means for generating demodulated data by demodulating the received phase modulated signal using the symbol clock, and signal strength measuring means for measuring the strength of the received phase modulated signal An error rate measuring means for measuring an error rate of the demodulated data, an intensity measured by the signal strength measuring means is larger than a predetermined intensity, and an error rate measured by the error rate measuring means is a predetermined error. When it is larger than the rate, the timing detection switching means is caused to select the timing detected by the first timing detection means, and in other cases, the timing detection switching means is controlled to select the timing detected by the second timing detection means. A digital radio receiving terminal comprising: a control unit for selecting. 2. The phase-locked loop includes a plurality of loop filters having different time constants, a filter selecting unit for selecting one of the plurality of loop filters, and a loop filter selected by the filter selecting unit. A response characteristic according to a time constant, and means for generating a symbol clock which is a clock synchronized with the timing selected by the timing detection switching means, wherein the control means has a strength measured by the signal strength measuring means. Is greater than a predetermined strength and the error rate measured by the error rate measuring means is larger than a predetermined error rate,
The filter selection means is controlled to select a loop filter having a time constant in which the response characteristic of the phase-locked loop becomes slow, and in other cases, a loop filter having a time constant in which the response characteristic of the phase-locked loop becomes fast. 2. The filter control means is controlled so as to be selected.
The digital radio receiving terminal according to. 3. An automatic frequency control means for detecting that an error between the frequency of the demodulation reference clock that follows the frequency of the received phase modulation signal and the frequency of the received phase modulation signal has converged to a certain range, The digital radio receiving terminal according to claim 2, wherein the control means controls the selection of the timing detection switching means and the response characteristic of the phase locked loop according to the detection result of the automatic frequency control means. 4. A frame decoding means for identifying a frame formed by a plurality of demodulated data and performing a decoding process in synchronization with the frame, and a frame for detecting whether or not the frame decoding means is in synchronization with the frame. 4. A synchronization detecting means is provided, and the control means controls the selection of the timing detection switching means and the response characteristic of the phase locked loop according to the detection result of the frame synchronization detecting means.
The digital radio receiving terminal according to.