JPH10163864A - Phase-locked loop control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the synchronization with the input data without dividing a reference clock by performing a NAND operation between the output signal of an interval timer and the output signal of a set/reset flip-flop which is set by the signal obtained by delaying the output signal of the interval timer and then reset by an effective cell detection signal and producing a phase step-out detection signal. SOLUTION: A set/reset flip-flop 11 is set by the signal that is obtained by delaying the output signal of a prescribed cycle produced by an interval timer 8 by a delay circuit 10, and an output terminal Q of the flip-flop 11 is set at H. On the other hand, an effective cell detection signal 6 that is produced by a signal processing circuit 4 resets toe flip-flop 11 and sets the output of the flip-flop 11 at L. A NAND circuit 12 performs a NAND operation between an output signal 9 and the output signal of the flip-flop 11 and outputs a phase step-out detection signal 13. A PLL mode control circuit 19 secures again the synchronization of a PLL for a prescribed time by means of the signal 13. Thus, the phase step-out of the PLL can be recovered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase locked loop (hereinafter, PLL) control system.

[0002]

2. Description of the Related Art In digital data communication and data reproduction in a recording device such as a magnetic disk, a clock which is phase-synchronized with reproduced data is generated by a PLL, and data "1" and "0" are discriminated based on the timing of the clock. I do. However, the PLL may not be able to maintain the phase synchronization state when large noise or jitter occurs in the input data or when the difference between the PLL oscillation frequency and the input data frequency is large. Therefore, in such a case, means for detecting the loss of phase synchronization and restoring the phase synchronization of the PLL is required.

For example, in an example disclosed in Japanese Patent Application Laid-Open No. Hei 7-15325, an out-of-synchronization detecting circuit includes a phase comparing unit, a magnitude comparing unit, a storing unit, and a data processing unit. The phase comparing means detects the phase difference between the clock generated by the PLL and the input data, and counts the difference with the reference clock.
The magnitude comparing means compares the output data of the phase comparing means with a predetermined reference value and outputs the result. The storage means stores the output results of the magnitude comparison means in chronological order. The data processing means processes the data in chronological order stored in the storage means, and outputs a phase out-of-synchronization signal when a phase difference equal to or more than a reference value occurs for a predetermined period or more.

[0004]

In the prior art, when a phase difference exceeding a predetermined reference value continues for a certain period or more, it is determined that the phase is out of synchronization. However, since the above phase difference is counted by the reference clock, and each value is compared with the reference value and each process of storing is performed, a reference having a sufficiently high frequency with respect to the clock to be subjected to phase synchronization is required to improve detection accuracy. Requires a clock. That is, this method is effective when performing phase synchronization between a clock obtained by dividing the reference clock and input data, and is difficult to apply to a system that performs phase synchronization between the reference clock and input data.

An object of the present invention is to provide an out-of-phase detection method which is effective in a system for performing phase synchronization with input data without dividing a reference clock.

[0006]

To achieve the above object, the out-of-phase detecting circuit according to the present invention comprises an interval timer, a delay circuit, a set / reset flip-flop (hereinafter, R-SFF) and a NAND circuit. The interval timer generates an output signal every predetermined period,
Supply to the delay circuit and the NAND circuit. R-SFF is
It is set by the output signal of the interval timer delayed by the delay circuit, and is reset by the valid cell detection signal generated by the signal processing circuit. The NAND circuit has an R-
A NAND operation is performed on the output signal of the SFF and the output signal of the interval timer to generate an out-of-phase detection signal. Thus, when no valid cell is detected for a predetermined period, that is, when normal data cannot be received, it is determined that phase synchronization has been lost, a phase loss detection signal is output, and PLL synchronization recovery is performed.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described with a transmission rate of 25 Mb.
ps ATM (Asynchronous Transf
An example in which the present invention is applied to a signal processing circuit of the er Mode (hereinafter, AMT25) standard will be described with reference to FIGS. 1, 2, 3, 4, and 5. FIG.

FIG. 1 is a block diagram of one embodiment, FIG. 2 is a timing chart showing the operation of this embodiment, and FIG.
5 is an explanatory diagram showing a cell format as a unit of data transfer, FIG. 4 is an explanatory diagram of a HEADER portion of the cell shown in FIG. 3, and FIG. 5 is a block diagram of the signal processing circuit shown in FIG.

In FIG. 1, 1 is a reception signal input terminal, 2 is an equalization circuit, 3 is output data whose waveform has been equalized by the equalization circuit 2, 4 is a signal processing circuit, 5 is a data output terminal, and 6 is a data output terminal. A valid cell detection signal, 7 is an out-of-phase detection circuit, 8 is an interval timer, 9 is an interval timer output signal, 10
Is a delay circuit, 11 is an R-SFF, 12 is a NAND circuit,
13 is an out-of-phase detection signal, 14 is a crystal oscillator, 15
Is a PLL, 16 is a phase comparison circuit, 17 is a frequency comparison circuit, 18 is a selector, 19 is a PLL mode control circuit, 2
Reference numeral 0 denotes a charge pump, reference numeral 21 denotes a loop filter, reference numeral 22 denotes a voltage-controlled oscillation circuit (hereinafter, VCO), and reference numeral 23 denotes a clock signal.

The received signal input from the received signal input terminal 1 is compensated for waveform deterioration due to the signal transmission path by the equalizing circuit 2, and is converted into 1/0 binary data by a predetermined threshold value judgment process. You. The output data 3 of the equalizer 2 is supplied to the signal processor 4 and the PLL 15.

The signal processing circuit 4 performs a predetermined data decoding process on the output data 3 and outputs the data to a data output terminal 5. In addition, a valid cell is detected in the course of data decoding, and a valid cell detection signal 6 is output.

The PLL 15 receives the output data 3 of the equalizer circuit and the output signal of the crystal oscillator 14 and generates a clock signal 23. The phase comparison circuit 16 generates an error signal corresponding to the phase difference between the output data 3 of the equalization circuit and the clock signal 23 generated by the VCO 22. Further, the frequency comparison circuit 17 outputs the output signal of the crystal oscillator 14 and the VCO 22
Generates an error signal corresponding to the frequency difference from the clock signal 23 generated in step (1). The selector 18 is switched by the PLL mode control circuit 19, selects an output error signal of the frequency comparison circuit 17 when a reception signal is not input, and during a predetermined period at the time of startup, and supplies the output error signal to the charge pump 20. The charge pump 20 includes a current source and a switch, and charges and discharges the loop filter 21 according to the error signal. The loop filter 21 converts the charge / discharge current by the charge pump into a change in voltage and supplies the change to the VCO 22. The VCO 22 generates a clock signal 23 having an oscillation frequency according to the output voltage of the loop filter 21. By repeating the above process, the oscillation frequency of the VCO 22 matches the frequency of the crystal oscillator. This process of matching the two frequencies is called a frequency comparison mode.

After matching the oscillation frequency of the crystal oscillator 14 with the oscillation frequency of the VCO 22 in the frequency comparison mode, the selector 18 is switched to select the output signal of the phase comparison circuit 16. The output signal of the phase comparison circuit 16 is the output data 3 of the equalization circuit and the clock signal 23 generated by the VCO.
Corresponds to the phase difference between the clock signal 23 and the phase of the clock signal 23 generated by the VCO.
To follow the phase of This process of matching both phases is called a phase comparison mode.

Here, noise or the like is added to the input signal, and P
Consider a case where the LL loses phase synchronization. In general, on a magnetic disk or the like, data is divided into sectors each having a predetermined number of bytes, and a fixed pattern for synchronizing the PLL is recorded at the beginning of each sector. Phase synchronization can be restored at the beginning of the sector. On the other hand, in the ATM 25, since the data sequence transmitted on the line is converted into random data by signal processing at the time of transmission, once the phase is out of synchronization, the data used as a reference for phase comparison and the edge of the clock signal are defined. And it becomes difficult to recover synchronization,
In the worst case, subsequent data will not be decoded normally. Therefore, means for detecting the loss of phase synchronization of the PLL and performing resynchronization is required.

The out-of-phase detection circuit 7 equivalently determines the phase synchronization state of the PLL by monitoring the data reception status, and generates the out-of-phase detection signal 13. Hereinafter, the operation of the out-of-phase detection circuit 7 will be described.

The interval timer 8 generates an output signal 9 at a predetermined cycle, and outputs a delay circuit 10 and a NAND circuit 12
Supply to The interval timer output signal 9 delayed for a predetermined time by the delay circuit 10 is supplied to the set terminal of the R-SFF 11, and changes the output of the R-SFF to a high level. On the other hand, the valid cell detection signal 6 generated by the signal processing circuit 4 is supplied to the reset terminal of the R-SFF,
Set the output of the FF to low level. The NAND circuit 12
The NAND operation of the interval timer output signal 9 and the output signal of the R-SFF 11 is performed, and the out-of-phase detection signal 13 is generated. The PLL mode control circuit 19 switches the operation mode of the PLL to the frequency comparison mode for a predetermined time in response to the input of the out-of-phase detection signal 13, and resynchronizes the PLL.

The operation described above will be described with reference to a timing chart shown in FIG. As shown in the figure, the interval timer output signal 9 is generated at a predetermined cycle (Tint), and after being delayed by a predetermined time by the delay circuit 10, the R-S
FF11 is set to high level. On the other hand, when the valid cell detection signal 6 is generated by the signal processing circuit 4, R-
SFF is reset to a low level. Therefore, Tin
When a valid cell is detected during the period t, the output of the NAND circuit 12 remains at the high level because the R-SFF output at the timing of the next interval timer output signal is at the low level. 13 is not generated, and the PLL mode control circuit 19 continues to select the phase comparison mode. If no valid cell is detected during the Tint period, the R-SFF 11 is not reset, and the R-SFF output at the timing of the next interval timer output signal remains at the high level.
The output of the NAND circuit becomes low, and the out-of-phase detection signal 13 is generated. When the out-of-phase detection signal 13 is generated, the PLL mode control circuit 19 switches the PLL mode to the frequency comparison mode for a predetermined period,
The oscillation frequency of No. 2 is made to match the oscillation frequency of the crystal oscillator 14. After that, the PLL mode is switched to the phase comparison mode, and the phase of the clock signal 23 generated by the VCO 22 is made to match the phase of the output data 3 of the equalizer circuit. Therefore, even if the PLL is out of synchronization due to the influence of noise or the like during data reception, in the worst case, the PLL can be restored after the time specified by Tint.

Next, a method of detecting a valid cell in the signal processing circuit 4 will be described with reference to FIGS. 3, 4 and 5. FIG.

FIG. 3 is an explanatory diagram showing the format of a cell as a data transfer unit in the ATM 25. As shown in the figure, one cell is composed of 53 bytes of data, of which the first 5 bytes are HEADER indicating the ID of each cell and the following 48 bytes are PAYL.
This is user data called OAD.

FIG. 4 is an explanatory diagram of HEADER. As shown in the figure, the HEADER is mainly composed of a VPI, a VCI indicating a cell address, and a HEC used for detecting a transmission error of the HEADER. HEC is a CRC code for the first 4 bytes of the 5-byte HEADER data, and is generated based on a predetermined generating polynomial in signal processing on the transmission side.

FIG. 5 is a diagram showing a block configuration of the signal processing circuit 4. As shown in FIG. As shown in FIG.
The circuit comprises an RZI demodulation circuit 24, a 4B5B decoding circuit 25, a descramble circuit 26 and an HEC decoding circuit 27, and operates using a clock signal 23 generated by a PLL as a reference clock.

The equalizer circuit output data 3 is subjected to predetermined signal processing by an NRZI demodulator circuit 24, 4B5B decoder circuit 25 and descrambler circuit 26, and is supplied to an HEC decoder circuit 27. The HEC decoding circuit 27 detects whether an error has occurred in the HEADER of the cell subjected to each signal processing. Error detection is performed using a 5-byte HEADE using the same generator polynomial as the generator polynomial used when generating the HEC.
This is performed by dividing the R data. As a result of the division,
If the remainder is “0”, it indicates that no error has occurred in the HEADER data, and the HEC decoding circuit 27 generates a valid cell detection signal 6. On the other hand, as a result of division,
If it is not 0 ′, it indicates that an error has occurred in the HEADER data, and the HEC decoding circuit 27 does not generate the valid cell detection signal 6.

As described above, by monitoring whether or not a valid cell is detected at a predetermined cycle, it becomes possible to equivalently detect the loss of synchronization of the PLL and perform the synchronization recovery processing. The interval timer described in the present embodiment is not particularly limited as long as it generates an output signal at a predetermined cycle. The use of a multivibrator or a counter that operates with an output clock of a crystal oscillator or a clock divided by 1 / n (n is an integer) has no problem and does not impair the essence of the present invention.

Next, an example in which another configuration is used as the out-of-phase detection circuit 7 in the present invention will be described with reference to FIGS.
This will be described below.

FIG. 6 is a diagram showing the configuration of the out-of-phase detecting circuit 7 in this embodiment, and FIG.
6 is a timing chart showing an example of the operation of FIG.

In FIG. 6, 28 is a system controller, 2
9 is a register for performing a data interface with the system controller 28, 30 is a rising edge detection circuit, 31 is an R-SFF, 32 is a 3-input NAND circuit, 3
3 is output data of the system controller 28, 34 is a data write pulse, 35 is a clock synchronized with the output signal of the system controller 28, 36 is output data of the register 29, 37 is an output signal of the rising edge detection circuit 30, and 38 is R -An output signal of the SFF 31.

The system controller 28 controls the clock 3
5, the data 33 and the data write pulse 34 are generated, and "1" is written to the register 29 at a predetermined cycle. Since the initial value of the register 29 is "0", the register output data 36 is "1" from the system controller.
Changes to '1' when is written. The rising edge detection circuit 30 detects a rising edge of the register output signal 36 and generates an output signal 37. The output signal 37 of the rising edge detection circuit is supplied to the register 29 and the R-SFF 31. The register 29 is cleared by the output signal 37 of the rising edge detection circuit. The R-SFF 31 is set by the rising edge detection circuit output signal 37, and the output signal 38 of the R-SFF changes to "1".

Here, the operation in the case where a valid cell is received by the signal processing circuit 4 and the valid cell detection signal 6 is generated will be described. When the valid cell detection signal 6 is input, the R-SFF is reset, and the output signal 38 of the R-SFF changes to “0”. As a result, when the system controller 28 writes “1” to the register 29 after a predetermined period, the output signal 38 of the R-SFF of the input signals of the three-input NAND circuit 32 is “0”.
The output of the AND circuit 32 remains “1” and the out-of-phase detection signal 13 is not generated.

Next, the operation when the valid cell is not received by the signal processing circuit 4 and the valid cell detection signal 6 is not generated will be described. When the valid cell detection signal 6 is not input, the R-SFF remains set by the output signal 37 of the rising edge detection circuit and the R-SFF
The output signal 38 of the FF holds “1”. As a result, after a predetermined period, the system controller 28 sends the register 29
At the time of writing “1” to the 3-input NAND circuit 3
Since all the input signals of 2 become “1”, a 3-input NAND
The output of the circuit 32 changes to '0', and the out-of-phase detection signal 13 is generated.

This operation will be described with reference to the timing chart shown in FIG. FIG. 7A shows an operation in a case where a valid cell is not received by the signal processing circuit 4 and the valid cell detection signal 6 is not generated, and FIG. Are received and the valid cell detection signal 6 is generated.

As shown in FIG. 7A, at times T1 and T
In step 2, the system controller 28 writes data '1' to the register 29 in accordance with the output data 33 of the system controller, the data write pulse 34, and the clock 35. Thus, the output signal 36 of the register becomes the time T
It changes from '0' to '1' at 1 and T2. The rising edge detection circuit 30 detects a rising edge of the register output signal 36 and generates an output signal 37. The output signal 37 of the rising edge detection circuit is supplied to the register 29 and the R-SFF 31 to clear the register 29 and set the output signal 36 of the register to "0",
Set the FF 31 and set the output signal 38 of the R-SFF to “1”.
To change. Here, no valid cell is received between time T1 and T2, and no valid cell detection signal 6 is generated, so that the R-SFF 31 is not reset and the output signal 38 of the R-SFF holds “1”. As a result, at time T2
Therefore, when data "1" is written from the system controller 28 to the register 29, all the input signals of the three-input NAND circuit 32 become "1", so that the output signal of the three-input NAND circuit 32 becomes "0", An out-of-sync detection signal 13 is generated.

On the other hand, as shown in FIG. 7B, when a valid cell is received from time T1 to T2 and a valid cell detection signal 6 is generated, the R-SFF 31 is reset by the valid cell detection signal 6. And the output signal 38 becomes '0'. As a result, at the time point when data “1” is written from the system controller 28 to the register 29 at time T2,
Since the output signal 38 of the R-SFF among the input signals of the 3-input NAND circuit 32 is “0”, the 3-input NAN
The output signal of the D circuit remains “1”, and the out-of-phase detection signal 13 is not generated.

As described above, data "1" is written to the register 29 by the system controller 28 at predetermined intervals, and when a valid cell is received within the period, the out-of-phase detection signal 13 is not generated. , When no valid cell is detected within the period, the out-of-phase detection signal 13 is generated. When the out-of-phase detection signal 13 is generated, the PLL mode control circuit 19 temporarily switches the operation mode of the PLL from the phase comparison mode to the frequency comparison mode.
Control is performed so that LL is pulled in quickly.

Thus, even if the PLL loses phase synchronization due to disturbance such as noise or jitter in the input signal, phase loss can be detected equivalently by monitoring the reception status of the normal cell. , And PLL synchronization recovery can be performed.

In this embodiment, the case where the PLL control system of the present invention is applied to the signal processing circuit of the ATM 25 has been described. Of course, the same effects can be obtained when the present invention is applied to a digital data processing device of another standard. It is possible,
It does not impair the essence of the invention.

[0036]

According to the PLL control method of the present invention, in a PLL that performs phase synchronization with random data, even if the phase synchronization is lost due to disturbance such as noise or jitter in a received signal, the normal cell can be synchronized. Loss of phase synchronization can be detected by constantly monitoring the reception status, and PLL phase synchronization can be restored.

[Brief description of the drawings]

FIG. 1 is a block diagram of an out-of-phase detection circuit and a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of the operation of the embodiment whose configuration is shown in FIG.

FIG. 3 is an explanatory diagram of a cell which is a unit of data transfer in the ATM 25.

FIG. 4 is an explanatory diagram of a HEADER section of the cell shown in FIG. 3;

FIG. 5 is a block diagram of the signal processing circuit shown in FIG. 1;

FIG. 6 is a block diagram of an out-of-phase detection circuit according to another embodiment of the present invention.

7 is a timing chart showing an example of the operation of the out-of-phase detection circuit having the configuration shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Reception signal input terminal, 2 ... Equalization circuit, 3 ... Equalization circuit output data, 4 ... Signal processing circuit, 5 ... Data output terminal, 6 ... Effective cell detection signal, 7 ... Out of phase synchronization detection circuit, 8 ... Interval timer, 9: interval timer output signal, 10: delay circuit, 11: R-SFF, 12: NAND circuit, 13: out-of-phase detection signal, 14: crystal oscillator, 15: PLL circuit, 16: phase comparison circuit, 17: frequency comparison circuit, 18: selector, 19: PLL mode control circuit, 20: charge pump, 21: loop filter, 22: VCO, 23: clock signal.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Eizo Hakata 810 Shimoimaizumi, Ebina-shi, Kanagawa Prefecture Hitachi Systems Office Systems Division

Claims (3)

[Claims] A signal processing circuit for reproducing a signal from a signal transmission path or a signal recording medium; and a phase locked loop circuit for generating a clock signal synchronized with the reproduced signal. And a phase locked loop control circuit comprising an interval timer, a delay circuit for delaying an output signal of the interval timer for a predetermined time, a set / reset flip-flop, and a phase out-of-synchronization detection circuit comprising a NAND circuit. method. 2. The interval timer generates an output signal at a predetermined cycle, and the set / reset flip-flop sets an output level to high or an output level according to an output signal of the interval timer delayed by a predetermined time by the delay circuit. The output level is reset to low by an effective cell detection signal output from the signal processing circuit,
The ND circuit is configured to output the NAN of the output signal of the interval timer and the output signal of the set / reset flip-flop.
2. A phase-out-of-phase detection signal is generated by a D operation.
3. The phase-locked loop control method according to 1. 3. The phase-locked loop control method according to claim 2, wherein the phase-locked loop mode control circuit switches the operation mode of the phase-locked loop to a frequency comparison mode for a predetermined period according to the out-of-phase detection signal.