US20010005164A1 - Clock recovery circuit - Google Patents
Clock recovery circuit Download PDFInfo
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- US20010005164A1 US20010005164A1 US09/734,183 US73418300A US2001005164A1 US 20010005164 A1 US20010005164 A1 US 20010005164A1 US 73418300 A US73418300 A US 73418300A US 2001005164 A1 US2001005164 A1 US 2001005164A1
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- 238000011084 recovery Methods 0.000 title claims description 37
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 238000005070 sampling Methods 0.000 claims description 6
- 238000009499 grossing Methods 0.000 claims description 4
- 238000013139 quantization Methods 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 18
- 230000003213 activating effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
Definitions
- the present invention relates to a clock recovery circuit for reproducing a clock signal synchronized with an input signal quantized to a digital value from the input signal.
- a clock recovery circuit in a digital system includes a phase comparator, a loop filter, a D/A converter and a VFO (variable frequency oscillator).
- the VFO generates an oscillating clock signal of a variable frequency under control of an analog voltage.
- the phase comparator computes a digital value representing a phase error of the oscillating clock signal with respect to an input signal quantized to a digital value and outputs a phase error signal in a digital system as described, for example, in K. H. Mueller et al., “Timing Recovery in Digital Synchronous Data Receivers”, IEEE Transactions on Communications, Vol. COM-24, No. 5, pp. 516-531, May 1976.
- the loop filter is a circuit block for smoothing a digital output from the phase comparator and outputting the smoothed digital output.
- the D/A converter converts the digital output from the loop filter to an analog voltage so as to control generation of the oscillating clock signal so that the phase error is zero, and supplies the analog voltage to the VFO.
- FIG. 17 shows an example of the configuration of a conventional loop filter.
- reference numeral 31 and 32 denote first and second constant multipliers
- reference numeral 34 denotes an accumulator
- reference numeral 35 denotes an adder.
- the first constant multiplier 31 outputs a result obtained by multiplying a phase error signal E output from the phase comparator by a constant filter coefficient ⁇ .
- the second constant multiplier 32 outputs a result obtained by multiplying the phase error signal E by a constant filter coefficient ⁇ ( ⁇ ).
- the accumulator 34 outputs a result obtained by accumulating outputs H from the second constant multiplier 32 , and includes an adder 91 and a latch 92 .
- the adder 35 adds an output G from the first constant multiplier 31 and an output Y from the accumulator 34 .
- a digital value representing the result of this addition namely, a filter output Z, is supplied to the VFO via the D/A converter.
- FIG. 18 shows an example of a waveform of each portion of the loop filter of FIG. 17 when the clock recovery circuit is operated.
- a frequency pull-in operation is performed for a period during which a frequency error is contained in an oscillating clock signal of the VFO.
- a phase pull-in operation is started.
- a frequency pull-in is completed and a phase pull-in operation is started in cycle 7 , and the phase pull-in is completed in cycle 46 .
- E 14 (constant)
- the unit of these examples of the values is arbitrary.
- a first clock recovery circuit of the present invention includes a loop filter including first and second multipliers for multiplying a digital output from a phase comparator by respective filter coefficients and outputting the results; a control signal generating portion for outputting a control signal at the time when completion of frequency pull-in is detected based on the digital output from the phase comparator; an enable-provided latch for outputting a constant value 0 for a period during which the control signal is not output, and after the control signal is output, storing the output from the first multiplier at the time when the control signal is output, and outputting the same; an accumulator for accumulating outputs from the second multiplier and outputting a result; and an adder for supplying a digital value representing a result of addition of the output from the first multiplier, the output from the enable-provided latch, and the output from the accumulator as a filter output, wherein a phase pull-in operation is started using the stored value of the output from the first multiplier at the time of completion
- the first clock recovery circuit since the output from the enable-provided latch is 0 during the frequency pull-in operation, the sum of the output from the first multiplier and the output from the accumulator is the filter output as in the conventional example.
- the output from the first multiplier at the time of completion of the frequency pull-in is stored in the enable-provided latch.
- a phase pull-in operation is started in the state where a frequency correction component is stored collectively in the latch that is discrete from the accumulator. Then, during a phase pull-in operation, the sum of the output from the first multiplier, the output from the enable-provided latch, and the output from the accumulator is the filter output. Therefore, high speed phase pull-in can be attained.
- a second clock recovery circuit includes a loop filter including a control signal generating portion for outputting a control signal at the time when completion of frequency pull-in is detected based on the digital output from the phase comparator; a multiplier for outputting a result obtained by multiplying the digital output from the phase comparator by a first filter coefficient for a period during which the control signal is not output, and after the control signal is output, multiplying the digital output from the phase comparator by a second filter coefficient; an enable-provided accumulator for accumulating a constant value 0 for a period during which the control signal is not output, and accumulating outputs from the multiplier after the control signal is output and outputting a result; and an adder for supplying a digital value representing a result of addition of the output from the multiplier and the output of the enable-provided accumulator as a filter output, wherein a phase pull-in operation is started using a stored value of the output from the multiplier at the time of completion of the frequency pull-in.
- the filter output depends only on the output from the multiplier having a first filter coefficient as the multiplier factor.
- the output from the multiplier at the time of completion of the frequency pull-in is stored in the enable-provided accumulator and accumulation is started.
- a phase pull-in operation is started in the state where a frequency correction component is stored collectively in the enable-provided accumulator.
- the sum of the output from the multiplier having a second filter coefficient as the multiplier factor and the output from the enable-provided accumulator is the filter output. Therefore, high speed phase pull-in can be attained.
- the present invention can provide a clock recovery circuit that can achieve high speed phase pull-in by using a loop filter having an enable-provided latch or an enable-provided accumulator, and starting a phase pull-in operation using the stored value of the output from the multiplier at the time of completion of the frequency pull-in.
- FIG. 1 is a block diagram showing an example of the configuration of a reproduction system signal processing circuit in a data recording/reproducing apparatus utilizing a clock recovery circuit according to the present invention.
- FIG. 2 is a block diagram showing an example of the configuration of the clock recovery circuit in FIG. 1.
- FIG. 3 is a block diagram showing a first example of the configuration of the loop filter in FIG. 2.
- FIG. 4 is a circuit diagram showing the control signal generating portion in FIG. 3 in detail.
- FIG. 5 is a timing chart diagram showing an example of the operation of the control signal generating portion in FIG. 4.
- FIG. 6 is a block diagram showing a second example of the configuration of the loop filter in FIG. 2.
- FIG. 7 is a waveform diagram showing an example of the operation of the loop filter in FIG. 6.
- FIG. 8 is a block diagram showing a third example of the configuration of the loop filter in FIG. 2.
- FIG. 9 is a circuit diagram showing the multiplier-factor-variable multiplier in FIG. 8 in detail.
- FIG. 10 is a block diagram showing a fourth example of the configuration of the loop filter in FIG. 2.
- FIG. 11 is a circuit diagram showing the control signal generating portion in FIG. 10 in detail.
- FIG. 12 is a circuit diagram showing the enable-provided accumulator in FIG. 10 in detail.
- FIG. 13 is a block diagram showing a fifth example of the configuration of the loop filter in FIG. 2.
- FIG. 14 is a circuit diagram showing the control signal generating portion in FIG. 13 in detail.
- FIG. 15 is a block diagram showing a sixth example of the configuration of the loop filter in FIG. 2.
- FIG. 16 is a circuit diagram showing the control signal generating portion in FIG. 15 in detail.
- FIG. 17 is a block diagram showing an example of the configuration of a conventional loop filter.
- FIG. 18 is a waveform diagram showing an example of the operation of the loop filter of FIG. 17.
- FIG. 1 shows an example of the configuration of a reproducing system signal processing circuit in a data recording/reproducing apparatus utilizing a clock recovery circuit according to the present invention.
- reference numeral 10 denotes a recording medium
- reference numeral 11 denotes a head
- reference numeral 12 denotes an AGC circuit for amplitude correction of a reproduction signal
- reference numeral 13 denotes a waveform equalizer
- reference numeral 14 denotes an A/D converter
- reference numeral 15 denotes a correction circuit for waveform correction in the digital manner
- reference numeral 16 denotes a Viterbi decoder
- reference numeral 17 denotes a clock recovery circuit according to the present invention.
- a data signal recorded in the recording medium 10 is converted to an analog reproduction signal by the head 11 .
- the amplitude of this reproduction signal is corrected by the AGC circuit 12 , and then the reproduction signal is subjected to waveform equalization processing corresponding to the characteristics of the Viterbi decoder 16 by the waveform equalizer 13 .
- the waveform-equalized reproduction signal is quantized by the A/D converter 14 , waveform corrected in the digital manner by the correction circuit 15 , and then converted to decoded data by the Viterbi decoder 16 .
- the reproduction signal quantized by the A/D converter 14 is input also to the clock recovery circuit 17 .
- the clock recovery circuit 17 recovers a clock signal synchronized with this input signal from the input signal.
- An output clock (recovered clock) from the clock recovery circuit 17 is used as a sampling clock for quantization in the A/D converter 14 , and used as a system clock in digital portions such as the correction circuit 15 , the Viterbi decoder 16 or the like.
- FIG. 2 shows an example of the configuration of the clock recovery circuit 17 in FIG. 1.
- reference numeral 20 denotes a phase comparator
- reference numeral 21 denotes a loop filter
- reference numeral 22 denotes a D/A converter
- reference numeral 23 denotes a VFO (variable frequency oscillator).
- the VFO 23 generates an oscillating clock signal of a variable frequency under control of an analog voltage.
- the phase comparator 20 computes a digital value representing a phase error of the oscillating clock signal (sampling clock) with respect to an output signal (output sample) from the A/D converter 14 .
- the loop filter 21 is a circuit block for smoothing the digital output from the phase comparator 20 , namely, a phase error signal E, and outputting the smoothed signal.
- the D/A converter 22 converts the digital output Z from the loop filter 21 to an analog voltage so as to control generation of the oscillating clock signal so that the phase error is zero, and supplies the analog voltage to the VFO 23 .
- the oscillating clock signal from the VFO 23 is also used as a clock signal for synchronous operation of the loop filter 21 and the D/A converter 22 .
- FIG. 3 shows a first configuration example of the loop filter 21 in the FIG. 2.
- reference numeral 30 denotes a control signal generating portion
- reference numerals 31 and 32 denote first and second constant multipliers
- reference numeral 33 denotes an enable-provided latch
- reference numeral 34 denotes an accumulator
- reference numeral 35 denotes is an adder.
- the control signal generating portion 30 outputs a pulse at Hi (high) level as a control signal F for one clock cycle at the time when the completion of frequency pull-in is detected based on a phase error signal E output from the phase comparator 20 .
- the first constant multiplier 31 outputs a result obtained by multiplying the phase error signal E by a constant filter coefficient ⁇ .
- the second constant multiplier 32 outputs a result obtained by multiplying the phase error signal E by a constant filter coefficient ⁇ ( ⁇ ).
- the enable-provided latch 33 outputs a constant value 0 for a period during which the control signal F is not output, and after the control signal F is output, the enable-provided latch 33 stores the output G from the first constant multiplier 31 at the time when the control signal F is output, and outputs the same.
- the accumulator 34 outputs a result obtained by accumulating outputs H from the second constant multiplier 32 .
- the adder 35 adds an output G from the first constant multiplier 31 , an output X from the enable-provided latch 33 and an output Y from the accumulator 34 .
- a digital value representing the result of this addition namely, a filter output Z, is supplied to the VFO 23 via the D/A converter 22 .
- the filter coefficient ⁇ of the second constant multiplier 32 is set to sufficiently small, relative to the filter coefficient ⁇ of the first constant multiplier 31 for stable operation of the clock reproduction system.
- the oscillating clock signal of the VFO 23 in the initial state contains not only a phase error but also a frequency error.
- a frequency error is contained in a sampling clock of the A/D converter 14 , the sampling point of the A/D converter 14 shifts.
- the clock recovery circuit 17 in FIG. 2 first performs a frequency pull-in operation.
- the control signal F output from the control signal generating portion 30 is at the Lo (low) level, so that the output X from the enable-provided latch 33 is 0.
- the filter output Z is expressed by:
- the enable-provided latch 33 stores the frequency correction component ⁇ E(k) in response to the control signal F and outputs the same. From this point, a phase pull-in operation is started.
- phase pull-in operation is started, using the frequency correction component collectively stored in the enable-provided latch 33 , which is discrete from the accumulator 34 , so that high-speed phase pull-in can be attained.
- FIG. 4 shows a configuration example of the control signal generating portion 30 in FIG. 3 in detail.
- reference numeral 40 denotes a difference calculator
- reference numeral 50 denotes a window comparator
- reference numeral 60 denotes a counter
- reference numeral 70 denotes a pulse generator.
- the difference calculator 40 calculates a change in the phase error signal E and outputs a phase error difference signal S and includes two latches 41 and 42 and a subtractor 43 .
- the window comparator 50 outputs a count signal T at the Hi level when the difference S of the phase error is in a certain range defined by a positive threshold (TH+) and a negative threshold (TH ⁇ ) and includes two subtractors 51 and 52 , two latches 53 and 54 and a logic gate 55 .
- the counter 60 counts the count signal T at the Hi level supplied from the window comparator 50 .
- the pulse generator 70 generates a pulse signal upon determination that the frequency pull-in has been completed at the time when the output U from the counter 60 reaches a predetermined value, and outputs the generated pulse signal as the control signal F.
- the pulse generator 70 includes a comparator 71 , a latch 72 and a logic gate 73 .
- the output from the comparator 71 that turns to the Hi level when the output U from the counter 60 corresponds to the predetermined value is supplied to the counter 60 as a hold signal.
- the control signal generating portion 30 of FIG. 4 is configured so as to operate in synchronization with the supplied clock signal C.
- FIG. 5 shows an example of the operation of the control signal generating portion 30 of FIG. 4.
- the positive and negative thresholds TH+ and TH ⁇
- the predetermined value of the comparator 71 is 10.
- the control signal generating portion 30 outputs a pulse at the Hi level as the control signal F for one clock cycle upon determination that the frequency pull-in has been completed at the end of consecutive 10 clock cycles during which the difference S of the phase error is ⁇ 1, 0 or +1.
- FIG. 6 shows a second configuration example of the loop filter 21 in the FIG. 2.
- the configuration in FIG. 6 is different from that in FIG. 3 in that a selector 36 is added.
- the selector 36 outputs a constant value 0 for a period during which the control signal F is not output, and after the control singal F is output, the selector 36 supplies the phase error signal E to the second constant multiplier 32 .
- the control signal F output from the control signal generating portion 30 is at the Lo level, so that the output X from the enable-provided latch 33 is 0.
- the selector 36 selects the constant value 0, the output H from the second constant multiplier 32 and thus the output Y from the accumulator 34 are 0 as well. Consequently, assuming that the phase error at an arbitrary time n during the frequency pull-in operation is E(n), the filter output Z is expressed by:
- the enable-provided latch 33 stores the frequency correction component ⁇ E(k) in response to the control signal F and outputs the same.
- the selector 36 starts to supply the phase error signal E to the second constant multiplier 32 . From this point, a phase pull-in operation is started.
- phase pull-in operation is started, using the frequency correction component collectively stored in the enable-provided latch 33 , which is discrete from the accumulator 34 , so that high-speed phase pull-in can be attained.
- FIG. 7 shows an example of a waveform of each portion of the loop filter 21 of FIG. 6 when the clock recovery circuit 17 is operated.
- a frequency pull-in is completed and a phase pull-in operation is started in cycle 13
- the phase pull-in is completed in cycle 30 .
- E 6 (constant)
- the unit of these examples of the values is arbitrary.
- the frequency correction component G in the frequency lock state is turned to the latch output X immediately at the time of the start of the phase pull-in operation. Therefore, although the filter coefficient ⁇ is set to small, the phase pull-in is completed as quick as in 17 clock cycles from the start of the phase pull-in operation. Thus, high-speed pull-in can be attained.
- FIG. 8 shows a third configuration example of the loop filter 21 in the FIG. 2.
- the configuration in FIG. 8 is different from that in FIG. 3 in that the constant multipliers 31 and 32 in FIG. 3 are replaced by the multiplier-factor-variable multipliers 31 a and 32 a.
- the first multiplier-factor-variable multiplier 31 a is configured so as to multiply the phase error signal E by a first filter coefficient ⁇ 1 for a period during which the control signal F is not output, and multiply the phase error signal E by a second filter coefficient ⁇ 2 after the control signal F is output.
- the second multiplier-factor-variable multiplier 32 a is configured so as to multiply the phase error signal E by a first filter coefficient ⁇ 1 for a period during which the control signal F is not output, and multiply the phase error signal E by a second filter coefficient ⁇ 2 after the control signal F is output.
- This configuration makes it possible to set the loop gain for the frequency pull-in independently from the loop gain for the phase pull-in.
- FIG. 9 shows a configuration example of the first multiplier-factor-variable multiplier 31 a in FIG. 8.
- reference numeral 80 denotes a latch for storing the first filter coefficient ⁇ 1 used at the time of the frequency pull-in.
- Reference numeral 81 denotes a latch for storing the second filter coefficient ⁇ 2 used at the time of the phase pull-in.
- Reference numeral 82 denotes a selector for selecting either one of the first and second filter coefficients ⁇ 1 and ⁇ 2 as a multiplier factor in accordance with the control signal F.
- Reference numeral 83 denotes a multiplication unit for multiplying the phase error signal E by the selected multiplier factor.
- the configuration of the second multiplier-factor-variable multiplier 32 a is the same as that of FIG. 9.
- the control signal F output from the control signal generating portion 30 is at the Lo (low) level, so that the output X from the enable-provided latch 33 is 0.
- the multiplier-factor-variable multipliers 31 a and 32 a select the filter coefficients ⁇ 1 and ⁇ 1 , respectively. Consequently, assuming that the phase error at an arbitrary time j during the frequency pull-in operation is E(j), the filter output Z is expressed by:
- the enable-provided latch 33 stores the frequency correction component ⁇ 1 ⁇ E(k) in response to the control signal F and outputs the same.
- the first and second multiplier-factor-variable multipliers 31 a and 32 a select filter coefficients ⁇ 2 and ⁇ 2 , respectively, in response to the control signal F. From this point, a phase pull-in operation is started.
- phase pull-in operation is started, using the frequency correction component ⁇ 1 ⁇ E(k) collectively stored in the enable-provided latch 33 , which is discrete from the accumulator 34 , so that high-speed phase pull-in can be attained.
- FIG. 10 shows a fourth configuration example of the loop filter 21 in the FIG. 2.
- Reference numeral 30 a denotes a control signal generating portion
- reference numeral 31 a denotes a multiplier-factor-variable multiplier
- reference numeral 34 a denotes an enable-provided accumulator
- reference numeral 35 denotes is an adder.
- the control signal generating portion 30 a outputs a pulse at the Hi level as a control signal F for one clock cycle at the time when the completion of frequency pull-in is detected based on a phase error signal E output from the phase comparator 20 .
- the multiplier-factor-variable multiplier 31 a outputs a result obtained by multiplying the phase error signal E by a first filter coefficient ⁇ 1 for a period during which the control signal F is not output, and a result obtained by multiplying the phase error signal E by a second filter coefficient ⁇ 2 after the control signal F is output.
- the enable-provided accumulator 34 a accumulates a constant value 0 for a period during which the control signal F is not output, and after the control signal F is output, accumulates outputs G from the multiplier-factor-variable multiplier 31 a , and outputs a result.
- the adder 35 adds the output G from the multiplier-factor-variable multiplier 31 a and the output Y from the enable-provided accumulator 34 a.
- a digital value representing the result of this addition, namely, a filter output Z, is supplied to the VFO 23 via the D/A converter 22 .
- the control signal F output from the control signal generating portion 30 a is at the Lo level, so that the output Y from the enable-provided accumulator 34 a is 0.
- the filter output Z is expressed by:
- the enable-provided accumulator 34 a stores the frequency correction component ⁇ 1 ⁇ E(k) in response to the control signal F and then starts accumulating. From this point, a phase pull-in operation is started.
- phase pull-in operation is started, using the frequency correction component ⁇ 1 ⁇ E(k) collectively stored in the enable-provided accumulator 34 a , so that high-speed phase pull-in can be attained.
- FIG. 11 shows a configuration example of the control signal generating portion 30 a in FIG. 10 in detail.
- the configuration of FIG. 11 is different from that of FIG. 4 in that the counter 60 in FIG. 4 is replaced by a reset-provided counter 60 a, and a controller 61 is added.
- the controller 61 is means for resetting the count of the counter 60 a to 0 when it is confirmed that frequency pull-in is required again during the phase pull-in operation. Even if a frequency error is generated by, for example external disturbances during the phase pull-in operation, resetting of the counter 60 a by the controller 61 after a predetermined numbers of clock cycles have passed makes it possible to return from the phase pull-in operation to the frequency pull-in operation immediately.
- FIG. 12 shows a configuration example of the enable-provided accumulator 34 a in FIG. 10.
- reference numeral 90 denotes a selector
- reference numeral 91 denotes an adder
- reference numeral 92 denotes a latch.
- the selector 90 supplies a constant value 0 for a period during which the control signal F is not output, and supplies the output G from the multiplier-factor-variable multiplier 31 a after the control signal F is output, to the adder 91 .
- the adder 91 adds the output from the selector 90 and the output from the latch 92 .
- the value stored in the latch 92 is updated to the result of this addition. More specifically, the enable-provided accumulator 34 a in FIG. 12 accumulates only the outputs G from the multiplier-factor-variable multiplier 31 a after the control signal F is output.
- FIG. 13 shows a fifth configuration example of the loop filter 21 in the FIG. 2.
- the configuration in FIG. 13 is different from that of FIG. 10 in that the control signal generating portion 30 a and the multiplier-factor-variable multiplier 31 a in FIG. 10 are provided further with a multiplier factor switching function.
- the control signal generating portion 30 b in FIG. 13 has a function for activating and outputting a multiplier factor switching signal J when a phase inversion is detected from the phase error signal E during the frequency pull-in operation, in addition to a function for outputting a pulse at the Hi level as a control signal F at the time when the completion of frequency pull-in is detected based on the phase error signal E.
- the filter 13 is configured so as to multiply the phase error signal E by a first filter ⁇ 1 for a period during which the control signal F is not output under the condition that the multiplier factor switching signal J is not activated, a second filter coefficient ⁇ 2 after the control signal F is output, and a third filter coefficient ⁇ 3 when the activated multiplier factor switching signal J is received.
- the filter coefficient of the multiplier-factor-variable multiplier 31 b is changed to ⁇ 3 so that the frequency lock is attained.
- FIG. 14 is a configuration example of the control signal generating portion 30 b in FIG. 13 in detail.
- the configuration of FIG. 14 is different from that of FIG. 4 in that a phase inversion detector 65 is added.
- phase inversion occurs, where a phase error from a positive or a negative value having a large absolute value to a negative or a positive value having a large absolute value.
- the frequency error is positive (the oscillating clock frequency of the VFO 23 is too high)
- a phase inversion from negative to positive occurs.
- the frequency error is negative
- a phase inversion from positive to negative occurs.
- the phase inversion detector 65 in FIG. 14 detects such a phase inversion.
- the loop gain is changed by changing the filter coefficient of the multiplier-factor-variable multiplier 31 b in FIG. 13 to ⁇ 3 , and thus the frequency pull-in can be attained reliably.
- FIG. 15 shows a sixth configuration example of the loop filter 21 in the FIG. 2.
- the configuration in FIG. 15 is different from that of FIG. 10 in that the control signal generating portion 30 a and the adder 35 in FIG. 10 are provided further with an offset adjusting function.
- the control signal generating portion 30 c in FIG. 15 has a function for outputting an offset signal K when a phase inversion is detected from the phase error signal E during the frequency pull-in operation, in addition to a function for outputting a pulse at the Hi level as a control signal F at the time when the completion of frequency pull-in is detected based on the phase error signal E.
- the filter 15 adds the output G from the multiplier-factor-variable multiplier 31 a, the output Y from the enable-provided accumulator 34 a, and the offset K from the control signal generating portion 30 c.
- the digital value representing the result of this addition is the filter output Z.
- FIG. 16 is a configuration example of the control signal generating portion 30 c in FIG. 15 in detail.
- the configuration of FIG. 16 is different from that of FIG. 4 in that a phase inversion detector 65 and an offset generating circuit 66 are added.
- the phase inversion detector 65 detects a phase inversion from the phase error signal E.
- the offset generating circuit 66 supplies the offset signal K to the adder 35 , and thus the frequency pull-in can be attained reliably.
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Abstract
Description
- The present invention relates to a clock recovery circuit for reproducing a clock signal synchronized with an input signal quantized to a digital value from the input signal.
- In a data reproducing apparatus for decoding a data signal recorded in a recording medium such as an optical disk and a magnetic disk, in order to identify a reproduction signal from the recording medium as data, it is necessary to recover a clock signal synchronized with this reproduction signal from the reproduction signal.
- In general, a clock recovery circuit in a digital system includes a phase comparator, a loop filter, a D/A converter and a VFO (variable frequency oscillator). The VFO generates an oscillating clock signal of a variable frequency under control of an analog voltage. The phase comparator computes a digital value representing a phase error of the oscillating clock signal with respect to an input signal quantized to a digital value and outputs a phase error signal in a digital system as described, for example, in K. H. Mueller et al., “Timing Recovery in Digital Synchronous Data Receivers”, IEEE Transactions on Communications, Vol. COM-24, No. 5, pp. 516-531, May 1976. The loop filter is a circuit block for smoothing a digital output from the phase comparator and outputting the smoothed digital output. The D/A converter converts the digital output from the loop filter to an analog voltage so as to control generation of the oscillating clock signal so that the phase error is zero, and supplies the analog voltage to the VFO.
- FIG. 17 shows an example of the configuration of a conventional loop filter. In FIG. 17,
reference numeral reference numeral 34 denotes an accumulator, andreference numeral 35 denotes an adder. The first constant multiplier 31 outputs a result obtained by multiplying a phase error signal E output from the phase comparator by a constant filter coefficient α. The second constant multiplier 32 outputs a result obtained by multiplying the phase error signal E by a constant filter coefficient β (<α). Theaccumulator 34 outputs a result obtained by accumulating outputs H from the secondconstant multiplier 32, and includes anadder 91 and alatch 92. Theadder 35 adds an output G from the firstconstant multiplier 31 and an output Y from theaccumulator 34. A digital value representing the result of this addition, namely, a filter output Z, is supplied to the VFO via the D/A converter. - FIG. 18 shows an example of a waveform of each portion of the loop filter of FIG. 17 when the clock recovery circuit is operated. A frequency pull-in operation is performed for a period during which a frequency error is contained in an oscillating clock signal of the VFO. When the frequency pull-in is completed, a phase pull-in operation is started. In the example of FIG. 18, a frequency pull-in is completed and a phase pull-in operation is started in
cycle 7, and the phase pull-in is completed in cycle 46. In the frequency lock state aroundcycle 7, E=14 (constant), and G=5, Y=1, and Z=6. The output G (=5) from thefirst multiplier 31 represents a frequency correction component. In the phase lock state after cycle 46, E=0, and G=0, Y=4, and Z=4. In this case, the unit of these examples of the values is arbitrary. - According to the conventional loop filter shown in FIG. 17, during a period from the start of the phase pull-in operation to the completion of the phase pull-in, a main portion of the filter output Z (=G+Y) has to shift from the output G from the
first multiplier 31 to the output Y from theaccumulator 34. In the specific example of FIG. 18, during this period, the output G from thefirst multiplier 31 changes from 5 to 0, whereas the output Y from theaccumulator 34 changes 1 to 4. However, since the filter coefficient β is set to small for stable operation of the clock recovery circuit, the change of the output Y from theaccumulator 34 is slow. Therefore, in the example of FIG. 18, the start of the phase pull-in operation to the completion of the pull-in takes as long a time as 39 clock cycles. - It is an object of the present invention to provide a clock recovery circuit that can achieve high-speed phase pull-in.
- In order to achieve this object, a first clock recovery circuit of the present invention includes a loop filter including first and second multipliers for multiplying a digital output from a phase comparator by respective filter coefficients and outputting the results; a control signal generating portion for outputting a control signal at the time when completion of frequency pull-in is detected based on the digital output from the phase comparator; an enable-provided latch for outputting a
constant value 0 for a period during which the control signal is not output, and after the control signal is output, storing the output from the first multiplier at the time when the control signal is output, and outputting the same; an accumulator for accumulating outputs from the second multiplier and outputting a result; and an adder for supplying a digital value representing a result of addition of the output from the first multiplier, the output from the enable-provided latch, and the output from the accumulator as a filter output, wherein a phase pull-in operation is started using the stored value of the output from the first multiplier at the time of completion of the frequency pull-in. - According to the first clock recovery circuit, since the output from the enable-provided latch is 0 during the frequency pull-in operation, the sum of the output from the first multiplier and the output from the accumulator is the filter output as in the conventional example. However, when frequency pull-in is completed, and a frequency lock state is reached, the output from the first multiplier at the time of completion of the frequency pull-in is stored in the enable-provided latch. Thus, a phase pull-in operation is started in the state where a frequency correction component is stored collectively in the latch that is discrete from the accumulator. Then, during a phase pull-in operation, the sum of the output from the first multiplier, the output from the enable-provided latch, and the output from the accumulator is the filter output. Therefore, high speed phase pull-in can be attained.
- A second clock recovery circuit includes a loop filter including a control signal generating portion for outputting a control signal at the time when completion of frequency pull-in is detected based on the digital output from the phase comparator; a multiplier for outputting a result obtained by multiplying the digital output from the phase comparator by a first filter coefficient for a period during which the control signal is not output, and after the control signal is output, multiplying the digital output from the phase comparator by a second filter coefficient; an enable-provided accumulator for accumulating a
constant value 0 for a period during which the control signal is not output, and accumulating outputs from the multiplier after the control signal is output and outputting a result; and an adder for supplying a digital value representing a result of addition of the output from the multiplier and the output of the enable-provided accumulator as a filter output, wherein a phase pull-in operation is started using a stored value of the output from the multiplier at the time of completion of the frequency pull-in. - According to the second clock recovery circuit, since the output from the enable-provided accumulator is 0 during the frequency pull-in operation, the filter output depends only on the output from the multiplier having a first filter coefficient as the multiplier factor. When the frequency pull-in is completed and a frequency lock state is reached, the output from the multiplier at the time of completion of the frequency pull-in is stored in the enable-provided accumulator and accumulation is started. Thus, a phase pull-in operation is started in the state where a frequency correction component is stored collectively in the enable-provided accumulator. Then, during a phase pull-in operation, the sum of the output from the multiplier having a second filter coefficient as the multiplier factor and the output from the enable-provided accumulator is the filter output. Therefore, high speed phase pull-in can be attained.
- As described above, the present invention can provide a clock recovery circuit that can achieve high speed phase pull-in by using a loop filter having an enable-provided latch or an enable-provided accumulator, and starting a phase pull-in operation using the stored value of the output from the multiplier at the time of completion of the frequency pull-in.
- This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
- FIG. 1 is a block diagram showing an example of the configuration of a reproduction system signal processing circuit in a data recording/reproducing apparatus utilizing a clock recovery circuit according to the present invention.
- FIG. 2 is a block diagram showing an example of the configuration of the clock recovery circuit in FIG. 1.
- FIG. 3 is a block diagram showing a first example of the configuration of the loop filter in FIG. 2.
- FIG. 4 is a circuit diagram showing the control signal generating portion in FIG. 3 in detail.
- FIG. 5 is a timing chart diagram showing an example of the operation of the control signal generating portion in FIG. 4.
- FIG. 6 is a block diagram showing a second example of the configuration of the loop filter in FIG. 2.
- FIG. 7 is a waveform diagram showing an example of the operation of the loop filter in FIG. 6.
- FIG. 8 is a block diagram showing a third example of the configuration of the loop filter in FIG. 2.
- FIG. 9 is a circuit diagram showing the multiplier-factor-variable multiplier in FIG. 8 in detail.
- FIG. 10 is a block diagram showing a fourth example of the configuration of the loop filter in FIG. 2.
- FIG. 11 is a circuit diagram showing the control signal generating portion in FIG. 10 in detail.
- FIG. 12 is a circuit diagram showing the enable-provided accumulator in FIG. 10 in detail.
- FIG. 13 is a block diagram showing a fifth example of the configuration of the loop filter in FIG. 2.
- FIG. 14 is a circuit diagram showing the control signal generating portion in FIG. 13 in detail.
- FIG. 15 is a block diagram showing a sixth example of the configuration of the loop filter in FIG. 2.
- FIG. 16 is a circuit diagram showing the control signal generating portion in FIG. 15 in detail.
- FIG. 17 is a block diagram showing an example of the configuration of a conventional loop filter.
- FIG. 18 is a waveform diagram showing an example of the operation of the loop filter of FIG. 17.
- Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
- FIG. 1 shows an example of the configuration of a reproducing system signal processing circuit in a data recording/reproducing apparatus utilizing a clock recovery circuit according to the present invention. In FIG. 1,
reference numeral 10 denotes a recording medium,reference numeral 11 denotes a head,reference numeral 12 denotes an AGC circuit for amplitude correction of a reproduction signal,reference numeral 13 denotes a waveform equalizer,reference numeral 14 denotes an A/D converter,reference numeral 15 denotes a correction circuit for waveform correction in the digital manner,reference numeral 16 denotes a Viterbi decoder, andreference numeral 17 denotes a clock recovery circuit according to the present invention. - A data signal recorded in the
recording medium 10 is converted to an analog reproduction signal by thehead 11. The amplitude of this reproduction signal is corrected by theAGC circuit 12, and then the reproduction signal is subjected to waveform equalization processing corresponding to the characteristics of theViterbi decoder 16 by thewaveform equalizer 13. The waveform-equalized reproduction signal is quantized by the A/D converter 14, waveform corrected in the digital manner by thecorrection circuit 15, and then converted to decoded data by theViterbi decoder 16. The reproduction signal quantized by the A/D converter 14 is input also to theclock recovery circuit 17. Theclock recovery circuit 17 recovers a clock signal synchronized with this input signal from the input signal. An output clock (recovered clock) from theclock recovery circuit 17 is used as a sampling clock for quantization in the A/D converter 14, and used as a system clock in digital portions such as thecorrection circuit 15, theViterbi decoder 16 or the like. - FIG. 2 shows an example of the configuration of the
clock recovery circuit 17 in FIG. 1. In FIG. 2,reference numeral 20 denotes a phase comparator,reference numeral 21 denotes a loop filter,reference numeral 22 denotes a D/A converter, andreference numeral 23 denotes a VFO (variable frequency oscillator). TheVFO 23 generates an oscillating clock signal of a variable frequency under control of an analog voltage. Thephase comparator 20 computes a digital value representing a phase error of the oscillating clock signal (sampling clock) with respect to an output signal (output sample) from the A/D converter 14. Theloop filter 21 is a circuit block for smoothing the digital output from thephase comparator 20, namely, a phase error signal E, and outputting the smoothed signal. The D/A converter 22 converts the digital output Z from theloop filter 21 to an analog voltage so as to control generation of the oscillating clock signal so that the phase error is zero, and supplies the analog voltage to theVFO 23. The oscillating clock signal from theVFO 23 is also used as a clock signal for synchronous operation of theloop filter 21 and the D/A converter 22. - Hereinafter, first to sixth examples of the configuration of the
loop filter 21 in the FIG. 2 will be described. - First Configuration Example
- FIG. 3 shows a first configuration example of the
loop filter 21 in the FIG. 2. In FIG. 3,reference numeral 30 denotes a control signal generating portion,reference numerals reference numeral 33 denotes an enable-provided latch,reference numeral 34 denotes an accumulator, andreference numeral 35 denotes is an adder. The controlsignal generating portion 30 outputs a pulse at Hi (high) level as a control signal F for one clock cycle at the time when the completion of frequency pull-in is detected based on a phase error signal E output from thephase comparator 20. The firstconstant multiplier 31 outputs a result obtained by multiplying the phase error signal E by a constant filter coefficient α. The secondconstant multiplier 32 outputs a result obtained by multiplying the phase error signal E by a constant filter coefficient β (<α). The enable-providedlatch 33 outputs aconstant value 0 for a period during which the control signal F is not output, and after the control signal F is output, the enable-providedlatch 33 stores the output G from the firstconstant multiplier 31 at the time when the control signal F is output, and outputs the same. Theaccumulator 34 outputs a result obtained by accumulating outputs H from the secondconstant multiplier 32. Theadder 35 adds an output G from the firstconstant multiplier 31, an output X from the enable-providedlatch 33 and an output Y from theaccumulator 34. A digital value representing the result of this addition, namely, a filter output Z, is supplied to theVFO 23 via the D/A converter 22. The filter coefficient β of the secondconstant multiplier 32 is set to sufficiently small, relative to the filter coefficient α of the firstconstant multiplier 31 for stable operation of the clock reproduction system. - The oscillating clock signal of the
VFO 23 in the initial state contains not only a phase error but also a frequency error. When a frequency error is contained in a sampling clock of the A/D converter 14, the sampling point of the A/D converter 14 shifts. In order to eliminate this phenomenon, theclock recovery circuit 17 in FIG. 2 first performs a frequency pull-in operation. - According to the configuration of FIG. 3, during the frequency pull-in operation, the control signal F output from the control
signal generating portion 30 is at the Lo (low) level, so that the output X from the enable-providedlatch 33 is 0. Assuming that the phase error at an arbitrary time n during the frequency pull-in operation is E(n), the filter output Z is expressed by: - Z=X+G+Y=α×E(n)+Σi−0 n {β×E(i)}
- When the frequency pull-in is completed and the frequency lock state (E=constant) is reached, the control
signal generating portion 30 outputs a pulse at the Hi level as the control signal F. Assuming that the phase error in this frequency lock state is E(k), the output G from the firstconstant multiplier 31 is α×E(k) representing a frequency correction component. The enable-providedlatch 33 stores the frequency correction component α×E(k) in response to the control signal F and outputs the same. From this point, a phase pull-in operation is started. - Assuming that the phase error at an arbitrary time m during the phase pull-in operation is E(m), the filter output Z is expressed by:
- Z=X+G+Y=α×E(k)+α×E(m)+Σi−0 m {β×E(i)}
- In this case, the phase pull-in operation is started, using the frequency correction component collectively stored in the enable-provided
latch 33, which is discrete from theaccumulator 34, so that high-speed phase pull-in can be attained. - FIG. 4 shows a configuration example of the control
signal generating portion 30 in FIG. 3 in detail. In FIG. 4,reference numeral 40 denotes a difference calculator,reference numeral 50 denotes a window comparator,reference numeral 60 denotes a counter, andreference numeral 70 denotes a pulse generator. Thedifference calculator 40 calculates a change in the phase error signal E and outputs a phase error difference signal S and includes twolatches subtractor 43. Thewindow comparator 50 outputs a count signal T at the Hi level when the difference S of the phase error is in a certain range defined by a positive threshold (TH+) and a negative threshold (TH−) and includes twosubtractors latches logic gate 55. The counter 60 counts the count signal T at the Hi level supplied from thewindow comparator 50. Thepulse generator 70 generates a pulse signal upon determination that the frequency pull-in has been completed at the time when the output U from thecounter 60 reaches a predetermined value, and outputs the generated pulse signal as the control signal F. Thepulse generator 70 includes acomparator 71, alatch 72 and alogic gate 73. The output from thecomparator 71 that turns to the Hi level when the output U from thecounter 60 corresponds to the predetermined value is supplied to thecounter 60 as a hold signal. The controlsignal generating portion 30 of FIG. 4 is configured so as to operate in synchronization with the supplied clock signal C. - FIG. 5 shows an example of the operation of the control
signal generating portion 30 of FIG. 4. Herein, it is assumed that the positive and negative thresholds (TH+ and TH−) is +1 and −1, respectively, and the predetermined value of thecomparator 71 is 10. In this case, the controlsignal generating portion 30 outputs a pulse at the Hi level as the control signal F for one clock cycle upon determination that the frequency pull-in has been completed at the end of consecutive 10 clock cycles during which the difference S of the phase error is −1, 0 or +1. - Second Configuration Example
- FIG. 6 shows a second configuration example of the
loop filter 21 in the FIG. 2. The configuration in FIG. 6 is different from that in FIG. 3 in that aselector 36 is added. Theselector 36 outputs aconstant value 0 for a period during which the control signal F is not output, and after the control singal F is output, theselector 36 supplies the phase error signal E to the secondconstant multiplier 32. - According to the configuration of FIG. 6, during the frequency pull-in operation, the control signal F output from the control
signal generating portion 30 is at the Lo level, so that the output X from the enable-providedlatch 33 is 0. In addition, since theselector 36 selects theconstant value 0, the output H from the secondconstant multiplier 32 and thus the output Y from theaccumulator 34 are 0 as well. Consequently, assuming that the phase error at an arbitrary time n during the frequency pull-in operation is E(n), the filter output Z is expressed by: - Z=X+G+Y=α×E(n)
- When the frequency pull-in is completed and the frequency lock state (E=constant) is reached, the control
signal generating portion 30 outputs a pulse at the Hi level as the control signal F. Assuming that the phase error in this frequency lock state is E(k), the output G from the firstconstant multiplier 31 is α×E(k) representing a frequency correction component. The enable-providedlatch 33 stores the frequency correction component α×E(k) in response to the control signal F and outputs the same. On the other hand, theselector 36 starts to supply the phase error signal E to the secondconstant multiplier 32. From this point, a phase pull-in operation is started. - Assuming that the phase error at an arbitrary time m during the phase pull-in operation is E(m), the filter output Z is expressed by:
- Z=X+G+Y=α×E(k)+α×E(m)+Σi=k+1 m {β×E(i)}
- In this case, the phase pull-in operation is started, using the frequency correction component collectively stored in the enable-provided
latch 33, which is discrete from theaccumulator 34, so that high-speed phase pull-in can be attained. - FIG. 7 shows an example of a waveform of each portion of the
loop filter 21 of FIG. 6 when theclock recovery circuit 17 is operated. In this example, a frequency pull-in is completed and a phase pull-in operation is started incycle 13, and the phase pull-in is completed incycle 30. In the frequency lock state aroundcycle 13, E=6 (constant), and G=60, Y=0, X=0 and Z=60. The output G (=60) from thefirst multiplier 31 represents a frequency correction component. In the phase lock state aftercycle 30, E=0, and G=0, Y=0.4, X=60 and Z=60.4. In this case, the unit of these examples of the values is arbitrary. - According to FIG. 7, the frequency correction component G in the frequency lock state is turned to the latch output X immediately at the time of the start of the phase pull-in operation. Therefore, although the filter coefficient β is set to small, the phase pull-in is completed as quick as in 17 clock cycles from the start of the phase pull-in operation. Thus, high-speed pull-in can be attained.
- Third Configuration Example
- FIG. 8 shows a third configuration example of the
loop filter 21 in the FIG. 2. The configuration in FIG. 8 is different from that in FIG. 3 in that theconstant multipliers variable multipliers variable multiplier 31 a is configured so as to multiply the phase error signal E by a first filter coefficient α1 for a period during which the control signal F is not output, and multiply the phase error signal E by a second filter coefficient α2 after the control signal F is output. Similarly, the second multiplier-factor-variable multiplier 32 a is configured so as to multiply the phase error signal E by a first filter coefficient β1 for a period during which the control signal F is not output, and multiply the phase error signal E by a second filter coefficient β2 after the control signal F is output. This configuration makes it possible to set the loop gain for the frequency pull-in independently from the loop gain for the phase pull-in. - FIG. 9 shows a configuration example of the first multiplier-factor-
variable multiplier 31 a in FIG. 8. In FIG. 9,reference numeral 80 denotes a latch for storing the first filter coefficient α1 used at the time of the frequency pull-in.Reference numeral 81 denotes a latch for storing the second filter coefficient α2 used at the time of the phase pull-in.Reference numeral 82 denotes a selector for selecting either one of the first and second filter coefficients α1 and α2 as a multiplier factor in accordance with the control signalF. Reference numeral 83 denotes a multiplication unit for multiplying the phase error signal E by the selected multiplier factor. The configuration of the second multiplier-factor-variable multiplier 32 a is the same as that of FIG. 9. - According to the configuration of FIG. 8, during the frequency pull-in operation, the control signal F output from the control
signal generating portion 30 is at the Lo (low) level, so that the output X from the enable-providedlatch 33 is 0. In addition, the multiplier-factor-variable multipliers - Z=X+G+Y=α1×E(j)+Σn=0 j{β1×E(n)}
- When the frequency pull-in is completed and the frequency lock state (E=constant) is reached, the control
signal generating portion 30 outputs a pulse at the Hi level as the control signal F. Assuming that the phase error in this frequency lock state is E(k), the output G from the first multiplier-factor-variable multiplier 31 a is α1×E(k) representing a frequency correction component. The enable-providedlatch 33 stores the frequency correction component α1×E(k) in response to the control signal F and outputs the same. On the other hand, the first and second multiplier-factor-variable multipliers - Assuming that the phase error at an arbitrary time m during the phase pull-in operation is E(m), the filter output Z is expressed by:
- Z=X+G+Y=α1×E(k)+α2×E(m)+Σn=0 k{β1×E(n)}+Σn=k+1 m{β2×E(n)}
- In this case, the phase pull-in operation is started, using the frequency correction component α1×E(k) collectively stored in the enable-provided
latch 33, which is discrete from theaccumulator 34, so that high-speed phase pull-in can be attained. - Fourth Configuration Example
- FIG. 10 shows a fourth configuration example of the
loop filter 21 in the FIG. 2. In FIG. 10, Reference numeral 30 a denotes a control signal generating portion,reference numeral 31 a denotes a multiplier-factor-variable multiplier,reference numeral 34 a denotes an enable-provided accumulator, andreference numeral 35 denotes is an adder. The controlsignal generating portion 30 a outputs a pulse at the Hi level as a control signal F for one clock cycle at the time when the completion of frequency pull-in is detected based on a phase error signal E output from thephase comparator 20. The multiplier-factor-variable multiplier 31 a outputs a result obtained by multiplying the phase error signal E by a first filter coefficient α1 for a period during which the control signal F is not output, and a result obtained by multiplying the phase error signal E by a second filter coefficient α2 after the control signal F is output. The enable-providedaccumulator 34 a accumulates aconstant value 0 for a period during which the control signal F is not output, and after the control signal F is output, accumulates outputs G from the multiplier-factor-variable multiplier 31 a, and outputs a result. Theadder 35 adds the output G from the multiplier-factor-variable multiplier 31 a and the output Y from the enable-providedaccumulator 34 a. A digital value representing the result of this addition, namely, a filter output Z, is supplied to theVFO 23 via the D/A converter 22. - According to the configuration of FIG. 10, during the frequency pull-in operation, the control signal F output from the control
signal generating portion 30 a is at the Lo level, so that the output Y from the enable-providedaccumulator 34 a is 0. Assuming that the phase error at an arbitrary time j during the frequency pull-in operation is E(j), the filter output Z is expressed by: - Z=G+Y=α1×E(j)
- When the frequency pull-in is completed and the frequency lock state (E=constant) is reached, the control
signal generating portion 30 a outputs a pulse at the Hi level as the control signal F. Assuming that the phase error in this frequency lock state is E(k), the output G from the multiplier-factor-variable multiplier 31 a is α1×E(k) representing a frequency correction component. The enable-providedaccumulator 34 a stores the frequency correction component α1×E(k) in response to the control signal F and then starts accumulating. From this point, a phase pull-in operation is started. - Assuming that the phase error at an arbitrary time m during the phase pull-in operation is E(m), the filter output Z is expressed by:
- Z=G+Y=α2×E(m)+α1×E(k)+Σn=k+1 m{α2×E(n)}
- In this case, the phase pull-in operation is started, using the frequency correction component α1×E(k) collectively stored in the enable-provided
accumulator 34 a, so that high-speed phase pull-in can be attained. - FIG. 11 shows a configuration example of the control
signal generating portion 30 a in FIG. 10 in detail. The configuration of FIG. 11 is different from that of FIG. 4 in that thecounter 60 in FIG. 4 is replaced by a reset-providedcounter 60 a, and acontroller 61 is added. Thecontroller 61 is means for resetting the count of the counter 60 a to 0 when it is confirmed that frequency pull-in is required again during the phase pull-in operation. Even if a frequency error is generated by, for example external disturbances during the phase pull-in operation, resetting of the counter 60 a by thecontroller 61 after a predetermined numbers of clock cycles have passed makes it possible to return from the phase pull-in operation to the frequency pull-in operation immediately. - The configurations of the control
signal generating portions 30 in FIGS. 3, 6 and 8 can be changed to the configuration of FIG. 11. - FIG. 12 shows a configuration example of the enable-provided
accumulator 34 a in FIG. 10. In FIG. 12,reference numeral 90 denotes a selector,reference numeral 91 denotes an adder andreference numeral 92 denotes a latch. Theselector 90 supplies aconstant value 0 for a period during which the control signal F is not output, and supplies the output G from the multiplier-factor-variable multiplier 31 a after the control signal F is output, to theadder 91. Theadder 91 adds the output from theselector 90 and the output from thelatch 92. The value stored in thelatch 92 is updated to the result of this addition. More specifically, the enable-providedaccumulator 34 a in FIG. 12 accumulates only the outputs G from the multiplier-factor-variable multiplier 31 a after the control signal F is output. - Fifth Configuration Example
- FIG. 13 shows a fifth configuration example of the
loop filter 21 in the FIG. 2. The configuration in FIG. 13 is different from that of FIG. 10 in that the controlsignal generating portion 30 a and the multiplier-factor-variable multiplier 31 a in FIG. 10 are provided further with a multiplier factor switching function. The controlsignal generating portion 30 b in FIG. 13 has a function for activating and outputting a multiplier factor switching signal J when a phase inversion is detected from the phase error signal E during the frequency pull-in operation, in addition to a function for outputting a pulse at the Hi level as a control signal F at the time when the completion of frequency pull-in is detected based on the phase error signal E. The multiplier-factor-variable multiplier 31 b in FIG. 13 is configured so as to multiply the phase error signal E by a first filter α1 for a period during which the control signal F is not output under the condition that the multiplier factor switching signal J is not activated, a second filter coefficient α2 after the control signal F is output, and a third filter coefficient α3 when the activated multiplier factor switching signal J is received. In other words, when the controlsignal generating portion 30 b detects a phase inversion during the frequency pull-in operation, the filter coefficient of the multiplier-factor-variable multiplier 31 b is changed to α3 so that the frequency lock is attained. - FIG. 14 is a configuration example of the control
signal generating portion 30 b in FIG. 13 in detail. The configuration of FIG. 14 is different from that of FIG. 4 in that aphase inversion detector 65 is added. - When the loop gain in the
clock recovery circuit 17 during the frequency pull-in operation is too small, a significant frequency error occurs, and thus the frequency pull-in cannot be attained. In this case, a so-called “phase inversion” occurs, where a phase error from a positive or a negative value having a large absolute value to a negative or a positive value having a large absolute value. For example, when the frequency error is positive (the oscillating clock frequency of theVFO 23 is too high), a phase inversion from negative to positive occurs. When the frequency error is negative, a phase inversion from positive to negative occurs. Thephase inversion detector 65 in FIG. 14 detects such a phase inversion. When a phase inversion is detected, the loop gain is changed by changing the filter coefficient of the multiplier-factor-variable multiplier 31 b in FIG. 13 to α3, and thus the frequency pull-in can be attained reliably. - The same configuration change as the change from FIG. 10 to FIG. 13 can be made with respect to the loop filters21 of FIGS. 3, 6, and 8.
- Sixth Configuration Example
- FIG. 15 shows a sixth configuration example of the
loop filter 21 in the FIG. 2. The configuration in FIG. 15 is different from that of FIG. 10 in that the controlsignal generating portion 30 a and theadder 35 in FIG. 10 are provided further with an offset adjusting function. The controlsignal generating portion 30 c in FIG. 15 has a function for outputting an offset signal K when a phase inversion is detected from the phase error signal E during the frequency pull-in operation, in addition to a function for outputting a pulse at the Hi level as a control signal F at the time when the completion of frequency pull-in is detected based on the phase error signal E. Theadder 35 in FIG. 15 adds the output G from the multiplier-factor-variable multiplier 31 a, the output Y from the enable-providedaccumulator 34 a, and the offset K from the controlsignal generating portion 30 c. The digital value representing the result of this addition is the filter output Z. In other words, when the controlsignal generating portion 30 c detects a phase inversion during the frequency pull-in operation, the offset signal K is supplied to theadder 35 so that the frequency lock is attained. - FIG. 16 is a configuration example of the control
signal generating portion 30 c in FIG. 15 in detail. The configuration of FIG. 16 is different from that of FIG. 4 in that aphase inversion detector 65 and an offset generatingcircuit 66 are added. Thephase inversion detector 65 detects a phase inversion from the phase error signal E. When a phase inversion is detected, the offset generatingcircuit 66 supplies the offset signal K to theadder 35, and thus the frequency pull-in can be attained reliably. - The same configuration change as the change from FIG. 10 to FIG. 15 can be made with respect to the loop filters21 of FIGS. 3, 6, and 8.
- The invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed in this application are to be considered in all respects as illustrative and not limiting. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.
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Cited By (10)
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US20030234693A1 (en) * | 2002-06-19 | 2003-12-25 | Staszewski Robert B. | Type-II all-digital phase-locked loop (PLL) |
US20060146959A1 (en) * | 2005-01-05 | 2006-07-06 | Agere Systems Inc. | Look-ahead digital loop filter for clock and data recovery |
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US20100332581A1 (en) * | 2009-06-25 | 2010-12-30 | Intuit Inc. | Creating a composite program module in a computing ecosystem |
US20150263848A1 (en) * | 2014-03-13 | 2015-09-17 | Lsi Corporation | Cdr relock with corrective integral register seeding |
CN111416617A (en) * | 2020-03-18 | 2020-07-14 | 广州土圭垚信息科技有限公司 | Clock synchronization method and device and electronic equipment |
WO2023020677A1 (en) * | 2021-08-16 | 2023-02-23 | Huawei Technologies Co., Ltd. | Timing recovery lock detector, signal receiver apparatus, and method of detecting timing recovery lock |
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JP2005294981A (en) * | 2004-03-31 | 2005-10-20 | Matsushita Electric Ind Co Ltd | Phase locking circuit |
JP2009246668A (en) * | 2008-03-31 | 2009-10-22 | Fujitsu Ltd | Clock recovery apparatus and clock recovery method, transmission device, and relay communication system |
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CA2180100C (en) * | 1994-01-12 | 2006-04-11 | Bhavesh Bhalchandra Bhatt | Higher order digital phase loop filter |
JP3350349B2 (en) | 1995-09-26 | 2002-11-25 | 株式会社日立製作所 | Digital information signal reproducing circuit and digital information device |
US6097768A (en) * | 1996-11-21 | 2000-08-01 | Dps Group, Inc. | Phase detector for carrier recovery in a DQPSK receiver |
JPH10200396A (en) | 1997-01-13 | 1998-07-31 | Hitachi Ltd | Phase locked loop circuit and signal recovery circuit using it |
US5987085A (en) * | 1997-03-26 | 1999-11-16 | Lsi Logic Coporation | Clock recovery circuit |
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1999
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-
2000
- 2000-12-12 US US09/734,183 patent/US6393084B2/en not_active Expired - Fee Related
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US7145399B2 (en) | 2002-06-19 | 2006-12-05 | Texas Instruments Incorporated | Type-II all-digital phase-locked loop (PLL) |
US20060290435A1 (en) * | 2002-06-19 | 2006-12-28 | Staszewski Robert B | Type-II All-Digital Phase-Locked Loop (PLL) |
US7382200B2 (en) | 2002-06-19 | 2008-06-03 | Texas Instruments Incorporated | Type-II all-digital phase-locked loop (PLL) |
US20030234693A1 (en) * | 2002-06-19 | 2003-12-25 | Staszewski Robert B. | Type-II all-digital phase-locked loop (PLL) |
US7463873B2 (en) | 2003-01-17 | 2008-12-09 | Texas Instruments Incorporated | Wireless communications device having type-II all-digital phase-locked loop (PLL) |
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US20050212606A1 (en) * | 2003-01-17 | 2005-09-29 | Staszewski Robert B | Wireless communications device having type-II all-digital phase-locked loop (PLL) |
US20060146959A1 (en) * | 2005-01-05 | 2006-07-06 | Agere Systems Inc. | Look-ahead digital loop filter for clock and data recovery |
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US20070085622A1 (en) * | 2005-10-19 | 2007-04-19 | Texas Instruments Incorporated | Continuous reversible gear shifting mechanism |
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US20080225170A1 (en) * | 2007-03-14 | 2008-09-18 | Larry Silver | Carrier recovery system with phase noise suppression |
US9191613B2 (en) * | 2007-03-14 | 2015-11-17 | Larry Silver | Phase-adjustment processing for broadcast channel signals |
US20080225168A1 (en) * | 2007-03-14 | 2008-09-18 | Chris Ouslis | Method and apparatus for processing a television signal with a coarsely positioned if frequency |
US8902365B2 (en) | 2007-03-14 | 2014-12-02 | Lance Greggain | Interference avoidance in a television receiver |
US20080225174A1 (en) * | 2007-03-14 | 2008-09-18 | Lance Greggain | Interference avoidance in a television receiver |
US8330873B2 (en) | 2007-03-14 | 2012-12-11 | Larry Silver | Signal demodulator with overmodulation protection |
US8502920B2 (en) | 2007-03-14 | 2013-08-06 | Vyacheslav Shyshkin | Method and apparatus for extracting a desired television signal from a wideband IF input |
US8537285B2 (en) * | 2007-03-14 | 2013-09-17 | Larry Silver | Carrier recovery system with phase noise suppression |
US20080225176A1 (en) * | 2007-03-14 | 2008-09-18 | Steve Selby | Automatic gain control system |
US20130335632A1 (en) * | 2007-03-14 | 2013-12-19 | Larry Silver | Phase-adjustment processing for broadcast channel signals |
WO2010078384A3 (en) * | 2008-12-31 | 2010-09-16 | Rambus Inc. | Method and apparatus for correcting phase errors during transient events in high-speed signaling systems |
WO2010078384A2 (en) * | 2008-12-31 | 2010-07-08 | Rambus Inc. | Method and apparatus for correcting phase errors during transient events in high-speed signaling systems |
US20100332581A1 (en) * | 2009-06-25 | 2010-12-30 | Intuit Inc. | Creating a composite program module in a computing ecosystem |
US20150263848A1 (en) * | 2014-03-13 | 2015-09-17 | Lsi Corporation | Cdr relock with corrective integral register seeding |
CN111416617A (en) * | 2020-03-18 | 2020-07-14 | 广州土圭垚信息科技有限公司 | Clock synchronization method and device and electronic equipment |
WO2023020677A1 (en) * | 2021-08-16 | 2023-02-23 | Huawei Technologies Co., Ltd. | Timing recovery lock detector, signal receiver apparatus, and method of detecting timing recovery lock |
Also Published As
Publication number | Publication date |
---|---|
US6393084B2 (en) | 2002-05-21 |
JP3403365B2 (en) | 2003-05-06 |
JP2001168712A (en) | 2001-06-22 |
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