JP2002208855A - Clock extracting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand capture range by only attaching a simple digital circuit to a clock extraction circuit of the conventional digital method. SOLUTION: A loop for extracting clock from an input signal is constructed, and a filter 21 in the loop is provided with a multiplier 30 for multiplying a phase error P by a filter coefficient, an accumulator 33 having multiplication function and an adder 34 for adding an output of the multiplier and an output of the accumulator. The filter 21 is further provided with a differential computing element 31 for calculating a difference D from the phase error P and a frequency error calculating device 32 for estimating a frequency error F from the difference D. The accumulator 33 with a multiplication function multiplies the frequency error F by a corresponding filter coefficient, while a control signal CONT instructing frequency pulling and the phase error P by a corresponding filter coefficient respectively; when the accumulator is shifted to phase- tracking operation, and also the multiplication results are accumulated and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock extracting circuit for extracting a clock signal synchronized with an input signal from an input signal quantized to a digital value.

[0002]

2. Description of the Related Art In a data reproducing apparatus for decoding and reproducing a data signal recorded on a recording medium such as an optical disk, a magnetic disk or the like, the reproduced signal from the recording medium is identified as data in order to identify the reproduced signal. It is necessary to extract a synchronized clock signal from the reproduction signal.

In general, a PLL (Phase-Locked Loop) technique is used for clock extraction. The digital clock extraction circuit includes a phase comparator, a loop filter, a D /
It consists of an A converter and a voltage controlled oscillator (VCO).
The VCO generates a variable frequency oscillation clock signal under the control of the analog voltage. The phase comparator calculates a digital value representing a phase error of an oscillation clock signal with respect to an input signal quantized to a digital value. For example, KHMueller et al., "Timing Recovery in
Digital Synchronous Data Receivers ", IEEE Transac
tions on Communications, Vol. COM-24, No. 5, pp.51
The phase error signal is output by the digital method described in 6-531, May 1976. The loop filter is a circuit block for smoothing and outputting the digital output of the phase comparator. For example, a first multiplier for multiplying the digital output of the phase comparator by a fixed filter coefficient α and outputting the result And a second multiplier for multiplying the digital output of the phase comparator by a fixed filter coefficient β (<α) and outputting the same, and an accumulator for accumulating and outputting the output of the second multiplier And an adder for supplying a digital value representing a result of addition of the output of the first multiplier and the output of the accumulator to the D / A converter. The filter coefficient β of the second multiplier is equal to the first coefficient for stable operation of the loop.
Is set to be sufficiently small with respect to the filter coefficient α of the multiplier. The D / A converter converts the digital output of the loop filter into an analog voltage and supplies it to the VCO so as to control the generation of the oscillation clock signal so as to reduce the phase error to zero.

The clock signal extracted as described above is used as a sampling clock for an A / D converter for generating a quantized signal which is one input of the phase comparator, and is used as a system clock for another digital unit. Each is given as a clock.

[0005] In the initial state, the oscillation clock signal of the VCO contains not only a phase error but also a frequency error. If the sampling clock of the A / D converter has a frequency error, a phenomenon occurs in which the sampling point of the A / D conversion shifts. In order to eliminate this phenomenon, the clock extraction circuit first performs a frequency pull-in operation. And
When the frequency lock state is achieved by the pull-in operation, the operation shifts to the phase tracking operation.

[0006]

The conventional digital clock extraction circuit has a problem that the pull-in range (capture range) of the PLL is narrow. This problem becomes more pronounced as the oscillation clock frequency of the VCO increases. This is because the digital delay (clock latency) from the phase comparison to the control of the VCO becomes longer, so that the loop gain of the PLL cannot be increased.

In order to solve this problem, it is conceivable that an analog clock extraction circuit and a digital clock extraction circuit coexist, and the former is used for frequency pull-in and the latter is used for phase tracking. However, in this case, the analog PLL and the digital PLL coexist, resulting in a disadvantage that the circuit scale is increased and the circuit operation is complicated.

It is an object of the present invention to expand the capture range only by adding a simple digital circuit to a conventional digital clock extraction circuit.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention estimates a frequency error based on a difference of a phase error. To
During the phase tracking in the frequency locked state, the phase errors are mainly accumulated respectively.

More specifically, the clock extracting circuit of the present invention includes the following loop filter. That is, the loop filter according to the present invention includes a multiplier for multiplying the digital output of the phase comparator by a filter coefficient and outputting the same, and a digital value for representing a difference between the digital outputs of the phase comparator and outputting the digital value. A difference calculator, a frequency error calculator for calculating and outputting a digital value representing a frequency error estimated from the difference, and a control signal instructing switching between a frequency pull-in operation and a phase tracking operation, and When the control signal indicates the frequency pull-in operation, it mainly corresponds to the digital output of the frequency error calculator, and when the control signal indicates the phase tracking operation, it mainly corresponds to the digital output of the phase comparator. Accumulator with a multiplication function for multiplying by the filter coefficient to be performed and accumulating and outputting the result of the multiplication Those having a chromatography data, and an adder for outputting a digital value representing the result of the addition of the outputs of the multiplication function accumulator multiplier.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an application example of the present invention to a clock extraction circuit in a reproduction system of an optical disk will be described.

FIG. 1 shows an example of a reproduction signal processing circuit in an optical disk device using a clock extraction circuit according to the present invention. In FIG. 1, 10 is an optical disk,
11 is an optical head, 12 is an AGC for amplitude correction of a reproduced signal.
Circuit, 13 is an analog filter for waveform equalization, 14 is A
/ D converter, 15 is a digital filter for waveform correction,
16 is a maximum likelihood decoder, and 17 is a clock extraction circuit according to the present invention.

According to the configuration shown in FIG. 1, a reproduced signal obtained from the optical disk 10 by the optical head 11
And the analog filter 13 performs waveform equalization according to the characteristics of the maximum likelihood decoder 16. The output of the analog filter 13 is supplied to an A / D converter 14. A
The / D converter 14 quantizes the supplied analog signal. The reproduced signal quantized in this way is subjected to waveform correction by the digital filter 15 so as to have desired reproduction characteristics, and then converted into decoded data by the maximum likelihood decoder 16. The reproduced signal quantized by the A / D converter 14 is also input to the clock extraction circuit 17. The clock extraction circuit 17 extracts a clock synchronized with the input signal from the input signal. The output clock (extracted clock) of the clock extracting circuit 17 is used as a sampling clock for quantization in the A / D converter 14 and is used as a digital filter 15 and a maximum likelihood decoder 16.
Etc. are used as the system clock of the digital section.

FIG. 2 shows a configuration example of the clock extraction circuit 17 in FIG. In FIG. 2, 20 is a phase comparator, 21 is a loop filter, 22 is a D / A converter, and 23
Is a voltage controlled oscillator (VCO). The VCO 23 generates a variable frequency oscillation clock signal under the control of the analog voltage. The phase comparator 20 includes the A / D converter 1
A digital value representing a phase error of the oscillation clock signal with respect to the output signal (output sample) of No. 4 is calculated and output.
The loop filter 21 is a circuit block for smoothing and outputting the digital output of the phase comparator 20, that is, the phase error signal P. The D / A converter 22 converts the digital output Z of the loop filter 21 into an analog voltage and supplies it to the VCO 23 so as to control the generation of the oscillation clock signal so that the phase error becomes zero. The oscillation clock signal of the VCO 23 is also used as a clock signal for the synchronous operation of the loop filter 21 and the D / A converter 22.

The loop filter 21 shown in FIG.
0, a difference calculator 31, a frequency error calculator 32, an accumulator 33 with a multiplication function, an adder 34, and a controller 35. The controller 35 generates a control (CONT) signal for instructing switching between the frequency pull-in operation and the phase tracking operation. Here, CONT = 0 (= L: low) indicates the frequency pull-in operation, and CONT = 1 (= H: high) indicates the phase tracking operation. The multiplier 30
The multiplier is a variable multiplier configured to multiply the phase error P by using the multiplier α0 as a filter coefficient when CONT = 0 and to output the multiplier α1 when CONT = 1, respectively. The output of the multiplier 30 is X. The difference calculator 31 receives an enable (EN) signal indicating the calculation timing of the phase error P from the phase comparator 20, calculates and outputs a digital value indicating the difference of the phase error P. This output is the phase error difference signal D. The frequency error calculator 32 calculates and outputs a digital value representing a frequency error estimated from the difference D between the phase errors. This output is the frequency error signal F. The accumulator 33 with the multiplication function is connected to the CON
When T = 0, mainly the frequency error F
When T = 1, the phase error P is mainly multiplied by the corresponding filter coefficient, and the result of the multiplication is accumulated and output. Accumulator 33 with this multiplication function
Is Y. The adder 34 supplies a digital value representing a result of addition of the multiplier output X and the accumulator output Y to the D / A converter 22 as a filter output Z. The controller 35, as described in detail below,
The CONT signal is generated according to whether or not the phase error difference D is within a preset range.

According to the above configuration, the frequency error F is estimated based on the phase error difference D, and the frequency error F is mainly accumulated when the frequency is pulled in the unlocked state. Can expand the capture range.

If the loop gain of the clock extracting circuit 17 during the frequency pull-in operation is too small, the frequency pull-in may not be achieved. This is because so-called “phase inversion” occurs in which the phase error changes from a positive or negative value having a large absolute value to a negative or positive value having a large absolute value. For example, if the frequency error is positive (the oscillation clock frequency of the VCO 23 is too high), a phase inversion from negative to positive occurs, and if the frequency error is negative, a phase inversion from positive to negative occurs. FIG. 3 shows the phase comparator 2
An example of phase inversion from negative to positive at 0 is shown.

When the phase inversion as shown in FIG. 3 occurs, the phase error difference signal D output from the difference calculator 31 in FIG. 2 shows a large digital value. When the frequency error is estimated based on this digital value, the frequency error signal F indicating a large digital value in the direction opposite to the direction of the actual frequency error is accumulated by the accumulator 33 with the multiplication function, and There is a possibility that a loop for extraction may be in an oscillation state. Therefore, it is preferable that the frequency error calculator 32 eliminate the influence of the phase inversion by integrating the frequency error with respect to one cycle of the phase inversion.

Hereinafter, the configuration examples of the difference calculator 31, the frequency error calculator 32, the accumulator 33 with a multiplication function, and the controller 35 in FIG. 2 will be sequentially described.

FIG. 4 shows a configuration example of the difference calculator 31 in FIG. The difference calculator 31 shown in FIG. 4 calculates the difference between the phase error signals P and outputs the phase error difference signal D by two latches 4 operating in response to the EN signals.
0, 41 and a subtractor 42. The phase error difference signal D represents the difference between the phase errors of two consecutive samples.

FIG. 5 shows an example of the configuration of the frequency error calculator 32 in FIG. In FIG. 5, 50 is an absolute value calculator, 51 is a subtractor, and 52 and 53 are selectors. The absolute value calculator 50 calculates and outputs the absolute value of the phase error difference D. The subtractor 51 subtracts the output of the absolute value calculator 50 from a preset threshold TH and outputs the result. The most significant bit (MSB) of the output of the subtractor 51 is 0 if the difference D of the phase error falls between + TH and -TH, and is 1 otherwise. The selector 52 is
When the difference D of the phase error is positive, a positive specified value (F
+) Is replaced by a negative specified value (F) when the difference D is negative.
-) Are code selectors for selecting and outputting each of them. The selector 53 sets the MSB of the output of the subtractor 51 to 0.
Is an output selector for selecting the output of the code selector 52 if not, and selecting 0 otherwise, and outputting it as the frequency error signal F.

According to the configuration of FIG. 5, only when the difference D of the phase error falls within a preset range, F
+ Or F- is regarded as the frequency error F. However, the absolute value calculator 50, the subtractor 51, and the output selector 53 are omitted, and the output of the code selector 52 is directly used as the frequency error F.
However, it is possible to eliminate the influence of the phase inversion.

FIG. 6 shows another example of the configuration of the frequency error calculator 32 in FIG. The configuration in FIG. 6 is such that the code selector 52 in FIG. 5 is omitted. According to FIG. 6, the output selector 53 determines the difference D of the phase error when the MSB of the output of the subtractor 51 is 0;
Are selected and output as the frequency error F. Therefore, only when the difference D of the phase error is within the preset range, the difference D is regarded as the frequency error F as it is.

FIG. 7 shows a configuration example of the accumulator 33 with a multiplication function in FIG. In FIG. 7, 60,
61 is first and second multipliers, 62 and 63 are first and second accumulators, and 64 is an adder. The first multiplier 60 calculates a multiplier β0 if CONT = 0 and CONT =
If 1, the multiplier is a variable multiplier configured to multiply the frequency error F by the multiplier β1 as a filter coefficient and output the result. The second multiplier 61 is a variable multiplier configured to multiply the phase error P as a filter coefficient and output the multiplier γ0 if CONT = 0 and the multiplier γ1 if CONT = 1. Frequency pull-in operation (C
During ONT = 0, the frequency error F is weighted larger than the phase error P, and the phase tracking operation (C
During ONT = 1), β0, β1, γ0 and γ1 are adjusted so that the phase error P is weighted more than the frequency error F. The first accumulator 62 includes a first accumulator 62.
Accumulates the output of the multiplier 60, and is composed of one adder and one latch. The second accumulator 63 accumulates the output of the second multiplier 61, and similarly includes one adder and one latch. The adder 64 uses a digital value representing the result of addition of the outputs of the accumulators 62 and 63 as the output Y of the accumulator 33 with the multiplication function.

According to the configuration of FIG. 7, the frequency error F is mainly accumulated at the time of frequency pull-in, and the phase error P is mainly accumulated at the time of phase tracking. In addition, the three multipliers 30, 60, and 61 can independently set the gain for frequency pull-in and the gain for phase tracking.

FIG. 8 shows another example of the configuration of the accumulator 33 with a multiplication function in FIG. In FIG. 8, 7
0 is a selector, 71 is a multiplier, and 72 is an accumulator. The selector 70 selects and outputs the frequency error F if CONT = 0 and the phase error P if CONT = 1. The multiplier 71 outputs a multiplier β if CONT = 0.
The multiplier is a variable multiplier configured to multiply the output of the selector 70 by selecting 0 as the filter coefficient and output the multiplier β1 as the filter coefficient if CONT = 1. β0 is adjusted to a value for frequency pull-in, and β1 is adjusted to a value for phase tracking. The accumulator 72 accumulates the output of the multiplier 71 and uses the result as the output Y of the accumulator 33 with the multiplication function. The accumulator 72 includes one adder and one latch.

According to the configuration shown in FIG. 8, only the frequency error F is accumulated during frequency pull-in, and only the phase error P is accumulated during phase tracking. In addition, the two multipliers 30 and 71 can independently set the frequency pull-in gain and the phase tracking gain.

FIG. 9 shows an example of the configuration of the controller 35 in FIG. In FIG. 9, reference numeral 80 denotes a window comparator, 90 denotes a control signal generation circuit, and 100 denotes an unlock detection circuit. The controller 35 of FIG. 9 always checks whether or not the difference D of the phase error falls within a preset range, and it is confirmed during the frequency pull-in operation that the difference D falls within the range. In this case, a CONT signal is generated so as to instruct the shift from the frequency pull-in operation to the phase tracking operation, and when it is confirmed during the phase tracking operation that the difference D is not within the range, The CONT signal is generated so as to instruct the shift from the phase tracking operation to the frequency pull-in operation.

The window comparator 8 shown in FIG.
0, control signal generation circuit 90 and unlock detection circuit 10
An example of the internal configuration of 0 will be described sequentially.

The window comparator 80 checks whether or not the difference D between the phase errors is within a preset range, and outputs the result as an in-range (IR) signal. It is composed of subtracters 81 and 82 and one logic gate 83. Here, if the phase error difference D falls between the positive threshold value (TH +) and the negative threshold value (TH-), IR = 1 (= H); otherwise, IR = 0 ( = L). Specifically, the first subtracter 81 subtracts a positive threshold value (TH +) from the difference D of the phase error, and obtains the MSB of the result.
Is applied to one input of the logic gate 83. The second subtractor 82 subtracts the negative threshold value (TH−) from the difference D of the phase error, and supplies the resulting MSB to the other input of the logic gate 83. In the initial state of the clock extraction circuit 17, IR
= 0 and IR = 1 in the frequency locked state.

The control signal generation circuit 90 includes a counter 91
, A comparator 92, a logic gate 93, a rising edge detector 94, and an OR gate 95. Since IR = 0 in the initial state, the OR gate 95
Resets the counter 91. When IR = 1, the counter 91 counts a clock signal (not shown). The comparator 92 determines that the frequency pull-in has been completed when the output of the counter 91 reaches the set value A, and sets CONT = 1. The CONT signal that has been set to the H level in this manner is supplied as a hold signal to the counter 91 via the logic gate 93. For example, positive and negative thresholds (TH + and TH−) are +1 and −1, respectively,
Assuming that the set value A is 10, the phase error difference D
It is determined that the frequency pull-in has been completed at the point in time when the period during which −1, 0 or +1 continues for 10 clock cycles. When the IR signal returns to the L level, the IR signal is supplied to the counter 91 via the OR gate 95 as a reset signal. Rising edge detector 9
4 will be described later.

The out-of-lock detection circuit 100 includes a logic gate 101, a counter 102, a comparator 103, and a rising edge detector 104 so as to generate an out-of-lock (LO) signal from the CONT signal and the IR signal. You. Here, it is assumed that LO = 0 (= L) while no unlock is detected, and LO = 1 (= H) when the unlock is detected. When shifting from the frequency pull-in operation to the phase tracking operation, CO
The NT signal rises from L level to H level. The rising edge detector 104 resets the counter 102 when detecting the rising edge of the CONT signal. The logic gate 101 informs the counter 102 that IR = 0 while CONT = 1. That is, the counter 102 counts the number of times phase inversion has occurred. When the output of the counter 102 reaches the set value B or more, the comparator 103 determines that unlock has occurred and sets LO = 1. The LO signal that has been set to the H level in this manner is supplied to the logic gate 93 as a signal for releasing the hold of the counter 91 in the control signal generation circuit 90. Also, the control signal generation circuit 90
Are detected by the rising edge detector 94 at the time when the rising edge of the LO signal is detected.
Resets the counter 91 via the OR gate 95 so that the CONT signal falls to the L level. The CONT signal which has been set to the L level in this manner is output from the counter 1
02 is given as a hold signal.

As described above, according to the controller 35 of FIG. 9, not only the transition from the frequency pull-in operation to the phase tracking operation, but also the phase tracking operation in the case where the lock is lost due to the influence of noise, for example, the frequency pull-in operation Migration can be performed automatically. Note that it is of course possible to generate the CONT signal from a signal other than the phase error difference signal D.

[0034]

As described above, according to the present invention, the frequency error is estimated based on the difference between the phase errors, and the frequency error is mainly accumulated when the frequency is pulled in the unlocked state. The capture range of the clock extraction circuit can be easily expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a reproduction system signal processing circuit in an optical disk device using a clock extraction circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a clock extraction circuit in FIG. 1;

FIG. 3 is a waveform chart showing an example of phase inversion in the phase comparator in FIG. 2;

FIG. 4 is a block diagram illustrating a configuration example of a difference calculator in FIG. 2;

FIG. 5 is a block diagram illustrating a configuration example of a frequency error calculator in FIG. 2;

FIG. 6 is a block diagram showing another example of the configuration of the frequency error calculator in FIG. 2;

FIG. 7 is a block diagram showing a configuration example of an accumulator with a multiplication function in FIG. 2;

FIG. 8 is a block diagram showing another example of the configuration of the accumulator with a multiplication function in FIG. 2;

FIG. 9 is a block diagram illustrating a configuration example of a controller in FIG. 2;

[Explanation of symbols]

 Reference Signs List 10 optical disk 11 optical head 12 AGC circuit 13 analog filter 14 A / D converter 15 digital filter 16 maximum likelihood decoder 17 clock extraction circuit 20 phase comparator 21 loop filter 22 D / A converter 23 voltage controlled oscillator (VCO) 30 , 60, 61, 71 Multiplier 31 Difference calculator 32 Frequency error calculator 33 Accumulator with multiplication function 34, 64 Adder 35 Controller 40, 41 Latch 42, 51 Subtractor 50 Absolute value calculator 52, 53, 70 Selector 62 , 63, 72 Accumulator 80 Window comparator 81, 82 Subtractor 83, 93, 101 Logic gate 90 Control signal generation circuit 91, 102 Counter 92, 103 Comparator 94, 104 Rising edge detector 95 OR gate 100 B Click out detector circuit CONT control signal D phase error difference signal EN enable signal F frequency error signal IR-range signal LO unlock signal P phase error signal X multiplier output Y accumulator output Z filter output alpha, beta, gamma filter coefficients

Claims (10)

[Claims] 1. A clock extracting circuit for extracting a clock signal synchronized with an input signal from an input signal quantized to a digital value, comprising: an oscillator for generating an oscillation clock signal having a variable frequency; A phase comparator for calculating and outputting a digital value representing a phase error of the oscillation clock signal with respect to an input signal; a loop filter for smoothing and outputting a digital output of the phase comparator; and A converter for converting a digital output of the loop filter to an analog voltage and supplying the analog voltage to the oscillator so as to control the generation of the oscillation clock signal to zero. A multiplier for multiplying the digital output of the comparator by a filter coefficient and outputting the result, and a difference between digital outputs of the phase comparator. A difference calculator for calculating and outputting a digital value representing the following; a frequency error calculator for calculating and outputting a digital value representing a frequency error estimated from the difference; a frequency pull-in operation and a phase tracking operation When the control signal indicates a phase tracking operation, mainly when the control signal indicates a frequency pull-in operation, the digital signal of the frequency error calculator indicates that the control signal indicates a phase tracking operation. An accumulator with a multiplication function for multiplying the digital output of the phase comparator by a corresponding filter coefficient, and accumulating and outputting the result of the multiplication, with the output of the multiplier and the multiplication function An adder for supplying a digital value representing the result of addition with the output of the accumulator to the converter. A clock extraction circuit, comprising: 2. The clock extracting circuit according to claim 1, wherein the multiplier is a multiplier variable multiplier for multiplying a digital output of the phase comparator by a different multiplier according to the control signal and outputting the result. A clock extraction circuit, characterized in that: 3. The clock extraction circuit according to claim 1, wherein the frequency error calculator selects one of positive and negative prescribed values according to whether the digital output of the difference arithmetic unit is positive or negative. 1. A clock extraction circuit comprising a code selector for outputting a clock signal. 4. The clock extraction circuit according to claim 3, wherein the frequency error calculator determines whether or not a digital output of the difference calculator falls within a preset range. An output selector for selecting and outputting the output of the code selector when the digital output of the difference calculator falls within the range, and otherwise selecting and outputting 0. Clock extraction circuit. 5. The clock extracting circuit according to claim 1, wherein the frequency error calculator determines whether a digital output of the difference calculator falls within a preset range. An output selector for selecting and outputting the digital output of the difference arithmetic unit when the digital output of the difference arithmetic unit falls within the range, and otherwise selecting 0. And a clock extraction circuit. 6. The clock extracting circuit according to claim 1, wherein the accumulator with a multiplying function is configured to multiply a digital output of the frequency error calculator by a different multiplier according to the control signal and output the multiplied result. A multiplier variable multiplier, a second multiplier variable multiplier for multiplying a digital output of the phase comparator by a different multiplier corresponding to the control signal, and outputting the multiplied variable multiplier, and an output of the first multiplier variable multiplier. A first accumulator for accumulating and outputting; a second accumulator for accumulating and outputting the output of the second multiplier variable multiplier; and each of the first and second accumulators A clock extraction circuit, comprising: an adder for outputting a digital value representing a result of the addition of the outputs. 7. The clock extraction circuit according to claim 1, wherein the accumulator with a multiplying function outputs a digital output of the frequency error calculator when the control signal indicates a frequency pull-in operation. Is instructing a phase tracking operation, a selector for selecting and outputting a digital output of the phase comparator, and multiplying the output of the selector by a different multiplier according to the control signal, and outputting the result. A clock extraction circuit comprising: a variable multiplier for accumulating the output of the variable multiplier; and an accumulator for accumulating and outputting the output of the variable multiplier. 8. The clock extraction circuit according to claim 1, wherein the loop filter generates the control signal depending on whether a digital output of the difference calculator falls within a preset range. A clock extraction circuit, further comprising: 9. The clock extraction circuit according to claim 8, wherein the controller determines that a digital output of the difference calculator falls within the range during the frequency acquisition operation. A clock extraction circuit comprising means for generating the control signal so as to instruct a transition from an operation to a phase tracking operation. 10. The clock extraction circuit according to claim 8, wherein the controller performs phase tracking when it is confirmed that the digital output of the difference calculator does not fall within the range during the phase tracking operation. A clock extraction circuit comprising means for generating the control signal so as to instruct a transition from an operation to a frequency pull-in operation.