JPH0346413A - Phase locked loop circuit - Google Patents

Phase locked loop circuit

Info

Publication number
JPH0346413A
JPH0346413A JP1182042A JP18204289A JPH0346413A JP H0346413 A JPH0346413 A JP H0346413A JP 1182042 A JP1182042 A JP 1182042A JP 18204289 A JP18204289 A JP 18204289A JP H0346413 A JPH0346413 A JP H0346413A
Authority
JP
Japan
Prior art keywords
voltage
phase
frequency
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1182042A
Other languages
Japanese (ja)
Inventor
Masajiro Kondo
近藤 政次郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1182042A priority Critical patent/JPH0346413A/en
Publication of JPH0346413A publication Critical patent/JPH0346413A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain the phase pull-in with a wide frequency range by detecting a level of a frequency error signal, discriminating the level with a threshold level, switching the level of a frequency error signal fed to a voltage controlled oscillator so as to eliminate the effect of an interrupt signal or distortion. CONSTITUTION:A threshold voltage of a control voltage detection circuit 61 of a control voltage changeover means 6 is set between an output voltage of a frequency error detection means 5 with the production of pseudo locking caused therein and an output voltage of the means 5 with interference or distortion caused therein in advance. When an output voltage of the means 5 is higher than the threshold voltage, it is decided as the occurrence of pseudo pull-in phenomenon, and the output of a voltage changeover device 62 is switched to input the output voltage of the means 5 as it is to a 2nd input terminal 8 of a voltage controlled oscillator 3 thereby controlling the frequency of the oscillator 3. On the other hand, when the output voltage of the means 5 is lower than the threshold level, it is decided to be in the phase pull-in state even with interruption or distortion. Then the output of the changeover device 62 is switched to input a preset control voltage to the terminal 8 so that the reference phase carrier (b) has the frequency f0 of the input signal (a) thereby keeping the frequency of the carrier (b) to the frequency f0.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、位相変調されたディジタル信号から同期信号
を再生する位相同期回路に利用され、特に、干渉信号の
多い条件下においても、安定した同期引込みができる位
相同期回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to a phase synchronization circuit that regenerates a synchronization signal from a phase-modulated digital signal, and is particularly applicable to a phase synchronization circuit that reproduces a synchronization signal from a phase-modulated digital signal. This invention relates to a phase-locked circuit capable of synchronous pull-in.

〔概要〕〔overview〕

本発明は、入力信号と電圧制御発振器から出力される基
準位相搬送波とを比較し位相誤差信号および周波数誤差
信号を生成し、これらの誤差信号により前記電圧制御発
振器の制御を行う構成の位相同期回路において、 前記周波数誤差信号の大きさを検出し、その大きさをあ
らかじめ定められたしきい値にて判定し、この判定結果
に従って前記電圧制御発振器に供給する前記周波数誤差
信号の大きさを切り替えることにより、 干渉信号や歪みによる影響をなくし、広い周波数引込範
囲がとれるようにしたものである。
The present invention provides a phase locked circuit configured to compare an input signal with a reference phase carrier output from a voltage controlled oscillator, generate a phase error signal and a frequency error signal, and control the voltage controlled oscillator using these error signals. , detecting the magnitude of the frequency error signal, determining the magnitude using a predetermined threshold, and switching the magnitude of the frequency error signal supplied to the voltage controlled oscillator according to the determination result. This eliminates the effects of interference signals and distortion, and allows for a wide frequency pull-in range.

〔従来の技術〕[Conventional technology]

従来、この種の位相同期回路は、第2図に示すように信
号入力端子lから入力される入力信号aを基準位相搬送
波すにて位相検波する4相の位相検波器2と、第一入力
端子7および第二入力端子8の二つの入力端子を有しこ
れらの入力端子により発振周波数を制御し、基準位相搬
送波すを出力する電圧制御発振器3と、位相検波器2の
出力に結合され、入力信号と基準位相搬送波との位相誤
差を検出し、その平均電圧を位相誤差信号Cとして出力
する位相誤差検出手段4と、同じく位相検波器2の出力
に結合され、入力信号と基準位相搬送波との周波数誤差
を検出し、その平均電圧を周波数誤差信号dとして出力
する周波数誤差検出手段5とを備え、電圧制御発振器3
の第一入力端子7には位相誤差検出手段4の出力電圧を
、第二入力端子8には周波数誤差検出手段の出力電圧を
直接入力することにより、基準位相搬送波の周波数を制
御していた。
Conventionally, this type of phase synchronization circuit includes a four-phase phase detector 2 that detects the phase of an input signal a input from a signal input terminal l using a reference phase carrier wave, as shown in FIG. A voltage controlled oscillator 3 which has two input terminals, a terminal 7 and a second input terminal 8, controls the oscillation frequency by these input terminals, and outputs a reference phase carrier wave, and is coupled to the output of the phase detector 2, Phase error detection means 4 detects the phase error between the input signal and the reference phase carrier wave and outputs the average voltage as a phase error signal C; frequency error detection means 5 for detecting a frequency error of , and outputting the average voltage as a frequency error signal d;
The frequency of the reference phase carrier wave was controlled by directly inputting the output voltage of the phase error detection means 4 to the first input terminal 7 and the output voltage of the frequency error detection means to the second input terminal 8.

なおここで、位相誤差検出手段4は、排他的論理和回路
41および低減ろ波器42を含み、周波数誤差検出手段
5は、遅延回路51、排他的論理和回路52、合成回路
53および低域ろ波器54を含んでいる。
Here, the phase error detection means 4 includes an exclusive OR circuit 41 and a reduction filter 42, and the frequency error detection means 5 includes a delay circuit 51, an exclusive OR circuit 52, a synthesis circuit 53, and a low frequency A filter 54 is included.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述した従来の位相同期回路は、周波数誤差信号の平均
電圧を直接電圧制御発振器3の第二入力端子8に供給す
るため、入力信号が干渉信号の影響を受け、入力信号の
スペクトラムが変形した場合、例えば、第3図(a)お
よび(b)に示すように、入力信号のスペクトラムが、
同図(a)から同図ら)のように変形すると、あたかも
、入力信号の周波数がずれたかのように、周波数誤差信
号の平均電圧が変化し、基準位相搬送波の周波数がf。
The conventional phase-locked circuit described above directly supplies the average voltage of the frequency error signal to the second input terminal 8 of the voltage controlled oscillator 3, so if the input signal is affected by an interference signal and the spectrum of the input signal is deformed. For example, as shown in FIGS. 3(a) and (b), the spectrum of the input signal is
When the transformation is performed as shown in (a) to (a) of the same figure, the average voltage of the frequency error signal changes as if the frequency of the input signal were shifted, and the frequency of the reference phase carrier wave changes to f.

からf′。from f'.

へ移動するため、位相引込周波数範囲が狭くなってしま
う欠点がある。
This has the drawback that the phase entrainment frequency range becomes narrower.

本発明の目的は、前記の欠点を除去することにより、擬
似引込現象を起こすことなく、広い同期引込周波数範囲
を有する位相同期回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked circuit having a wide synchronous pull-in frequency range without causing a pseudo pull-in phenomenon by eliminating the above-mentioned drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、入力信号を基準位相搬送波にて位相検波する
位相検波器と、第一および第二入力端子を有しこれら入
力端子に供給される電圧によって発振周波数を変化させ
前記基準位相搬送波を出力する電圧制御発振器と、前記
位相検波器の出力により前記入力信号と前記基準位相搬
送波との位相誤差を検出し位相誤差信号を生成し前記電
圧制御発振器の第一入力端子に供給する位相誤差検出手
段と、前記位相検波器の出力により前記入力信号と前記
基準位相搬送波との周波数誤差を検出し周波数誤差信号
を生成し前記電圧制御発振器の第二入力端子に供給する
周波数誤差検出手段とを備えた位相同期回路において、
前記周波数誤差信号電圧の大きさを検出しこの検出され
た電圧の大きさをあらかじめ定められたしきい値電圧と
比較して判定しこの判定結果に従って前記電圧制御発振
器の第二入力端子に供給する電圧の大きさを切り替える
制御電圧切替手段を備えたことを特徴とする。
The present invention has a phase detector that detects the phase of an input signal using a reference phase carrier wave, and a first and second input terminal, and changes the oscillation frequency by a voltage supplied to these input terminals to output the reference phase carrier wave. a voltage controlled oscillator that detects a phase error between the input signal and the reference phase carrier wave using the output of the phase detector, generates a phase error signal, and supplies the generated phase error signal to a first input terminal of the voltage controlled oscillator. and frequency error detection means that detects a frequency error between the input signal and the reference phase carrier wave using the output of the phase detector, generates a frequency error signal, and supplies the generated frequency error signal to a second input terminal of the voltage controlled oscillator. In a phase locked circuit,
Detecting the magnitude of the frequency error signal voltage, determining the magnitude of the detected voltage by comparing it with a predetermined threshold voltage, and supplying the voltage to the second input terminal of the voltage controlled oscillator according to the determination result. The present invention is characterized by comprising a control voltage switching means for switching the magnitude of the voltage.

〔作用〕[Effect]

入力信号と基準位相搬送波との周波数誤差信号は、擬似
引込現象が発生した場合には周波数ずれが大きいために
、その大きさは非常に大きくなる。
The frequency error signal between the input signal and the reference phase carrier wave becomes very large when the pseudo-entrainment phenomenon occurs because the frequency deviation is large.

一方、干渉信号や歪みによる前記基準位相搬送波の周波
数のずれは小さいので、この同期引込時にはその大きさ
は小さい、そこで、制御電圧切替手段におけるしきい値
として前記周波数誤差信号の大きさの擬似引込現象時の
値と、同期引込時の値との中間に設定する。そして、し
きい値以上のときは、前記周波数誤差信号をそのまま電
圧制御発振器の第二入力端子に供給し、しきい値以下の
場合は通常の規定の大きさの信号を供給する。
On the other hand, since the frequency shift of the reference phase carrier wave due to interference signals and distortion is small, the magnitude is small at the time of this synchronization pull-in. Therefore, a pseudo pull-in of the magnitude of the frequency error signal is used as a threshold value in the control voltage switching means. Set between the value at the time of the phenomenon and the value at the time of synchronization pull-in. When the frequency error signal is above the threshold value, the frequency error signal is supplied as it is to the second input terminal of the voltage controlled oscillator, and when it is below the threshold value, a signal of a normal prescribed magnitude is supplied.

従って、擬似引込現象を起こすことなく、かつ、基準位
相搬送波の周波数ずれがなくなり、広範囲の周波数範囲
で同期引込みを行うことが可能となる。
Therefore, it is possible to perform synchronous pull-in in a wide frequency range without causing a pseudo pull-in phenomenon and without frequency deviation of the reference phase carrier wave.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例を示すブロック構成図である
FIG. 1 is a block diagram showing one embodiment of the present invention.

本実施例は、信号入力端子1に入力される入力信号aを
基準位相搬送波すにて位相検波する位相検波器2と、第
一および第二入力端子7および8を有しこれら入力端子
7および8に供給される電圧によって発振周波数を変化
させ基準位相搬送波すを出力する電圧制御発振器3と、
位相検波器2の出力により入力信号aと基準位相搬送波
すとの位相誤差を検出し位相誤差信号Cを生成し電圧制
御発振器3の第一入力端子7に供給する位相誤差検出手
段4と、位相検波器2の出力により入力信号aと基準位
相搬送波すとの周波数誤差を検出し周波数誤差信号dを
生成し電圧制御発振器3の第二入力端子8に供給する周
波数誤差検出手段5とを備えた位相同期回路において、 本発明の特徴とするところの、周波数誤差信号電圧の大
きさを検出しこの検出された電圧の大きさをあらかじめ
定められたしきい値電圧にて判定しこの判定結果に従っ
て電圧制御発振器3の第二入力端子8に供給する電圧の
大きさを切り替える制御電圧切替手段6を備えている。
This embodiment has a phase detector 2 which detects the phase of an input signal a input to a signal input terminal 1 using a reference phase carrier wave, and a first and second input terminal 7 and 8. a voltage controlled oscillator 3 that changes its oscillation frequency depending on the voltage supplied to the oscillator 8 and outputs a reference phase carrier wave;
A phase error detection means 4 detects the phase error between the input signal a and the reference phase carrier wave by the output of the phase detector 2, generates a phase error signal C, and supplies it to the first input terminal 7 of the voltage controlled oscillator 3; The frequency error detection means 5 detects the frequency error between the input signal a and the reference phase carrier wave by the output of the wave detector 2, generates a frequency error signal d, and supplies the generated frequency error signal d to the second input terminal 8 of the voltage controlled oscillator 3. In a phase-locked circuit, the present invention is characterized by detecting the magnitude of the frequency error signal voltage, determining the magnitude of the detected voltage using a predetermined threshold voltage, and adjusting the voltage according to the determination result. A control voltage switching means 6 is provided for switching the magnitude of the voltage supplied to the second input terminal 8 of the controlled oscillator 3.

さらに、位相誤差検出手段4は、位相検波器2からの二
つの出力の排他的論理和をとる排他的論理和回路41と
、この排他的論理和回路41の出力中の高周波成分を取
り除き位相誤差信号Cを出力する低域ろ波器42とを含
み、 周波数誤差検出手段5は、位相検波回路2の一方の出力
に所定の遅延を与える遅延回路51と、この遅延回路5
1の出力と位相検波回路2の他方の出力との排他的論理
和をとる排他的論理和回路52と、この排他的論理和回
路52の出力から排他的論理和回路41の出力を差し引
く合成回路53と、この合成回路53の出力中の高周波
成分を取り除き周波数誤差信号dを出力する低域ろ波器
54とを含み、制御電圧切替手段6は、周波数誤差信号
dを入力しその電圧の大きさをあらかじめ与えられたし
きい値電圧と比較し切替信号eを出力する制御電圧検出
回路61と、入力される切替信号eに従って周波数誤差
信号dをそのまま出力するか、通常の規定電圧を有する
信号を出力するかの切り替えを行う制御電圧切替器62
とを含んでいる。
Furthermore, the phase error detection means 4 includes an exclusive OR circuit 41 that takes the exclusive OR of two outputs from the phase detector 2, and a phase error that removes high frequency components in the output of this exclusive OR circuit 41. The frequency error detection means 5 includes a delay circuit 51 that provides a predetermined delay to one output of the phase detection circuit 2;
1 and the other output of the phase detection circuit 2; and a synthesis circuit that subtracts the output of the exclusive OR circuit 41 from the output of the exclusive OR circuit 52. 53, and a low-pass filter 54 that removes high frequency components from the output of the synthesis circuit 53 and outputs a frequency error signal d.The control voltage switching means 6 inputs the frequency error signal d and determines the magnitude of the voltage. A control voltage detection circuit 61 that compares the frequency error signal with a predetermined threshold voltage and outputs a switching signal e, and outputs the frequency error signal d as is or outputs a signal having a normal specified voltage according to the input switching signal e. A control voltage switch 62 that switches whether to output
Contains.

次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.

信号入力端子1に加えられた入力信号aは、位相検波器
2に入力され、ここで電圧制御発振器3の出力信号を基
準位相搬送波として位相検波される。位相検波器2の二
つの出力は、位相誤差検出手段4に入力され、排他的論
理和回路41にて論理演算され、位相誤差信号Cが形成
され、低域ろ波器42において高域周波数成分が除去さ
れた後、電圧制御発振器3の第一入力端子7に供給され
、発振周波数を制御するとともに、その一部は周波数誤
差検出手段5の合成回路53に入力される。
Input signal a applied to signal input terminal 1 is input to phase detector 2, where phase detection is performed using the output signal of voltage controlled oscillator 3 as a reference phase carrier. The two outputs of the phase detector 2 are input to the phase error detection means 4, subjected to a logical operation in an exclusive OR circuit 41, a phase error signal C is formed, and a high frequency component is extracted in a low pass filter 42. After being removed, it is supplied to the first input terminal 7 of the voltage controlled oscillator 3 to control the oscillation frequency, and a part of it is input to the synthesis circuit 53 of the frequency error detection means 5.

さらに、位相検波器2の二つの出力は位相誤差検出手段
4間で各々分岐され、一方の信号は、周波数誤差検出手
段5の遅延回路51に入力され、遅延回路51を通過し
た後排他的論理和回路52の一方の入力に入力される。
Further, the two outputs of the phase detector 2 are branched between the phase error detection means 4, and one signal is input to the delay circuit 51 of the frequency error detection means 5, and after passing through the delay circuit 51, the exclusive logic It is input to one input of the summation circuit 52.

位相検波器2のもう一方の出力は、周波数誤差検出手段
5の排他的論理和回路52の他方の入力に入力され、遅
延回路51を通過した信号とで論理演算を施され、合成
回路53に入力される。排他的論理和回路52の出力に
は、周波数誤差信号の他に位相誤差信号Cも含まれてい
るが、合成回路53において位相誤差信号Cは相殺され
、合成回路53の出力は周波数誤差信号dだけとなり、
低域ろ波器54を通して高域周波数成分を除去された後
、制御電圧切替手段6に入力される。
The other output of the phase detector 2 is input to the other input of the exclusive OR circuit 52 of the frequency error detection means 5, is subjected to a logical operation with the signal that has passed through the delay circuit 51, and is sent to the synthesis circuit 53. is input. The output of the exclusive OR circuit 52 includes a phase error signal C in addition to the frequency error signal, but the phase error signal C is canceled out in the synthesis circuit 53, and the output of the synthesis circuit 53 is the frequency error signal d. only,
After high frequency components are removed through the low-pass filter 54, the signal is input to the control voltage switching means 6.

ここで、擬似引込現象が発生した場合には、入力信号a
と基準位相搬送波すとの周波数誤差が非常に大きくなる
ため、周波数誤差検出手段5の出力電圧は高くなるが、
干渉信号や歪みが生じた場合には、周波数誤差は少ない
ため、周波数誤差検出手段5の出力電圧は低くなること
に着目し、制御電圧切替手段6の制御電圧検出回路61
のしきい値電圧をあらかじめ擬似引込現象が生じた場合
の周波数誤差検出手段5の出力電圧と、干渉や歪みが生
じた場合の周波数誤差検出手段5の出力電圧との中間に
設定しておき、周波数誤差検出手段5の出力電圧が、し
きい値電圧より高ければ、擬似引込現象が生じたと判定
し、周波数検出手段5の出力電圧をそのまま第二入力端
子8に入力するように、制御電圧切替器62の出力を切
り替え、電圧制御発振器3の発振周波数を制御する。
Here, if a pseudo-entrainment phenomenon occurs, the input signal a
Since the frequency error between
Focusing on the fact that when an interference signal or distortion occurs, the output voltage of the frequency error detection means 5 becomes low because the frequency error is small, the control voltage detection circuit 61 of the control voltage switching means 6
The threshold voltage of is set in advance to be between the output voltage of the frequency error detection means 5 when a pseudo-entrainment phenomenon occurs and the output voltage of the frequency error detection means 5 when interference or distortion occurs, If the output voltage of the frequency error detection means 5 is higher than the threshold voltage, it is determined that a pseudo pull-in phenomenon has occurred, and the control voltage is switched so that the output voltage of the frequency detection means 5 is directly inputted to the second input terminal 8. The output of the voltage controlled oscillator 3 is switched to control the oscillation frequency of the voltage controlled oscillator 3.

一方、しきい値電圧よりも低い場合には、干渉信号や歪
みが生じていても、同期引込状態であると判定し、基準
位相搬送波すが通常の入力信号aの周波数f。となるよ
うにあらかじめ設定した制御電圧を第二入力端子8に入
力するように、制御電圧切替器62の出力を切り替え、
基準位相搬送波すの周波数をf。に保持する。
On the other hand, if it is lower than the threshold voltage, it is determined that the synchronous pull-in state is present even if an interference signal or distortion occurs, and the reference phase carrier wave is set to the normal frequency f of the input signal a. Switch the output of the control voltage switch 62 so that the control voltage set in advance as follows is input to the second input terminal 8,
The frequency of the reference phase carrier wave is f. to hold.

本実施例では、2相位相同期回路について説明したが、
本発明の位相同期回路は、N相位相同期回路(Nは2以
上の整数)の場合においても同様である。
In this embodiment, a two-phase phase locked circuit was explained, but
The same applies to the phase-locked circuit of the present invention in the case of an N-phase phase-locked circuit (N is an integer of 2 or more).

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、周波数誤差信号
の平均電圧を検出し、入力信号と基準位相搬送波との周
波数誤差が擬似引込現象により生じたものか、あるいは
、干渉信号や歪みにより生じたものかを判定し、擬似引
込現象の場合には、基準位相搬送波の周波数を変化させ
擬似引込現象を回避し、干渉信号や歪みによる場合には
、基準位相搬送波の周波数を保持することにより、擬似
引込現象を起こすことなく、広範囲な同期引込周波数範
囲をもつ位相同期回路を得ることができ、その効果は大
である。
As explained above, according to the present invention, the average voltage of the frequency error signal is detected, and the frequency error between the input signal and the reference phase carrier wave is determined whether the frequency error is caused by a pseudo-entrainment phenomenon or is caused by an interference signal or distortion. If it is a pseudo-entrainment phenomenon, change the frequency of the reference phase carrier wave to avoid the pseudo-entrainment phenomenon, and if it is due to an interference signal or distortion, maintain the frequency of the reference phase carrier wave. It is possible to obtain a phase-locked circuit having a wide synchronous pull-in frequency range without causing a pseudo pull-in phenomenon, and the effect is great.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック構成図。 第2図は従来例を示すブロック構成図。 第3図(a)およびわ)は本発明における入力信号のス
ペクトラムを示す説明図。 1・・・信号入力端子、2・・・位相検波器、3・・・
電圧制御発振器、4・・・位相誤差検出手段、5・・・
周波数誤差検出手段、6・・・制御電圧切替手段、7・
・・第−入力層子、8・・・第二入力端子、41.52
・・・排他的論理和回路、42.54・・・低域ろ波器
、51・・・遅延回路、53・・・合成回路、61・・
・制御電圧検出回路、62・・・制御電圧切替器、a・
・・入力信号、b・・・基準位相搬送波、C・・・位相
誤差信号、d・・・周波数誤差信号、e・・・切替信号
。 夷鞄例 昂 1 圓 徒來ぜ11 昂 2 圓 入力信号スXクトラム 昂 3 回
FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing a conventional example. FIGS. 3(a) and 3(a) are explanatory diagrams showing the spectrum of an input signal in the present invention. 1... Signal input terminal, 2... Phase detector, 3...
Voltage controlled oscillator, 4... Phase error detection means, 5...
Frequency error detection means, 6... Control voltage switching means, 7.
...-th input layer child, 8... second input terminal, 41.52
... exclusive OR circuit, 42.54 ... low-pass filter, 51 ... delay circuit, 53 ... synthesis circuit, 61 ...
- Control voltage detection circuit, 62... Control voltage switch, a.
...Input signal, b...Reference phase carrier wave, C...Phase error signal, d...Frequency error signal, e...Switching signal.夷bag例昂 1 Ensemble 11 昂 2 圓 Input Signal Skutram 昂 3 times

Claims (1)

【特許請求の範囲】 1、入力信号を基準位相搬送波にて位相検波する位相検
波器と、 第一および第二入力端子を有しこれら入力端子に供給さ
れる電圧によって発振周波数を変化させ前記基準位相搬
送波を出力する電圧制御発振器と、前記位相検波器の出
力により前記入力信号と前記基準位相搬送波との位相誤
差を検出し位相誤差信号を生成し前記電圧制御発振器の
第一入力端子に供給する位相誤差検出手段と、 前記位相検波器の出力により前記入力信号と前記基準位
相搬送波との周波数誤差を検出し周波数誤差信号を生成
し前記電圧制御発振器の第二入力端子に供給する周波数
誤差検出手段と を備えた位相同期回路において、 前記周波数誤差信号電圧の大きさを検出しこの検出され
た電圧の大きさをあらかじめ定められたしきい値電圧と
比較して判定しこの判定結果に従って前記電圧制御発振
器の第二入力端子に供給する電圧の大きさを切り替える
制御電圧切替手段を備えた ことを特徴とする位相同期回路。
[Claims] 1. A phase detector that detects the phase of an input signal using a reference phase carrier wave; and a phase detector having first and second input terminals, and changing the oscillation frequency by the voltage supplied to these input terminals, a voltage controlled oscillator that outputs a phase carrier wave; and a phase error between the input signal and the reference phase carrier wave is detected by the output of the phase detector, a phase error signal is generated, and the phase error signal is supplied to a first input terminal of the voltage controlled oscillator. phase error detection means; and frequency error detection means that detects a frequency error between the input signal and the reference phase carrier wave using the output of the phase detector, generates a frequency error signal, and supplies the generated frequency error signal to a second input terminal of the voltage controlled oscillator. Detecting the magnitude of the frequency error signal voltage, determining the magnitude of the detected voltage by comparing it with a predetermined threshold voltage, and controlling the voltage according to the determination result. 1. A phase synchronized circuit comprising control voltage switching means for switching the magnitude of the voltage supplied to a second input terminal of an oscillator.
JP1182042A 1989-07-13 1989-07-13 Phase locked loop circuit Pending JPH0346413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1182042A JPH0346413A (en) 1989-07-13 1989-07-13 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1182042A JPH0346413A (en) 1989-07-13 1989-07-13 Phase locked loop circuit

Publications (1)

Publication Number Publication Date
JPH0346413A true JPH0346413A (en) 1991-02-27

Family

ID=16111327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1182042A Pending JPH0346413A (en) 1989-07-13 1989-07-13 Phase locked loop circuit

Country Status (1)

Country Link
JP (1) JPH0346413A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02117936A (en) * 1983-07-26 1990-05-02 Ciba Geigy Ag Method of using resin composition containing spherical fused silica
US5892474A (en) * 1997-02-26 1999-04-06 Fujitsu Limited Clock phase acquisition/tracking device and phase acquisition method
WO2021130885A1 (en) * 2019-12-25 2021-07-01 ヤマハ発動機株式会社 Component mounting system, tape collection device, and tape collection method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02117936A (en) * 1983-07-26 1990-05-02 Ciba Geigy Ag Method of using resin composition containing spherical fused silica
US5892474A (en) * 1997-02-26 1999-04-06 Fujitsu Limited Clock phase acquisition/tracking device and phase acquisition method
WO2021130885A1 (en) * 2019-12-25 2021-07-01 ヤマハ発動機株式会社 Component mounting system, tape collection device, and tape collection method

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