JPH0661850A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the opportunity of production of a frequency difference and a phase difference before and after input interruption by devising the circuit such that an oscillating output keeping a phase in the normal state just before the interruption on the occurrence of a reference input signal. CONSTITUTION:A delay circuit 12 delays a phase control signal fed from a 1st frequency divider 3 by a multiple of (n) of a phase comparison period in a phase comparator circuit 6. A suppression circuit 14 delays an output signal of the delay circuit 12, that is, the phase control signal from the frequency divider 3 by a time nT to control the phase of a 3rd frequency divider 10. Then the suppression circuit 14 prevents a phase control signal from being given to the frequency divider 10 from the frequency divider 3 before any fluctuation incident within a time nT when a reference signal is interrupted gives any effect on the phase of the frequency division signal from the frequency divider 10. Moreover, a selection circuit 5 selects a frequency division output signal from the frequency divider 10 to be fed to the phase comparator circuit 6 and a control voltage is kept at the interruption of the input.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase locked oscillator,
In particular, the present invention relates to a phase-holding type phase-locked circuit which obtains an oscillation output holding the normal phase immediately before the reference input signal is cut off.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional phase lock circuit of this type. That is, the reference signal is applied from the input terminal 1 to the signal disconnection detection circuit and the first frequency dividing circuit 3. The first frequency divider 3 is a frequency divider that divides the reference signal to the phase comparison frequency, and sends the frequency-divided output signal that is p-divided to the selection circuit 5.

When the input reference signal is normal, the selection circuit 5 supplies the frequency division output signal of the first frequency divider 3 to the phase comparison circuit 6, and the phase comparison circuit 6 divides the output signal of the voltage controlled oscillator 8. A DC signal corresponding to the phase difference between the frequency-divided output signal of the second frequency divider 9 and the frequency-divided output signal of the first frequency divider 3 selected by the selection circuit 5 is generated, and the loop filter 7 A high frequency component is removed and a DC control signal is given to the voltage controlled oscillator 8. The voltage controlled oscillator 8 is controlled by this DC control signal and outputs an oscillation output signal phase-locked with the reference signal from the output terminal 2 to the outside. The output signal of the voltage controlled oscillator 8 is given to the second frequency divider 9 and the third frequency divider 10. The third frequency divider 10 divides the output signal of the voltage controlled oscillator 8 and in accordance with the phase control signal given from the first frequency divider 3 via the inhibition circuit 11 in a state where the reference signal is normally input. , And outputs the divided signal having the smallest phase difference from the output signal of the first division period 3. At the same time, the third frequency divider 10 outputs the output phase of the third frequency divider 10 to the first frequency divider 3.
The phase control signal for adjusting to the output phase of 1 is sent, but when the reference signal is normally input, it is not sent to the first frequency divider 3 by the suppression circuit 11.

When the reference signal is disconnected, the selection circuit 5 sends the frequency division output of the third frequency divider 10 to the phase comparison circuit 6,
The phase comparison circuit 6 compares the frequency-divided output phases of the second frequency divider 9 and the third frequency divider 10 and sends a DC control signal corresponding to the phase difference to the voltage-controlled oscillator 8 for voltage control. It is configured to hold the DC control signal of the oscillator 8.

When the input disconnection is recovered, the first frequency divider 3 and the third frequency divider 10 are connected to each other by the phase control signal given from the third frequency divider 10 to the first frequency divider 3 through the inhibition circuit 11. Since the phases of the divided output signals of are substantially the same, the selection circuit 5
Even if the frequency division output of the first frequency divider 3 is selected again and sent to the phase comparison circuit 6, the output of the voltage controlled oscillator 8 is hardly affected.

[0006]

In the conventional phase locked loop circuit described above, the transition of the reference signal from the normal state to the disconnection state occurs instantaneously, and the signal disconnection detection circuit 4 can detect such disconnection without delay. If so, there is no problem, but in fact, as shown in Fig. 2, fluctuations in frequency and phase before the signal is completely cut off,
In many cases, a signal loss occurs after a disturbance such as a missing bit gradually occurs. In the conventional phase-locked loop, the period from the occurrence of the disturbance of the reference signal until the signal loss detection circuit detects the loss is the first minute. Since the phase control signal sent from the first frequency divider 3 is improperly changed so that the frequency division output phase of the frequency divider 3 matches the frequency division output phase of the third frequency divider 10, the third frequency divider is applied. There is a problem that the frequency division output phase of 10 fluctuates and adversely affects the DC control signal given to the voltage controlled oscillator 8.

[0007]

The circuit of the present invention comprises a first frequency divider for dividing an input reference signal having a constant frequency, a second frequency divider for dividing an output signal, and the second frequency divider. Comparator for outputting a DC control signal corresponding to the phase difference between the output signal of the frequency divider and the output signal of the first frequency divider, and a voltage controlled oscillator for varying the frequency of the output signal in response to the DC control signal And a signal disconnection detection circuit for detecting an input disconnection of the reference signal, and a control voltage holding means for holding the DC control signal immediately before the input disconnection of the reference signal, The phase control signal output from the one frequency divider is n times the cycle T of the output signal of the second frequency divider (n = 1, 2,
3)) and a delay circuit for delaying the output signal of the voltage controlled oscillator by a time corresponding to 3), and an output signal of the delay circuit, which has the smallest phase difference from the output signal of the first frequency divider. A third frequency divider that outputs a frequency output, and a selection circuit that selectively selects an output signal of the third frequency divider or the first frequency divider and inputs the output signal to the phase comparison circuit, When the input of the reference signal is cut off, the control voltage is held so that the DC control signal is output from the phase comparison circuit corresponding to the phase difference between the output signal of the third frequency divider and the output signal of the second frequency divider. It is characterized in that the means is configured.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, blocks to which the same reference numerals as in FIG. 3 are given are the same as those in the conventional circuit of FIG.

In the delay circuit 12 of this embodiment, the phase control signal sent from the first frequency divider 3 is n times the phase comparison cycle T in the phase comparison circuit 6 (n = 1, 2, 3 ...). It's delayed. The suppression circuit 14 differs from the conventional circuit in that the delay circuit 12
Output signal, that is, the phase control signal output from the first frequency divider 3 is delayed by time nT to control the phase of the third frequency divider 10.

In this way, any fluctuation that occurs within the time nT before the reference signal is cut off will not be affected by the third frequency divider 1.
The suppression circuit 14 prevents the phase control signal from being sent from the first frequency divider 3 to the third frequency divider 10 before affecting the phase of the frequency divided signal of 0, and the selection circuit 5 causes the third frequency divider 3 to The frequency division output signal of the frequency divider 10 is switched to be sent to the phase comparison circuit 6,
The control voltage can be held when the input is cut off.

[0012]

As described above, according to the present invention, the disturbance period such as frequency and phase fluctuations which may occur in the reference signal within the time nT immediately before the reference signal is completely cut off, and the signal group detection circuit are provided. By suppressing the influence of the disconnection detection delay time on the control voltage holding output to the voltage controlled oscillator when the input is disconnected, it is possible to reduce the frequency / phase difference of the voltage controlled oscillator before and after the input disconnection.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a signal timing diagram for explaining the operation of the present invention and the conventional circuit.

FIG. 3 is a block diagram of a conventional phase locked loop circuit.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 3 First Frequency Divider 4 Signal Loss Detection Circuit 5 Selection Circuit 6 Phase Comparison Circuit 7 Loop Filter 8 Voltage Controlled Oscillator 9 Second Frequency Divider 10 Third Frequency Divider 11, 14 Suppression Circuit 12 Delay circuit

Claims (2)

[Claims] 1. A first divider for dividing an input reference signal having a constant frequency, a second divider for dividing an output signal, and the second divider.
A phase comparison circuit that outputs a DC control signal corresponding to the phase difference between the output signal of the frequency divider and the output signal of the first frequency divider, and a voltage that varies the frequency of the output signal in response to the DC control signal. In a phase locked loop circuit including a control oscillator, a signal break detection circuit that detects an input break of the reference signal, and a control voltage holding unit that holds the DC control signal immediately before the input break of the reference signal, The phase control signal output from the first frequency divider is applied to the second frequency divider.
N times the cycle T of the output signal of the frequency divider (n = 1, 2, 3 ...)
And a delay circuit for delaying the output signal of the voltage controlled oscillator by a time corresponding to the above, and a frequency division output having the smallest phase difference from the output signal of the first frequency divider by the output signal of the delay circuit. A third frequency divider for outputting and a selection circuit for selectively selecting the output signal of the third frequency divider or the first frequency divider and inputting it to the phase comparison circuit, The control voltage holding means is configured to output the DC control signal from the phase comparison circuit corresponding to the phase difference between the output signal of the third frequency divider and the output signal of the second frequency divider when the input is cut off. A phase-locked loop circuit characterized by the above. 2. The control voltage holding means allows the output signal of the delay circuit to pass through the third frequency divider when the reference signal is normally input, and outputs the output signal from the third frequency divider to the first frequency divider. The phase control signal is suppressed, and when the input is cut off, the output signal from the delay circuit to the third frequency divider is suppressed so that the phase control signal from the third frequency divider is passed to the first frequency divider. 2. The phase locked loop circuit according to claim 1, wherein the output signal of the first frequency divider is controlled so as to output a frequency division output having the smallest phase difference from the output signal of the third frequency divider.