JP2003258629A - Pll circuit and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily reduce the PLL output phase fluctuation width at a momentary break of an input reference signal, without using a high performance PLL circuit such as for hold over. <P>SOLUTION: A momentary break detector 2 detects a momentary break of an input reference signal, to fix the output of a primary loop gain unit 4 to '0'. After recovery from the momentary break, it cancels the output fixing of the loop gain unit 4 and resets the counter of a frequency divider to control for forcibly matching the phase, thereby suppressing the PLL output phase fluctuation, when a momentary break is detected. The suppressed phase fluctuation width at this time depends on a momentary break detection time of the momentary break detector 2, if the gains of a primary and secondary loops and the frequency division ratio of the frequency divider are determined. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit and a control method thereof, and more particularly to phase comparison between an input signal and a frequency-divided output of a frequency-controlled oscillator frequency divider, and a result of the comparison is referred to as a primary loop gain section. A secondary type P which is used as a control signal of a voltage controlled oscillator via a secondary loop gain section.
The present invention relates to an LL circuit and a control method thereof.

[0002]

2. Description of the Related Art A conventional secondary type PLL circuit of this type will be described with reference to FIG. Referring to FIG. 4, a reference signal, which is an input signal, is a phase comparator (PD) 3
At, the phase of the signal from the voltage controlled oscillator (VCO) 9 is compared with the frequency divided signal by the frequency divider 7. The result of the phase comparison by the phase comparator 3 is the primary loop gain unit 4
To the input of the adder 6. The output of the primary loop gain unit 4 is input to the secondary loop gain unit 5, and the output of the secondary loop gain unit 5 becomes the other input of the adder 6.

The addition output of the adder 6 becomes an analog signal by the digital / analog converter (D / A) 8,
It is used as a control signal for the voltage controlled oscillator 9. The output of the voltage controlled oscillator 9 is the output signal of the PLL circuit, and this output signal is frequency-divided by the frequency divider (1 / N) 7 and becomes the other input of the phase comparator 3. The phase comparator 3, the primary loop gain unit 4, the secondary loop gain unit 5, the adder 6 and the frequency divider 7 are the digital signal processing unit 1.
Are configured.

In such a PLL circuit, when the input reference signal and the PLL reproduction signal obtained by dividing the output of the voltage controlled oscillator 9 by the frequency divider 7 match in frequency and phase, the phase comparator 3 In the phase difference “0” control, the phase difference is calculated by the primary loop gain unit 4 and the secondary loop gain unit 5, respectively, and the result is output to the adder 6. The adder 6 adds the phase difference calculation results from the primary loop gain unit 4 and the secondary loop gain unit 5, and outputs the result to the D / A converter 8. D /
In the A converter 8, the digital signal from the digital signal processing unit 1 is converted into an analog signal, which then becomes the control voltage of the voltage controlled oscillator 9 and the input reference according to the phase difference data from the digital signal processing unit 1. A signal whose frequency and phase match the signal is reproduced.

[0005]

If a momentary interruption occurs in the input reference signal, the phase comparator 3 detects the phase difference corresponding to the momentary interruption time and outputs it to the primary loop gain unit 4. . In the primary loop gain unit 4, amplification processing is performed based on the phase difference data from the phase comparator 3,
It is output to the secondary loop gain unit 5. Since the loop gain of the secondary loop gain unit 5 is set to be extremely smaller than that of the primary loop gain unit 4, the phase difference data actually added by the adder 6 is output to the output of the primary loop gain unit 4. It becomes almost equal. After all, when the input reference signal is instantaneously interrupted, the phase difference detected by the phase comparator 3 is equal to PL processed by the primary loop gain unit 4.
The L output phase will change.

In order to suppress the fluctuation of the PLL output phase due to the occurrence of such an instantaneous interruption of the input reference signal,
For example, it is necessary to use a highly functional PLL such as holdover. Such a highly functional PLL has a drawback that the circuit configuration is complicated and the cost is high.

An object of the present invention is to provide a PLL circuit and a control method therefor capable of suppressing an output phase fluctuation when an instantaneous interruption of an input reference signal occurs at an extremely simple and low cost without using a highly functional PLL. Is to provide.

[0008]

In a PLL circuit according to the present invention, a phase comparison between an input signal and a frequency-divided output by a frequency-controlled oscillator frequency divider is performed, and the comparison result is used as a primary loop gain section and a secondary loop. A secondary type PLL circuit adapted to use as a control signal of the voltage controlled oscillator via a gain section, wherein the output of the primary loop gain section is fixed to a predetermined value in response to a momentary interruption of the input signal. In addition, in response to the restoration from the instantaneous interruption, the output of the primary loop gain unit is released and the frequency divider is reset, and an instantaneous interruption detection unit is included.

Further, in the control method according to the present invention, the phase comparison between the input signal and the frequency-divided output by the frequency divider of the voltage-controlled oscillator is performed, and the comparison result is compared between the primary loop gain section and the secondary loop gain section. A method of controlling a secondary type PLL circuit, wherein a control signal of the voltage controlled oscillator is used as a control signal, wherein the output of the primary loop gain unit is fixed to a predetermined value in response to a momentary interruption of the input signal. And releasing the fixing of the output of the primary loop gain unit and resetting the frequency divider in response to the recovery from the instantaneous interruption.

The operation of the present invention will be described. If the output of the primary loop gain section is fixed to "0" which is a predetermined value when the instantaneous reference signal is detected and the output is detected, the output of the primary loop gain section is released after the recovery from the interruption. At the same time, the counter of the frequency divider is reset to force the phase adjustment. By doing so, it is possible to suppress the fluctuation of the PLL output phase at the time of instantaneous interruption.

At this time, if the instantaneous interruption detection time is long, the PLL
If the output phase fluctuation amount is large and short, there is a possibility of false detection due to jitter / wander. Further, the phase fluctuation width at the time of instantaneous interruption is determined by the primary loop gain, the secondary loop gain, and the frequency division ratio of the frequency divider. Therefore, if the PLL output phase fluctuation width to be suppressed is determined, The fluctuation range will also be determined. Since this input phase fluctuation range corresponds to the instantaneous interruption detection time of the input reference signal, the PLL output phase variation range is determined by setting the instantaneous interruption detection time in the instantaneous interruption detector. Therefore, when a momentary interruption occurs in the input reference signal, the PLL output phase fluctuation can be suppressed to the arbitrarily set phase fluctuation width.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and the same portions as those in FIG. 4 are designated by the same reference numerals. Explaining only the parts different from FIG. 4, the instantaneous interruption detector 2 for detecting the instantaneous interruption of the input reference signal is provided. When a momentary interruption is detected in the momentary interruption detector 2, a reset signal for fixing the output to “0” is generated for the primary loop gain unit 4, and the output fixation is released after the momentary interruption is restored. At the same time, control is performed so that the counter of the frequency divider 7 is reset.
Other configurations are the same as those in FIG. 4, and the description thereof will be omitted.

In such a structure, during normal operation in which no instantaneous interruption occurs in the input reference signal, P in FIG.
The same operation as the LL circuit is performed. In this state,
When a momentary interruption occurs in the input reference signal, it is detected by the momentary interruption generator 2, and in response thereto, control is performed to fix the output of the primary loop gain unit 4 to a predetermined value "0". When the instantaneous disconnection is restored, the output of the primary loop gain unit 4 is released, and at the same time, the counter of the frequency divider 7 is reset to forcibly perform phase matching control.

In the present PLL circuit, the instantaneous interruption detector 2 is connected to the phase comparator 3 in order to monitor the instantaneous interruption of the input reference signal.
However, as described above, if the instantaneous interruption detection time in the instantaneous interruption detector 2 is set to be long, the PLL output phase fluctuation amount becomes large, and if it is short, erroneous detection due to jitter / wander may occur. There is a fact that. There is also the fact that the PLL output phase fluctuation width at the time of occurrence of an instantaneous interruption is determined by the gains of the primary loop and secondary loop gain units, the frequency division ratio of the frequency divider 7, and the like.

Therefore, P to be suppressed when an instantaneous interruption occurs
It can be said that the LL output phase fluctuation range is determined by the instantaneous interruption detection time of the instantaneous interruption detector 2 if the gains and frequency division ratios of the primary loop and secondary loop sections are determined. Therefore, in the present PLL circuit, by setting the momentary interruption detection time of the momentary interruption detector 2 to a desired value, it becomes possible to suppress the PLL output phase fluctuation width accordingly.

FIG. 2 is a functional block diagram of the primary loop gain section 4 applied to the PLL circuit of another embodiment of the present invention. The primary loop gain unit 4 includes a first primary amplifier unit (normal time) 41 having a gain n and a gain m (n> n).
m), a second primary amplifier section (when phase fluctuation slope is guaranteed) 42, a selecting section 43 for selecting either one of the amplifier sections 41, 42 to enter a loop, and a timer 4
It consists of 4.

In a normal state in which the input reference signal is not interrupted, the selection unit 43 operates as the first primary amplifier unit 41.
Is selected to enter the loop, and the primary loop gain at that time is “n”. When the instantaneous interruption detector 2 detects an instantaneous interruption, the first primary amplifier section 41 is reset and its output is fixed to "0". When the phase fluctuation of the PLL output is controlled only by the amplitude (quantity), there is no problem in the operation of fixing the output of the primary loop gain amplifier unit to "0", that is, the operation of the embodiment shown in FIG. .

However, when it is desired to set and control the PLL output phase fluctuation in addition to the amplitude, the slope of the PLL output phase fluctuation can be restored at the same time as the gain of the primary amplifier is temporarily lowered.
For example, by setting "m" (m <n), the PLL
The slope of output phase fluctuation can be suppressed.

Therefore, in addition to the primary amplifier section 41 for normal operation, a primary amplifier section 42 for ensuring phase fluctuation slope is provided separately, and its gain is set to "m" lower than "n" and instantaneous interruption occurs. The timer 44 is operated for a fixed time after the restoration, and during that period, the primary amplifier unit 42 at the time of guaranteeing the phase fluctuation slope is
Is selected by the selection unit 43 so that the loop is controlled.

The state at this time is shown in FIG. 3 of the timing chart, and FIG. 3A is a timing chart when the phase fluctuation inclination is not guaranteed (operation of the embodiment of FIG. 1).
FIG. 9B is a timing chart when the phase fluctuation inclination is guaranteed.

In this way, in this embodiment, not only the width (amount) of the PLL output phase fluctuation at the time of restoration of the instantaneous interruption of the input reference signal, but also the inclination thereof can be controlled, and in addition to the suppression of wander generation, It will also be possible to suppress jitter.

[0022]

As described above, according to the present invention, even if a high-performance PLL circuit such as a holdover function is not used, if the input reference signal is instantaneously interrupted, the PLL can be used.
There is an effect that the output phase fluctuation can be suppressed to an arbitrarily set width (amount). The reason is that the instantaneous interruption of the input reference signal is constantly monitored, and the phase suppression variation process is performed on the primary loop gain and the frequency divider.

Further, by setting the gain of the primary loop gain unit to be lower than that in the normal state for a certain period of time when the instantaneous interruption is restored, it is possible to control not only the PLL output phase fluctuation width but also its inclination. There is also an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a primary loop gain unit used in another embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional PLL circuit.

[Explanation of symbols]

1 Digital signal processor 2 Instantaneous interruption detector 3 Phase comparator 4 Primary loop gain section 5 Secondary loop gain section 6 adder 7 divider 8 D / A converter 9 Voltage controlled oscillator 41 First primary amplifier section 42 Second primary amplifier section 43 Selector 44 timer

Claims (9)

[Claims] 1. A phase comparison between an input signal and a frequency-divided output by a frequency divider of a voltage-controlled oscillator, and a result of this comparison is passed through a primary loop gain unit and a secondary loop gain unit. Secondary type PLL adapted to control signal
A circuit, wherein the output of the primary loop gain unit is fixed to a predetermined value in response to a momentary interruption of the input signal, and the output of the primary loop gain unit is released from being fixed in response to a momentary interruption recovery. A PLL circuit including a momentary interruption detecting means for resetting the frequency divider. 2. The PLL circuit according to claim 1, wherein the predetermined value is a value indicating that the phase difference is “0”. 3. The PLL circuit according to claim 1, wherein the momentary interruption detection time in the momentary interruption detection means is a predetermined time. 4. The PLL according to claim 1, wherein the gain of the primary loop gain unit is set to be smaller than the normal gain for a predetermined period in response to the recovery from the instantaneous interruption. circuit. 5. The primary loop gain section includes a first amplifier section having the normal gain, a second amplifier section having a gain smaller than the normal gain, and the second amplifier section for the predetermined period. 5. The PL according to claim 4, further comprising means for switching the amplifier section of the switch so as to enter a loop.
L circuit. 6. A phase comparison between an input signal and a frequency-divided output by a frequency divider of the voltage-controlled oscillator, and a result of this comparison is passed through a primary loop gain unit and a secondary loop gain unit. Secondary type PLL adapted to control signal
A method for controlling a circuit, comprising: fixing an output of the primary loop gain unit to a predetermined value in response to a momentary interruption of the input signal; fixing an output of the primary loop gain unit in response to a momentary interruption recovery. And releasing the frequency divider, the control method is also provided. 7. The control method according to claim 6, wherein the predetermined value is a value indicating that the phase difference is “0”. 8. The momentary interruption detection time of the input signal is a predetermined time.
The described control method. 9. The method according to claim 6, further comprising the step of setting the gain of the primary loop gain unit to be smaller than the normal gain for a predetermined period in response to the recovery from the instantaneous interruption. Either of the control methods.