JP2004260321A - Synchronization detecting circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization detecting circuit capable of properly detecting a synchronizing signal even when a deviation takes place in the phase of a timing pulse for detecting a pedestal level. <P>SOLUTION: In the synchronization detecting circuit for detecting the synchronizing signal on the basis of a threshold value decided by the pedestal level detected from the timing pulse and a minimum value level (SYNC chip level) in a video signal, whether or not an interval of a detected horizontal synchronizing signal is normal is discriminated. Thus, it is discriminated that the synchronizing signal is not normally detected due to the deviation in the phase of the timing pulse. Further, the synchronizing signal can be detected properly even with a fault by detecting the synchronizing signal on the basis of a second threshold value decided according to, for example, the SYNC chip level according to this discriminated result. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a synchronization detection circuit in a television receiver. The present invention also relates to a synchronization detection method in such a synchronization detection circuit.
[0002]
[Prior art]
A television receiver is provided with, for example, a sync separation circuit for separating and extracting a horizontal / vertical sync signal from an input composite signal. In such a synchronization separation circuit, a circuit system for separating a horizontal synchronization signal includes a synchronization detection circuit for detecting a horizontal synchronization signal included in a video signal.
FIG. 10 is a diagram schematically illustrating an example of a waveform of a video signal (composite signal) input to such a synchronization detection circuit.
First, FIG. 10A shows an example of a waveform when a video signal is normally received by the television receiver. In this figure, the L1 level shown first is a pedestal level called a so-called black level.
Further, the horizontal synchronizing signal is superimposed on the video signal at a position where the pedestal level becomes higher or lower as shown in the figure so as to correspond to one horizontal scanning cycle (1H). Then, as shown in the figure, a section in which the video signal is at the minimum value level, which is indicated by L2 in the figure, is a section as a horizontal synchronization signal, that is, a horizontal synchronization signal section. In a video signal, a minimum value level corresponding to a horizontal synchronization signal section is also called a so-called sync chip level.
For this reason, in the above-described synchronization detection circuit, a threshold (th in the figure) corresponding to such a minimum value level in the video signal is set to detect the horizontal synchronization signal.
[0003]
However, at this time, a normal synchronization signal may not be obtained as a video signal as shown in, for example, FIGS. 10B and 10C due to a weak electric field, ghost, transmission system distortion, and the like.
For example, in the case shown in FIG. 10B, the minimum value level of the video signal is less than the normal level shown in FIG. Then, in this case, even if the detection is performed with the threshold value th set as described above, there is a possibility that the synchronization signal cannot be detected as shown in the figure.
Further, in the example shown in FIG. 10C, the level of the synchronization signal is disturbed. In this case, if the detection is performed at the level of the threshold th, the synchronization signal section is detected shorter than the normal state as shown in the figure. It will be.
[0004]
In order to cope with such a problem, in the related art, for example, there is a configuration in which a threshold value for synchronization detection is adaptively changed according to the level of a horizontal synchronization signal of an input video signal. (See Patent Document 1 below).
[0005]
FIG. 11 is a block diagram of the synchronization detection circuit 100 configured to change the threshold value for detecting the synchronization signal.
In this figure, first, a composite signal cs as a video signal is input to a sample hold circuit 101 and a minimum value detection circuit 102 as shown in the figure.
The sample and hold circuit 101 detects a pedestal level in the composite signal cs based on a timing pulse tp generated based on an output of a PLL (Phase Locked Loop) block 110 described later. This is output to the synchronization signal level estimation circuit 103.
The minimum value detection circuit 102 detects the minimum value level of the composite signal cs and outputs the same to the synchronization signal level estimation circuit 103.
[0006]
The synchronizing signal level estimating circuit 103 outputs the sample and hold circuit output sh as the pedestal level output from the sample and hold circuit 101 and the minimum as the minimum value (sync chip level) output from the minimum value detecting circuit 102 as described above. The value circuit output ss is input, and the level of the synchronization signal is calculated from, for example, the difference between them. Then, the calculated synchronization signal level is supplied to the threshold value determination circuit 104.
[0007]
The threshold value determination circuit 104 calculates a threshold value th for detecting a synchronization signal by performing a required operation on the supplied synchronization signal level value. Then, the threshold value th thus calculated is output to the synchronization detector 105.
[0008]
The synchronization detector 105 detects a synchronization signal based on the input composite signal cs and the threshold th. That is, a portion exceeding the threshold th in the input composite signal cs is detected as a horizontal synchronization signal section, and this is output as a synchronization signal output D.
[0009]
The PLL block 110 generates various operation clocks based on the synchronization signal output D output from the synchronization detector 105.
In the PLL block 110, the output cycle of the synchronization signal output D output from the synchronization detector 105 is input to the phase detection circuit 111 as a reference frequency.
The phase detection circuit 111 outputs an output (frequency of an oscillation signal) of a VCO (voltage controlled oscillator) 113 frequency-divided at a predetermined ratio of 1 / N according to a division period 114 shown in FIG. The output D is compared with the frequency, and a detection signal corresponding to the phase difference is output to the filter 112.
The filter 112 generates a voltage level according to the phase difference by passing only a predetermined low-frequency component of the detection signal input from the phase detection circuit 111, and outputs the voltage level to the VCO 113. The VCO 113 varies the frequency of the oscillation signal by correcting the phase difference detected by the phase detection circuit 111 according to the input voltage level.
As a result, the PLL block 110 operates to lock the phase so that the phase matches the reference frequency. That is, the output of the oscillation signal of the VCO 113 operates so as to be synchronized with the synchronization signal output D input as the reference frequency.
[0010]
The output pulse of the VCO 113 is supplied to each unit as an output of the PLL block 110. In particular, the output to the synchronization detection circuit 100 in this case is input to the timing pulse generation circuit 115 as illustrated.
The timing pulse generation circuit 115 generates the timing pulse tp for detecting the pedestal level based on the pulse corresponding to the period of the synchronization signal input from the PLL block 110 as described above.
At this time, the timing pulse generation circuit 115 generates, for example, a delay pulse based on a pulse corresponding to the cycle of the input synchronization signal as described above, so that the section where the composite signal cs is at the pedestal level is generated. Is generated.
[0011]
FIG. 12 is a timing chart for explaining the operation of the synchronization detection circuit 100 configured as described above.
In FIG. 12, FIG. 12A schematically shows a composite signal cs input to the synchronization detection circuit 100. As described above, in this composite signal cs, the illustrated L1 level is The pedestal level is set, and the L2 level is set as the sync tip level. The portion where the composite signal cs is at the L2 level (period A in the figure) is a synchronization signal section.
In this case, the same composite signal cs shown in FIG. 12A is also shown in FIG. 12C as shown.
The timing pulse tp shown in FIG. 12 (b) is a delay pulse based on the synchronization signal output D (FIG. 12 (f)) as described above. The signal is obtained corresponding to the section where the signal cs is at the pedestal level.
[0012]
The output sh of the sample hold circuit 101 shown in FIG. 12C indicates the level of the composite signal cs at the timing when the timing pulse tp goes to the H level. As a result, a level corresponding to the pedestal level can be obtained as the sample hold output as shown in FIG.
Also, a level corresponding to the sync tip level (L2) is obtained as the minimum value circuit output ss shown in FIG. 12C, and the threshold value th shown in FIG. The value is set, for example, as shown in FIG.
[0013]
Here, as shown at time t1 in the figure, since the timing pulse tp is obtained corresponding to the section where the composite signal cs is at the pedestal level, the sample hold circuit 101 shown in FIG. Detects the pedestal level of the composite signal cs input in response thereto.
Then, the synchronization signal level estimating circuit 103 calculates the level of the synchronization signal based on the sample and hold circuit output sh as the pedestal level thus detected and the minimum value circuit output ss as the sync tip level. To be.
Then, the threshold value determination circuit 104 determines the threshold value th of the level as shown in FIG. 12C by performing arithmetic processing based on the level of the synchronization signal thus calculated. .
That is, in this case, it is possible to determine an optimum threshold value according to the actual synchronization signal level detected from the input composite signal cs.
[0014]
Then, the synchronization detector 105 detects a section in the input composite signal cs that exceeds the level of the threshold value th calculated in this way, as shown at a time point t2 to t3 in the figure, and A synchronization signal output D shown in FIG. 12 (d) is output.
[0015]
In this manner, in the conventional synchronization detection circuit 100, the threshold th for detecting the synchronization signal is set according to the pedestal level and the minimum value level (sync tip level) in the input video signal. . That is, the threshold value th for detecting the synchronization signal is variably set according to the actual level of the synchronization signal.
The threshold value th is variably set in accordance with the actual level of the synchronization signal in this manner, so that, for example, even when the signals shown in FIGS. The synchronization signal can be detected.
[Patent Document 1]
JP 2000-152027A
[0016]
[Problems to be solved by the invention]
Here, when the threshold value th is variably set based on the sync tip level and the pedestal level in the video signal as described above, the sync tip level is obtained by detecting the minimum value of the video signal. Can be.
On the other hand, the pedestal level is detected based on the timing pulse tp generated based on the output of the PLL block 110.
Therefore, in this case, if such a phase shift occurs in the timing pulse tp, the sample-and-hold circuit 101 may detect an erroneous portion in the video signal as a pedestal level.
[0017]
This will be described with reference to FIG. 12. First, as shown at time t4 in the figure, in response to the timing pulse tp being obtained in the video section of the composite signal cs, for example, In the hold circuit 101, the level of this video section is detected as a pedestal level (FIG. 12C).
When the level of the video section is detected as the pedestal level in this manner, the level of the threshold th for synchronization detection shown in FIG. 12C increases as shown in the figure.
As a result, the synchronization detector 105 that performs synchronization signal detection based on the level of the threshold th detects an erroneous portion in the composite signal cs as a synchronization signal section as shown at time points t5 to t6.
Thereafter, while an erroneous value is set as the threshold value th due to the phase shift of the timing pulse tp, the synchronization signal section is erroneously detected as shown at time t7-t8 in the figure. It will be.
[0018]
The erroneous detection of the synchronizing signal affects the operation of the PLL block 110 that inputs the synchronizing signal output D as the reference frequency. In other words, a deviation occurs between the synchronization signal cycle of the actual composite signal cs and the output pulse of the PLL block 110.
As a result, the timing pulse tp generated based on the output of the PLL block 110 is further shifted, and as a result, the operation of the PLL block 110 becomes unstable and becomes normal. The convergence to a proper phase is greatly delayed.
[0019]
It is to be noted that such a shift of the timing pulse tp can easily occur, for example, when a receiving channel is switched in a television receiver, or due to a head skew of a VTR.
That is, from this, it can be said that the conventional synchronization detection circuit 100 has a possibility that erroneous detection of the horizontal synchronization signal section occurs with a relatively high probability as described above. Therefore, in consideration of detecting the horizontal synchronization signal section with as high accuracy as possible while avoiding erroneous detection of the horizontal synchronization signal section, first, it is possible to determine whether or not the horizontal synchronization signal section is properly detected. Is required.
[0020]
[Means for Solving the Problems]
Therefore, in the present invention, the synchronization detection circuit is configured as follows.
That is, first, in order to detect the level of the horizontal synchronization signal included in the input video signal, minimum value level detection means for detecting the minimum value level of the input video signal, and a pedestal in the input video signal Pedestal level detecting means for detecting the level of the input video signal at a predetermined timing based on a detection cycle of the horizontal synchronization signal by the synchronization detection circuit to detect the level.
A first threshold value determining unit that determines a first threshold value for detecting the horizontal synchronization signal based on the levels detected by the minimum value level detecting unit and the pedestal level detecting unit; At least the first threshold value determined by the first threshold value determination means is input, and the input video is input based on a result of comparing the input threshold value with the level of the input video signal. A first synchronizing signal detecting means for detecting a horizontal synchronizing signal in the signal.
Then, a section length detecting means for detecting a section length of the horizontal synchronization signal detected by the first synchronization signal detecting means, and a section in which the section length detected by the section length detecting means is normal. A determination unit for determining whether the length is long.
[0021]
Further, according to the present invention, a synchronization detection method in the synchronization detection circuit is as follows.
That is, in order to detect the level of the horizontal synchronization signal included in the input video signal, the minimum value level detection procedure for detecting the minimum value level of the input video signal, and the pedestal level in the input video signal In order to perform the detection, a pedestal level detection procedure for detecting the level of the input video signal is executed at a predetermined timing based on the detection cycle of the horizontal synchronization signal.
A first threshold value determining step for determining a first threshold value for detecting the horizontal synchronization signal based on the levels detected by the minimum value level detecting step and the pedestal level detecting step; A first synchronization that detects a horizontal synchronization signal in the input video signal based on a result of comparing the level of the video signal to be input and at least the first threshold determined in the first threshold determination procedure. And a signal detection procedure.
Then, a section length detection procedure for detecting the section length of the horizontal synchronization signal detected by the first synchronization signal detection procedure, and a section length detected by the section length detection procedure are determined to be normal section lengths. And a determination procedure for determining whether or not there is an instruction.
[0022]
According to the above configuration, it is determined whether or not the section length of the synchronization signal section detected from the input video signal is normal. That is, as described above, it is possible to determine that the phase shift occurs in the timing pulse as described above, and that the detection of the synchronization signal is not normally performed due to the setting of an incorrect threshold value.
Then, in response to the determination that the section length of the synchronization signal is not normal, the detection of the synchronization signal is performed based on the second threshold value determined based on, for example, the minimum value level (sync tip level) detected from the video signal. Is performed, it is possible to prevent the synchronization signal from being erroneously detected based on the threshold value determined to be an erroneous value as described above.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram illustrating a configuration example of a synchronization detection circuit 1 according to a first embodiment of the present invention.
The synchronization detection circuit 1 shown in FIG. 1 is included in a television receiver, for example, in a synchronization separation circuit system for separating and extracting a horizontal / vertical synchronization signal from an input composite signal. Then, a horizontal synchronizing signal included in the video signal is detected by being included in such a synchronization separating circuit system.
First, in FIG. 1, the sample hold circuit 2 detects a pedestal level in an input video signal. For example, a composite signal cs as shown in FIG. 2A is input to the sample and hold circuit 2 as the video signal.
In the composite signal cs, the level L1 shown in FIG. 2A is a pedestal level (black level), and the level L2 is a sync tip level. A portion (period A in the figure) where the composite signal cs is at the sync chip level (level L2) is defined as a synchronization signal section.
[0024]
Further, a timing pulse tp for detecting the pedestal level is also supplied to the sample and hold circuit 2. In this case, the timing pulse tp is generated, for example, based on the output of a PLL (Phase Locked Loop) block not shown here.
[0025]
Here, the PLL block has the same configuration as the PLL block 110 described in FIG.
That is, in such a PLL block 110, first, the output cycle of the synchronization signal output which is the output of the synchronization detection circuit is input to the phase detection circuit 111 shown in FIG. 11 as a reference frequency. That is, in this case, the synchronization signal output D output from the synchronization detection circuit 1 is input as described later.
The phase detection circuit 111 synchronizes the output (frequency signal of the oscillation signal) of the VCO (voltage controlled oscillator) 113 divided by a predetermined ratio of 1 / N with the divided period 114 shown in FIG. The signal output D is compared with the frequency of the signal output D, and a detection signal corresponding to the phase difference is output to the filter 112 shown in the figure.
The filter 112 generates a voltage level according to the phase difference by passing only a predetermined low-frequency component of the detection signal input from the phase detection circuit 111, and outputs the voltage level to the VCO 113. The VCO 113 varies the frequency of the oscillation signal by correcting the phase difference detected by the phase detection circuit 111 according to the input voltage level.
As a result, the PLL block 110 operates to lock the phase so that the phase matches the reference frequency. That is, the output of the oscillation signal of the VCO 113 operates so as to be synchronized with the synchronization signal output D input as the reference frequency.
[0026]
The output pulse of the VCO 113 is supplied to each unit as an output of the PLL block 110. Also in this case, the output to the synchronization detection circuit 1 is input to the timing pulse generation circuit 115 as illustrated.
The timing pulse generation circuit 115 generates the timing pulse tp for detecting the pedestal level based on the pulse corresponding to the period of the synchronization signal input from the PLL block 110. That is, also in this case, the timing pulse generating circuit 115 generates a composite signal cs at a pedestal level by generating, for example, a delay pulse based on a pulse corresponding to the cycle of the input synchronization signal as described above. A timing pulse tp corresponding to an existing section is generated.
[0027]
Thereby, the timing pulse tp having a pulse cycle corresponding to the section where the composite signal cs is at the pedestal level is input to the sample-hold circuit 2 shown in FIG. 1, for example, as shown in FIG. It has become so.
[0028]
In FIG. 1, the sample-and-hold detection circuit 2 to which such a timing pulse tp is inputted detects the pedestal level by detecting (holding) the level of the composite signal cs at the timing when the timing pulse tp is supplied. To be done. Then, such a detection output is supplied to the synchronization signal level estimating circuit 4 as a sample and hold circuit output sh shown in the figure.
[0029]
The minimum value detection circuit 3 detects the sync chip level by detecting the minimum value level of the composite signal cs. Then, as shown in the figure, the minimum value circuit output ss is supplied to each of the synchronization signal level estimation circuit 4 and the second threshold value determination circuit 6.
[0030]
The synchronizing signal level estimating circuit 4 inputs the sample and hold circuit output sh as the pedestal level and the minimum value circuit output ss as the sync tip level supplied as described above, and obtains the level of the synchronizing signal from the difference therebetween. Is calculated. Then, the synchronization signal level thus calculated is supplied to the first threshold value determination circuit 5.
[0031]
The first threshold value determination circuit 5 calculates a first threshold value th1 for detecting a synchronization signal by performing a required operation on the supplied synchronization signal level value. Then, the first threshold value th1 calculated in this way is supplied to the terminal t1 of the switch SW.
[0032]
The second threshold value determination circuit 6 determines a value offset from the minimum value circuit output ss supplied from the minimum value detection circuit 3 by the illustrated offset value α as the second threshold value th2 as described above. Then, the second threshold value th2 determined in this way is supplied to the terminal t2 of the switch SW.
[0033]
The switch SW is a two-contact switch in which the terminal t1 and the terminal t2 can be selectively switched with respect to the terminal t3 as shown in the figure.
The terminal switching of the switch SW is controlled by a latch, which is an output of the latch circuit 10 described later.
[0034]
The synchronization detector 7 receives the composite signal cs and the first threshold th1 or the second threshold th2 output from the terminal t3 of the switch SW, and detects a synchronization signal based on these. That is, a portion exceeding the threshold value th (first threshold value th1 or second threshold value th2) in the input composite signal cs is detected as a synchronization signal section, and is output as a synchronization signal output D.
The synchronization signal output D output in this manner is supplied to a PLL block (not shown) and used for generating various operation clocks. In particular, in the case of the present embodiment, the output pulse of the PLL block is used for generating a timing pulse tp for detecting the pedestal level in the sample and hold circuit 2 described above.
[0035]
Further, the synchronization signal output D is also supplied to an integrator 8 shown in the figure.
The integrator 8 performs an integration operation corresponding to a synchronization signal section indicated by the synchronization signal output D. Here, the operation of the up-reset counter will be described for convenience, but the integrator 8 is configured to increase the count value while the synchronization signal output D indicates the synchronization signal section. Then, the operation is performed so that the count value is reset at the timing at which the illustrated reset pulse RP generated corresponding to the 1H cycle of the composite signal cs is supplied.
In other words, the operation of the integrator 8 is to count up during the synchronization signal section and to reset the value every period corresponding to 1H.
[0036]
The output of the integrator 8 is supplied to the comparator 9 as an integrator output BB as shown in the figure. The comparator 9 also receives a preset judgment value β.
The comparator 9 outputs, for example, an L-level signal to the illustrated latch circuit 10 under the condition of integrator output BB <judgment value β, based on the result of comparing the integrator output BB with the judgment value β. Further, an H-level signal is output to the latch circuit 10 under the condition of integrator output BB> determination value β.
[0037]
The output of the comparator 9 and the previous reset pulse RP are input to the latch circuit 10. This latch circuit 10 latches the output of the comparator 9 at the timing when the reset pulse RP is supplied. That is, in this case, for example, when the comparator 9 outputs an L-level signal at the timing when the reset pulse RP is supplied, the L-level signal is changed according to the cycle (1H) of the reset pulse RP. Output during the specified period. Further, for example, in response to the comparator 9 outputting the H-level signal at the timing when the reset pulse RP is supplied, the H-level signal is changed according to the cycle (1H) of the reset pulse RP. Output for a period.
[0038]
The output of the latch circuit 10 is supplied to the above-described switch SW as a latch output latch, and is used for terminal switching control of the switch SW. That is, in this case, the switch SW selects the terminal t1 and outputs the first threshold th1 in response to the L level being supplied as the latch output latch (the integrator output BB <the determination value β). To be. Further, when the H level is supplied as the latch output latch (integrator output BB> judgment value β), the terminal t2 is selected to output the second threshold th2.
[0039]
The operation of the synchronization detection circuit 1 configured as described above will be described with reference to a timing chart shown in FIG.
FIG. 2A schematically shows a composite signal cs input to the synchronization detection circuit 1. As described above, in this composite signal cs, the illustrated L1 level is pedestal. And the L2 level is the sync chip level. The portion where the composite signal cs is at the L2 level (period A in the figure) is a synchronization signal section.
The timing pulse tp shown in FIG. 2B is, for example, a delay pulse based on the synchronization signal output D (FIG. 2G) as described above, so that the composite signal cs as shown in FIG. The pulse of the H level is obtained corresponding to the section where is at the pedestal level.
[0040]
The output sh of the sample and hold circuit shown in FIG. 2C indicates the level of the composite signal cs when the timing pulse tp is detected. That is, as described above, a level corresponding to the pedestal level can be obtained as the sample-and-hold circuit output sh as shown in the figure.
A level corresponding to the sync chip level (L2) is obtained as the minimum value circuit output ss shown in FIG. 2F, and the first threshold value th1 shown in FIG. The level is set to, for example, a level as shown in FIG. That is, the first threshold value th1 is set to an optimum level between the minimum value circuit output SS and the sample hold circuit output sh.
[0041]
Further, in this case, the second threshold value th2 shown in FIG. 2E is the same as the minimum circuit output ss (FIG. 2F) in FIG. 1 in the second threshold value determination circuit 6 shown in FIG. By calculating the offset value α, for example, a level as shown in the figure is set.
A synchronization signal output D shown in FIG. 2G indicates a signal output from the synchronization detector 7 shown in FIG.
[0042]
In this case, since the timing pulse tp shown in FIG. 2B is supplied at a normal timing corresponding to the section of the pedestal level of the composite signal cs as shown at time t1, the sample shown in FIG. In response to this, the hold circuit 2 normally detects the pedestal level and outputs an appropriate sample / hold circuit output sh (FIG. 2C).
Then, in the first threshold value determination circuit 5, the first threshold value th1 can be set based on the appropriate sample-hold circuit output sh and the minimum value circuit output ss output by the minimum value detection circuit 3. .
[0043]
Further, in this case, as shown in the figure, the synchronization signal output D (FIG. 2 (g)) is detected with a normal pulse width, and the integrator output BB output from the integrator 8 becomes as shown in FIG. ) Does not exceed the level of the determination value β.
That is, in this case, when the pulse width of the synchronizing signal output D (FIG. 2 (g)) is normal, the level of the determination value β is set so that the level of the integrator output BB does not exceed the determination value β. Is what it is.
Here, for example, in the case of the composite signal cs in the NTSC system, the synchronization signal section indicated by A in the figure is about 4.7 μs. Therefore, at this time, the section in which the synchronization signal output D shown in FIG. 2G is at the H level is about 4.7 μs when the synchronization signal section is normally detected.
In view of this, the level of the determination value β may be set to a value corresponding to the value calculated by the integrator 8 during the period of 4.7 μs, for example. If the determination value β is set to such a value, it is possible to detect that the pulse width of the synchronization signal is abnormal due to the value of the integrator output BB exceeding the determination value β. Become.
[0044]
In FIG. 2, as shown at time t1, depending on the condition of integrator output BB <judgment value β, comparator 9 outputs an L-level signal as described above.
Then, in response to this, the latch circuit 10 latches this L-level signal at the timing of the reset pulse RS shown in FIG. 2J, and supplies this to the switch SW as a latch output latch.
By supplying the L-level signal as the latch output latch, the switch SW is controlled to select the terminal t1. Then, the first threshold th1 is supplied to the synchronization detector 7 accordingly.
As a result, as shown in FIG. 2, when the timing pulse tp has no phase shift and the pedestal level is normally detected, the first properly set as described above is set. The synchronization signal is detected based on the threshold th1.
[0045]
By the way, the timing pulse tp used for detecting the pedestal level in the composite signal cs as described above includes, for example, a phase shift due to switching of a reception channel in a television receiver or head skew of a VTR. Can easily occur.
Then, depending on the occurrence of the phase shift in the timing pulse tp, as described above, the erroneous portion in the composite signal cs is detected as the pedestal level in the sample-and-hold circuit 2, thereby causing The first threshold th1 will be set to an incorrect value.
[0046]
FIG. 3 is a timing chart showing an operation performed in the synchronization detection circuit 1 in response to a shift in the phase of the timing pulse tp.
In FIG. 3, as an example in which the above-described phase shift has occurred, it is assumed that the timing pulse tp is obtained at a timing when the composite signal cs becomes a video section as shown at a time point t1.
Then, in response to this, in the sample hold circuit 2, such a level of the video section of the composite signal cs is erroneously recognized as a pedestal level. In this case, an erroneous level is calculated as the first threshold value th1 determined by the first threshold value determination circuit 5 according to the sample hold circuit output sh output from the sample hold circuit 2 as shown in the figure. It will be.
[0047]
Therefore, in this case, the synchronization detector 7 performs the synchronization signal detection based on the level of the first threshold th1 as described above, and as a result at the time t2, the synchronization detector 7 detects the erroneous position in the composite signal cs. The synchronization signal section will be detected.
According to the first threshold value th1, the period from the time t2 to the time t4, which is a period in which the level of the composite signal cs exceeds the level of the first threshold value th1, is erroneously detected as a synchronization signal section. Things.
[0048]
However, in the case of the present embodiment, an erroneous portion in the composite signal cs is detected as a synchronization signal section as described above, and in accordance with the fact that the synchronization signal section is detected longer than usual, The operation of switching the erroneously determined threshold value to another threshold value is performed.
[0049]
That is, in this case, first, the erroneous first threshold value th1 is determined as described above, and the synchronization signal section (H level section of the synchronization signal output D) becomes longer, and accordingly, the integration shown in FIG. The level of the device output BB exceeds the level of the determination value β.
That is, as described above, the determination value β in this case is set to a value corresponding to the value of the integrator 8 calculated during the H level period of the synchronization signal output D in the normal state. Therefore, when the H level period of the synchronizing signal output D becomes longer than usual, the integrator output BB exceeds the level of the determination value β.
When the integrator output BB exceeds the level of the determination value β, the comparator 9 outputs an H-level signal. In response, the latch circuit 10 outputs the H-level signal. Is latched at the timing of the reset pulse RS shown in FIG. 3 (i), and this is supplied to the switch SW as a latch output latch (FIG. 3 (j)) (time t3).
The switch t is supplied with the H-level signal as the latch output latch in this way, so that the terminal t2 is selected. In response to this, the second threshold value th2 determined by the second threshold value determination circuit 6 is output from the terminal t3 of the switch SW.
[0050]
As a result, at this time point t3, the synchronization detector 7 starts detecting the synchronization signal using the second threshold value th2 shown in FIG. In this case, as described above, depending on the first threshold value th1, the period from time t2 to time t4 is detected as a synchronization signal section, but here, the period from time t2 to time t3 is synchronized as illustrated. It can be detected as a signal section.
That is, in this case, since the value corresponding to the minimum value of the actual composite signal cs is set as the second threshold value th2, the second threshold value th2 is more accurate than the case based on the first threshold value th1 set to an incorrect value. The synchronization signal can be detected at the same time.
[0051]
As described above, in the synchronization detection circuit 1 according to the present embodiment, when the phase shift occurs in the timing pulse tp and the pedestal level is not normally detected, the first threshold value erroneously set as described above. The synchronization signal can be detected by the second threshold value th2, which is set to a value more appropriate than th1.
That is, even when a phase shift occurs in the timing pulse tp and the pedestal level is not normally detected, the synchronization signal can be properly detected.
[0052]
By selecting the second threshold value th2 in this manner, as shown in the figure, if the next synchronization signal section after the time point t5 to t6 is correctly detected, the first threshold value th1 is selected again accordingly. It becomes.
That is, as shown at time points t5 to t6, when the synchronization signal section is properly detected by the second threshold value th2, the comparator 8 first recognizes the condition of the integrator output BB <the determination value β. Then, in response to this, at the timing when the reset pulse RS is supplied at the time point t7, the latch circuit 10 outputs the L-level latch output latch as shown in FIG. 3 (j). Further, in response to the L-level latch output latch, the switch SW selects the terminal t1, and the first threshold th1 is supplied to the synchronization detector 7 again.
[0053]
By the way, as in the example shown in FIG. 3, when the phase of the timing pulse tp instantaneously returns to the normal state at this time point t7, the first threshold value th1 selected again as described above is thereafter used. , It is possible to perform appropriate synchronization signal detection.
However, at this time, when the timing pulse tp is generated based on, for example, the output of the PLL block 110 as described above, the phase does not actually return instantaneously as described above, and the phase variation does not occur. Often gradually converges.
[0054]
Here, it is assumed that the timing pulse tp is generated based on the output of the PLL block 110 as described above, which corresponds to a case where the timing pulse tp has not yet returned to the original phase at time t7 shown in FIG. Therefore, the following operation is performed in the synchronization detection circuit 1 of the present example.
First, at time t7, if the phase of the timing pulse tp still shifts, the level of the sample and hold circuit output sh shown in FIG. 3C is maintained at the level at time t1. As a result, the level of the first threshold value th1 selected again at the time point t7 as described above is maintained at the level of the time point t1.
In such a state, if a next synchronization signal section (not shown) is reached after the time point t7, the synchronization signal section is detected by the erroneous first threshold th1 as described above. When the output BB exceeds the level of the determination value β, the second threshold value th2 is selected. Then, when the synchronization signal is properly detected again by the second threshold value th2, the first threshold value th1 is selected again. That is, in this case, unless the timing pulse tp returns to the normal phase, the operation of selecting the second threshold value th2 → the first threshold value th1 → the second threshold value th2 is repeated.
[0055]
As described above, the switching operation from the first threshold value th1 to the second threshold value th2 is repeated, and the synchronization signal output D output from the synchronization detection circuit 1 at this time is shown in FIG. As described above, the pulse width of the H level (synchronous signal section) differs every other cycle.
When the pulse width of the synchronization signal output D becomes unstable, the operation of the PLL block 110 that operates based on the synchronization signal output D becomes unstable.
Therefore, as a result, the timing pulse tp generated based on the output of the PLL block 110 is also affected, and in the worst case, the timing pulse tp may not converge forever.
[0056]
Therefore, in order to avoid such a problem, there is provided a period sufficient for the PLL to converge after the second threshold value th2 is selected and before switching to the first threshold value th1. This is a second embodiment.
[0057]
FIG. 4 is a block diagram showing a configuration example of the synchronization detection circuit 20 as such a second embodiment.
In FIG. 4, the same reference numerals are given to the parts already described in FIG. 1, and the description will be omitted.
The synchronization detection circuit 20 according to the second embodiment is different from the configuration of the synchronization detection circuit 1 according to the first embodiment in that an OR gate circuit 21, a 3-bit counter 22, and a determination circuit (= 0) 23 are further illustrated. , And a NOT gate circuit 24 are added.
[0058]
First, the latch output latch from the latch circuit 10 is input to the OR gate circuit 21. The output of the NOT gate circuit 24 is also input to the OR gate circuit 21 as shown in FIG.
The OR gate circuit 21 outputs an H level when at least one of the latch output latch input as described above and the output of the NOT gate circuit 24 is at an H level. That is, in other words, the L level is output only when these input signals are both at the L level.
As shown, the output of the OR gate circuit 21 is branched and supplied to the 3-bit counter 22 as an ENABLE signal and to the switch SW as a switch control signal SWC.
[0059]
The switch SW selects the terminal t1 in response to the L level of the switch control signal SWC supplied from the OR gate circuit 21. Further, the terminal t2 is selected in accordance with the switch control signal SWC attaining the H level.
[0060]
The 3-bit counter 22 starts counting 3-bits based on the timing of the counter clock CLK in response to the input ENABLE signal going high. As the counter clock CLK, a clock corresponding to the horizontal synchronization signal frequency is generated.
Then, when the 3-bit counting operation based on the timing of the clock CLK is completed, the count value is reset to “0”.
The value of the 3-bit counter 22 is input to the determination circuit 23.
[0061]
The determination circuit 23 determines whether the value of the 3-bit counter 22 (hereinafter referred to as a count value) is “0”.
When the count value is “0”, for example, an L-level signal is output to the NOT gate circuit 24. If the count value is not “0”, the H level signal is output to the NOT gate circuit 24.
The NOT gate circuit 24 supplies the inverted output of the signal output from the determination circuit 23 to the OR gate circuit 21.
[0062]
The operation of the synchronization detection circuit 20 according to the second embodiment having such a configuration will be described with reference to a timing chart shown in FIG.
First, in this figure, it is assumed that the phase of the timing pulse tp has shifted at time point t1 in the figure.
Then, in response to this, an erroneous portion in the composite signal cs is detected as the pedestal level as described above, and accordingly, the first threshold th1 is also set to an erroneous value, The pulse width of the H level of the synchronization signal output D (FIG. 5C) becomes abnormal.
When the pulse width of the synchronization signal output D becomes abnormal as described above, the integrator output BB shown in FIG. 5D exceeds the level of the determination value β. The indicated latch output latch rises to the H level (time t2).
[0063]
As described above, when the latch output latch rises to the H level, at this time t2, the OR gate circuit 21 shown in FIG. 4 outputs the H level as the switch control signal SWC (FIG. 5 (i)). It becomes.
By outputting the H level as the switch control signal SWC in this manner, the terminal t2 is selected in the switch SW as described above, whereby the second threshold th2 is supplied to the synchronization detector 7. Will be entered. That is, the synchronization detector 7 detects a synchronization signal based on the threshold th2.
[0064]
In this case, the H-level output of the OR gate circuit 21 is also supplied to the 3-bit counter 22 shown in FIG. 4 as an H-level ENABLE signal. Then, in response to the supply of the H-level ENABLE signal, the 3-bit counter 22 starts counting 3 bits at a timing based on the counter clock CLK shown in FIG. 5 (g) (time t3).
[0065]
In response to the start of the operation of the 3-bit counter 22, the determination circuit 23 shown in FIG. 4 determines that the count value is not "0". In response to this, an L level signal is output from the determination circuit 23 to the NOT gate circuit 24 as described above.
Further, since the NOT gate circuit 24 inverts and outputs the signal supplied from the discrimination circuit 23, an H level signal is input to the OR gate circuit 21 at this time. It becomes.
[0066]
When the H-level signal is supplied to the OR gate circuit 21, the count value of the 3-bit counter 22 (FIG. 5 (h)) becomes "7", the 3-bit count ends, and the count value is reset to "0". It continues until the time point t4. That is, at this time point t4, the count value becomes “0”, and accordingly, a high-level signal is output from the determination circuit 23, and a low-level signal is supplied from the NOT gate circuit 24 to the OR gate circuit 21. Until it is completed.
That is, even when the latch output latch from the latch circuit 10 is reset to the L level by the reset pulse RP shown in FIG. 5E, an H level signal is output to the OR gate circuit 21. Will be supplied.
[0067]
When the H level signal is continuously supplied to the OR gate circuit 21 in this manner, the switch control signal SWC output from the OR gate circuit 21 is also maintained at the H level.
While the H level is maintained as the switch control signal SWC, the terminal t2 is selected in the switch SW, whereby the second threshold th2 is continuously selected.
That is, in this case, the second threshold value th2 is selected until time t4 when the count value is reset to “0” as described above.
[0068]
Thus, in the synchronization detection circuit 20, during a certain period according to the count value, the synchronization signal is detected by the second threshold value th2 which is more reliable than the first threshold value th1. become able to.
In this case, a sufficient period is provided until the PLL converges and the timing pulse tp returns to the normal phase from the detection of the synchronization signal using the second threshold value th2 to the switching to the first threshold value th1. Will be able to
[0069]
As a result, depending on the synchronization detection circuit 20 of the second embodiment, the responsiveness of the PLL when the phase between the horizontal synchronization signal and the timing pulse tp is shifted due to, for example, channel switching or VTR head skew is improved. Can be improved.
[0070]
Here, the case where the counter that determines the selection period of the second threshold value th2 as described above is a 3-bit counter is described as an example, but this should be changed as appropriate according to the characteristics of the PLL to be used. There is no particular limitation.
[0071]
As described above, in the second embodiment, when a phase shift occurs in the timing pulse tp, the synchronization signal is detected by the second threshold th2 for a certain period, and a sufficient period for the convergence of the PLL is achieved. Is provided.
However, according to the configuration of the second embodiment, the timing at which the PLL converges and the timing pulse tp returns to the normal phase does not always coincide with the timing of switching to the first threshold th1. No.
That is, in this case, although the timing pulse tp returns to the normal phase and an appropriate value is set as the first threshold th1, a period occurs in which the synchronization signal detection by the second threshold th2 is continued. there is a possibility.
In such a period, for example, when the input composite signal cs has a waveform as shown in FIGS. 10B and 10C due to a weak electric field or transmission system distortion, the synchronization signal is detected. Accuracy will be reduced.
[0072]
Therefore, in order to avoid such a situation, when the timing pulse tp returns to the normal phase, the switching to the first threshold th1 is immediately performed. This is a synchronization detection circuit 30 as an embodiment.
[0073]
FIG. 6 is a block diagram showing a configuration example of the synchronization detection circuit 30 according to the third embodiment. Also in this figure, the same reference numerals are given to the parts already described in FIG. 1 and the description is omitted.
The synchronization detection circuit 30 includes two synchronization detection circuits, that is, a first synchronization detector 30a and a second synchronization detector 30b, as shown in the figure, as circuits for detecting the synchronization signal of the input composite signal cs. It will be.
In this case, the first synchronization detector 30a is configured to perform the synchronization detection based on the first threshold th1 set by the first threshold determination circuit 5 as illustrated.
On the other hand, the second synchronization detector 30b is configured to perform synchronization detection based on the second threshold value th2 set by the second threshold value determination circuit 6.
[0074]
The first synchronization detector 30a is provided with an integrator 8, a comparator 9, and a latch circuit 10, which are connected in the same manner as in the case of FIG.
That is, in this case, the integrator 8 outputs the integrator output BB by performing the integration operation by inputting the detection output D1 of the first synchronization detector 30a, and the latch circuit 10 Outputs a latch output latch in accordance with the result of comparison between the integrator output BB and the judgment value β.
[0075]
Further, in this case, the switch SW whose switching operation is controlled by the latch output latch from the latch circuit 10 has a terminal t1 connected to the first synchronization detector 30a and a terminal 2 connected to the terminal 2 as shown in the figure. It is connected to the second synchronization detector 30b.
That is, when the terminal t1 is selected, the detection output D1 of the first synchronization detector 30a is output as the synchronization signal output D from the terminal t3. When the terminal t2 is selected, the detection output D2 of the second synchronization detector 30b is output as the synchronization signal output D.
[0076]
FIG. 7 is a timing chart for explaining the operation of the synchronization detection circuit 30 configured as described above.
Also in this case, if the phase of the timing pulse tp is shifted as shown at a time point t1 in the figure, for example, the pedestal level is erroneously recognized in the sample and hold circuit 2, so that the first threshold value th1 is also set to an erroneous value. Is done. In response to this, the synchronization signal section is erroneously detected in the first synchronization detector 30a, and as a result, the detection output D1 shown in FIG. It will stand up.
[0077]
As described above, when the detection output D1 rises at an incorrect timing, the H level section of the detection output D1 becomes longer, and accordingly, the value of the integrator output BB to which the detection output D1 is input becomes the determination value β. Will be exceeded. When the value of the integrator output BB exceeds the value of the determination value β, the latch output latch is supplied at the timing when the reset pulse RP (FIG. 7E) is supplied, as shown at time t3. (FIG. 7F) rises to the H level.
[0078]
When the latch output latch rises to the H level, the terminal t2 is selected in the switch SW, whereby the output D2 of the second synchronization detector 30b is output as the synchronization signal output D as described above. . That is, in this case, the synchronization signal detected based on the second threshold value th2 is output.
As a result, even in this case, when the phase shift occurs in the timing pulse tp as described above, the synchronization signal output D can be output based on the second threshold th2 that is more appropriate than the first threshold th1.
[0079]
Here, as described above, in the third embodiment, after providing two independent synchronization detection circuits of the first synchronization detector 30a and the second synchronization detector 30b, the first synchronization detector An integrator 8, a comparator 9, and a latch circuit 10 are provided for 30a.
That is, in this case, as can be seen with reference to FIG. 6, the integrator 8, the comparator 9, and the latch circuit 10 always monitor the pulse width of the detection output D1 of the first synchronization detector 30a. Is what it is.
[0080]
Accordingly, in this case, even after the time point t3 when the second threshold value th2 is selected as described above, the pulse width of the detection output D1 of the first synchronization detector 30a shown in FIG. Is monitored based on the integrator output BB and the determination value β shown in FIG.
[0081]
In this way, the pulse width of the detection output D1 of the first synchronization detector 30a can be monitored even after the second threshold value th2 is selected, so that the point in time when the pulse width of the detection output D1 returns to normal is detected. It becomes possible. That is, in this case, when the value of the integrator output BB falls below the value of the determination value β, it can be detected that the timing pulse tp has returned to the normal phase.
[0082]
As an operation at this time, first, after the time point t3, while the phase of the timing pulse tp (FIG. 7B) is shifted, the pulse width of the detection output D1 is wider than usual as shown in FIG. The width continues to be detected, and accordingly, the value of the integrator output BB also becomes larger than in the normal state, and continuously exceeds the determination value β at each synchronization signal detection timing.
As long as the value of the integrator circuit BB continues to exceed the determination value β, the H level is continuously output as the latch output latch as shown in FIG. 7F, whereby the switch SW selects the terminal t2. As a result, the detection output D2 of the second synchronization detector 30b continues to be output as the synchronization signal output D (FIG. 7 (g)).
In other words, in this case as well, while an erroneous value is set as the first threshold th1 as described above, the synchronization signal can be detected using the second threshold th2 that is more reliable than the first threshold th1. It is.
[0083]
When the timing pulse tp returns to a normal phase and the first threshold value th1 is set to a correct value, the first synchronization detector 30a correctly detects a synchronization signal based on the first threshold value th1 set as described above. Can be performed. When the normal pulse width is output as the detection output D1 of the first synchronization detector 30a, the value of the integrator output BB falls below the value of the determination value β, and the latch circuit 10 At the time t4, the latch output latch falls to the L level.
[0084]
In this manner, the switch SW selects the terminal t1 in response to the L level latch output latch becoming L level, whereby the detection output D1 of the first synchronization detector 30a becomes the synchronization signal output. D is output.
That is, as described above, the timing pulse tp returns to the normal phase, and the first synchronization detector 30a immediately synchronizes the detection output D1 of the first synchronization detector 30a with the normal synchronization detection. This can be output as a signal output D.
[0085]
In this way, it is possible to immediately switch to the detection output D1 in response to the return of the timing pulse tp to the normal phase, so that the synchronization detection circuit 30 detects the signal at the optimum threshold th. It is possible to output the synchronization signal output D.
In other words, since the synchronization signal can be detected with the threshold value th always optimized as described above, the detection accuracy of the synchronization signal can be further improved.
[0086]
Here, in the sync separation circuit of each embodiment described above, the input composite signal cs usually includes a vertical sync signal in addition to a horizontal sync signal.
As such a vertical synchronizing signal, for example, as shown in FIG. 9, the minimum value level in the signal is used as the synchronizing signal section similarly to the horizontal synchronizing signal. When such a vertical synchronizing signal section arrives in the circuit, the pulse width of the synchronizing signal is erroneously detected as abnormal.
[0087]
Therefore, a configuration as described below can be added to the synchronization separation circuit of each embodiment as a modification for preventing such erroneous detection.
FIG. 8 is a block diagram showing a configuration of the synchronization detection circuit 40 as such a modification. Here, the configuration as a modified example is illustrated only for the case where the configuration is applied to the synchronization detection circuit 1 shown in FIG. 1, and when the configuration is applied to the synchronization separation circuits of the second and third embodiments. Since these are almost the same, description thereof will be omitted.
As a configuration of this modification, first, an OR gate circuit 41 is newly added as illustrated. Then, a reset pulse RP and a signal VMASK shown are input to the OR gate circuit 41.
As the signal VMASK, a signal in which the level of the composite signal cs becomes H level corresponding to the period of the vertical synchronization signal section is supplied. That is, the signal VMASK may be a signal based on a vertical synchronization signal supplied from, for example, a vertical synchronization signal separation circuit (not shown).
The OR gate circuit 41 outputs the reset pulse RP to the integrator 8 and the latch circuit 10 while the L level is being input as the signal VMASK. While the H level is input as the signal VMASK, the reset pulse RP is not supplied to the integrator 8 and the latch circuit 10.
[0088]
The operation according to the configuration of this modified example will be described with reference to the timing chart of FIG. 9. As described above, the signal VMASK (FIG. 9 (f)) corresponds to the cycle in which the composite signal cs becomes the vertical synchronization signal section. Therefore, for example, as shown in the figure, the section from time t1 to t2 is set to be the H level section.
While the signal VMASK is at the H level, the OR gate circuit 41 stops supplying the reset pulse RP to the integrator 8 and the latch circuit 10 as described above. During this period, the integrator circuit BB is at the "0" level as shown in FIGS. 9D and 9G, and the L level is also output as the latch output latch.
[0089]
That is, in this case, since the signal VMASK as described above is supplied, during the period when the vertical synchronization signal section shown in FIG. 9A is input, the synchronization signal by the integrator 8, the comparator 9, and the latch circuit 10 is provided. Is not monitored.
Thus, when the composite signal cs reaches the vertical synchronizing signal section, a situation in which an abnormal state is erroneously detected due to its pulse width is effectively prevented.
[0090]
【The invention's effect】
As described above, according to the present invention, in the synchronization detection circuit for detecting the horizontal synchronization signal included in the input video signal, first, the minimum value level of the input video signal for detecting the level of the horizontal synchronization signal is detected. In addition, in order to detect a pedestal level in an input video signal, the level of the input video signal is detected at a predetermined timing based on a detection cycle of a horizontal synchronization signal.
Then, based on the level of the video signal detected at a predetermined timing based on the detection cycle of the horizontal synchronization signal and the minimum value level, a first threshold value for detecting the horizontal synchronization signal is determined, The horizontal synchronization signal is detected based on the result of comparing the level of the input video signal with the first threshold.
Then, the section length of the horizontal synchronizing signal detected in this way is detected, and it is determined whether or not this section length is a section length that is normal.
[0091]
This makes it possible to determine whether or not the horizontal synchronization signal detected as described above is normally detected.
[0092]
Then, in response to the determination that the section length of the horizontal synchronization signal is not normal, detection of the horizontal synchronization signal is performed using the second threshold value determined based on the minimum value level (sync tip level). This makes it possible to prevent the horizontal synchronization signal from being erroneously detected based on the first threshold value determined to be an erroneous value due to, for example, a phase shift of the timing pulse.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a synchronization detection circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining an operation in the synchronization detection circuit according to the first embodiment.
FIG. 3 is a timing chart for explaining the operation of the synchronization detection circuit according to the first embodiment.
FIG. 4 is a block diagram illustrating a configuration example of a synchronization detection circuit according to a second embodiment;
FIG. 5 is a timing chart for explaining an operation in the synchronization detection circuit according to the second embodiment.
FIG. 6 is a block diagram illustrating a configuration example of a synchronization detection circuit according to a third embodiment;
FIG. 7 is a timing chart for explaining an operation in the synchronization detection circuit according to the third embodiment.
FIG. 8 is a block diagram showing a configuration example of a synchronization detection circuit as a modification.
FIG. 9 is a timing chart for explaining an operation in a synchronization detection circuit as a modification.
FIG. 10 is a diagram schematically illustrating an example of a waveform of a video signal.
FIG. 11 is a block diagram showing a configuration of a conventional synchronization detection circuit including a PLL block.
FIG. 12 is a timing chart for explaining an operation obtained in a conventional synchronization detection circuit.
[Explanation of symbols]
1, 20, 30, 40 synchronization detection circuit, 2 sample hold circuit, 3 minimum value detection circuit, 4 synchronization signal level estimation circuit, 5 first threshold value determination circuit, 6 second threshold value determination circuit, 7 synchronization detector, 8 integration , 9 comparator, 10 latch circuit, 21 OR gate circuit, 223 bit counter, 23 discriminating circuit (= 0), 24 NOT gate circuit, 30a first synchronous detector, 30b second synchronous detector, 41OR gate circuit, SW Switch, t1-t3 terminal

Claims (7)

In order to detect the level of the horizontal synchronization signal included in the input video signal, a minimum value level detection unit that detects the minimum value level of the input video signal,
Pedestal level detection means for detecting the level of the input video signal at a predetermined timing based on a detection cycle of the horizontal synchronization signal by the synchronization detection circuit to detect a pedestal level in the input video signal;
First threshold value determination means for determining a first threshold value for detecting the horizontal synchronization signal based on the levels detected by the minimum value level detection means and the pedestal level detection means;
At least the first threshold value determined by the first threshold value determination means is input as a threshold value. The input threshold value is determined based on a result of comparing the input threshold value with the level of the input video signal. First synchronizing signal detecting means for detecting a horizontal synchronizing signal in the video signal,
Section length detection means for detecting a section length of the horizontal synchronization signal detected by the first synchronization signal detection means;
Determining means for determining whether or not the section length detected by the section length detecting means is a normal section length;
A synchronization detection circuit comprising: Second threshold value determining means for determining a second threshold value different from the first threshold value determined by the first threshold value determining means based on the minimum value level detected by the minimum value level detecting means When,
In response to the determination result indicating that the section length of the horizontal synchronization signal is not normal being output by the determination means, the threshold value to be input to the first synchronization signal detection means is changed to the second threshold value. Further comprising threshold switching means for switching to the second threshold determined by the threshold determining means.
The synchronization detection circuit according to claim 1, wherein: The threshold switching means,
After a lapse of a predetermined period from the timing when the determination result indicating that the section length of the horizontal synchronization signal is not normal is output by the determination means, the threshold value to be input to the first synchronization signal detection means is again set to the first threshold value. Operate to switch to a threshold of 1,
3. The synchronization detection circuit according to claim 2, wherein: Second threshold value determining means for determining a second threshold value different from the first threshold value determined by the first threshold value determining means based on the minimum value level detected by the minimum value level detecting means When,
Second synchronization signal detection means for detecting a horizontal synchronization signal based on a result of comparing the level of the video signal with the second threshold value determined by the second threshold value determination means;
When the determination means outputs a determination result indicating that the section length of the horizontal synchronization signal is not normal, the detection output of the second synchronization signal detection means is output as the detection output of the synchronization detection circuit. The switching operation is performed as described above, and when the determination result indicating that the section length of the horizontal synchronization signal is normal is output, the detection output of the first synchronization signal detection means is output as the detection output of the synchronization detection circuit. Output switching means for performing a switching operation so as to perform
The synchronization detection circuit according to claim 1, further comprising: Further, in response to a vertical synchronization signal section in the video signal, a stop control unit that controls to stop the operation of the determination unit,
3. The synchronization detection circuit according to claim 2, wherein: In order to detect the level of the horizontal synchronization signal included in the input video signal, a minimum value level detection procedure for detecting the minimum value level of the input video signal,
To detect a pedestal level in the input video signal, at a predetermined timing based on the detection cycle of the horizontal synchronization signal, a pedestal level detection procedure for detecting the level of the input video signal,
A first threshold value determining procedure for determining a first threshold value for detecting the horizontal synchronization signal based on the levels detected by the minimum value level detecting procedure and the pedestal level detecting procedure;
Detecting a horizontal synchronization signal in the input video signal based on a result of comparing the level of the input video signal with at least the first threshold determined in the first threshold determination procedure; 1 synchronization signal detection procedure;
A section length detection procedure for detecting a section length of the horizontal synchronization signal detected by the first synchronization signal detection procedure;
A determination procedure for determining whether or not the section length detected by the section length detection procedure is a section length that is determined to be normal;
A synchronization detection method. Further, a second threshold value determining procedure for determining a second threshold value different from the first threshold value determined in the first threshold value determining procedure based on the minimum value level detected in the minimum value level detecting procedure. When,
In response to the result of the determination in the determination procedure, in which the section length of the horizontal synchronization signal is determined to be not normal, the threshold value to be compared with the level of the video signal in the first synchronization signal detection procedure is set to the A threshold switching procedure for switching to the second threshold determined by the second threshold determination procedure;
7. The synchronization detection method according to claim 6, wherein:

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