JPS5936468B2 - synchronous circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference signal generation circuit for generating and deriving reference signals necessary for performing various signal processing and circuit control in synchronization with television signals, for example in a television receiver. Concerning a preferred synchronous circuit.

For example, when performing various signal processing and circuit control in synchronization with television signals in a television receiver,
A reference signal generation circuit is required to generate and derive a reference signal synchronized with a desired position of a television signal.

In this case, a synchronization circuit having a counter circuit is used to synchronize the counting operation of the counter circuit with a horizontal synchronization signal or a vertical synchronization signal separated from the video signal, and the desired position of the television signal is determined based on the output of this counter circuit. The aim is to obtain a reference signal synchronized with the

FIG. 1 shows a reference signal generation circuit for generating a reference signal using, for example, a horizontal synchronization signal SH.

In the figure, 11 is the input end of the video signal, and this input end 1
A horizontal synchronization signal SH is separated from the video signal supplied to the horizontal synchronization signal SH by a horizontal synchronization separation circuit 12. This separated horizontal synchronization signal SH is transmitted to the automatic frequency control (AFC) circuit 13.
The horizontal AFC circuit 13 derives a pulse synchronized with the horizontal synchronizing signal SH. Figure 2a
What is shown in the figure is the horizontal synchronization signal SH separated by the horizontal synchronization separation circuit 12, and what is shown in the figure b is the horizontal synchronization signal SH separated by the horizontal synchronization separation circuit 12.
This is the output pulse P1 of the C circuit 13. This pulse P1 is supplied to a reset control circuit 14, which derives a pulse P2 synchronized with the rising edge of the pulse P1 as shown in FIG. 2c. This pulse P2 is supplied to the counter circuit 15 as a reset pulse. This counter circuit 15 uses a clock signal CP
The count output is stored in the ROM.
is supplied to circuit 16. In addition, the horizontal synchronization separation circuit 12,
The horizontal AFC circuit 13, the reset control circuit 14, and the counter circuit 15 constitute a synchronous circuit. The ROM circuit 16 derives a reference signal P3 synchronized with a desired position of the television signal based on the output of the counter circuit 15. This reference signal P3 is, for example, a pulse. Further, from this ROM circuit 16, the resetting control circuit 14 is
Then, a prohibition response P4 as shown in FIG. 2d is supplied.

This inhibition pulse P4 performs the following function. That is, since the counter circuit 15 only needs to be reset once, if the counter circuit 15 is reset by the reset pulse P2 at a certain time, the reset pulse P2 will be reset at a certain time.
2 is no longer supplied to the counter circuit 15 due to the action of the inhibit pulse P4. To put this specifically, for example, when the power is turned on, when changing channels, or when synchronization is disturbed due to transmission distortion of television signals, the counting operation of the counter circuit 15 is not synchronized with the horizontal synchronizing signal SH and is performed arbitrarily. It will work. Therefore, in this state, the prohibition pulse P4 is out of phase with the set pulse P2, and the reset pulse P2 does not fall within the generation period of the prohibition pulse P4. Therefore, when the power is turned on, the counter circuit 15 is generated approximately first and is reset by the set pulse P2. As a result, the counting operation of the counter circuit 15 is synchronized with the television signal, and since the predetermined counting operation is repeated cyclically, there is no need to supply the second and subsequent reset pulses P2 to the counter circuit 15. do not have. Therefore, when the counter circuit 15 is reset by approximately the first reset pulse P2,
The inhibit pulse P4 derived from the ROM circuit 16 is approximately 2
The generation timings of the reset pulses P2 and subsequent ones are controlled so that they are in phase. This results in approximately 2
The reset pulse P2 after the number is no longer supplied to the counter circuit 15. However, in the above-mentioned synchronous circuit, even if the horizontal AFC circuit 13 synchronizes its output pulse P1 with the horizontal synchronizing signal SH, the horizontal AF
Jitter tends to occur in the output pulse P1 of the C circuit 13, and this jitter becomes particularly large when the video signal includes a ghost.

In such a case, the reset pulse P2 will often occur outside the inhibit pulse P4, and each time the reset pulse P2
5 is now set, making it impossible to obtain the reference signal P3 synchronized with the television signal. in this case,
If the pulse width of the inhibit pulse P4 is increased, the counter circuit 15 will not be set frequently, so that the reference signal can be synchronized with the television signal. However, in this case, depending on the resetting of the counter circuit 15 or the generation position of the set pulse P2, there is a possibility that the obtained reference signal P3 is synchronized with the desired position of the television signal with a phase shift. . In addition, in this case, even if the phase of the television signal changes for some reason to a state that is inconvenient for the system after the counter circuit 15 is reset, the counter circuit 15 is reset so that the reset pulse P2 does not deviate outside the period of the prohibition pulse P4. It is likely that the circuit 15 will not be reset, resulting in a problem that the reference signal P3 will not be synchronously adjusted. Therefore, the reference signal generated in this manner cannot be used for signal processing or circuit control that requires strict synchronization with television signals. The present invention has been made in order to cope with the above-mentioned circumstances, and an object of the present invention is to provide a synchronization circuit that can accurately synchronize the counting operation of a counter circuit with a repetitive signal. Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, in which a counter correction circuit 1 is used instead of the reset control circuit 14 shown in FIG.
? The reference signal generating circuit is the same as the reference signal generating circuit shown in FIG. 1 except that two inhibition pulses having different time widths are used, so the same parts are given the same reference numerals and detailed explanation will be omitted.

That is, the horizontal synchronization signal SH as shown in FIG. 4a is derived from the horizontal synchronization separation circuit 12, and
From this, a pulse P1 as shown in FIG. 4b is derived. The output pulse P of the horizontal AFC circuit 13 is supplied to a counter correction circuit 17 and sampled using, for example, a clock signal CP used for counting by the counter circuit 15. As a result, a set pulse P2 as shown in FIG. 4c is generated near the rising edge of the pulse P. When the power is turned on, when a channel is changed, or when synchronization is disturbed, substantially the first pulse P2 of the set pulses P2 generated as described above is supplied to the counter circuit 15, and this pulse is reset. Thereby, the counting operation of the counter circuit 15 becomes approximately synchronized with the horizontal synchronizing signal SH. By the way, the counter correction circuit 17 includes a ROM.
The circuit 16 generates inhibit pulses P4 and P5 as shown in FIG. 4d.
is supplied. For example, a prohibition pulse P4 is supplied when the power is turned on, and in this case, the prohibition pulse P4 is usually out of phase with the approximately first reset pulse P2, but when the counter circuit 15 is reset, The phases will match. As a result, approximately the second and subsequent reset pulses P2 are no longer supplied to the counter circuit 15. However, the pulse width of the prohibition pulse P4 in this case is the second
The pulse width is set to be larger than the pulse width of the inhibit pulse P4 shown in FIG. It is set. Therefore, the reset pulse P2 almost never deviates outside the generation period of the inhibit pulse P4, and the counting operation of the counter circuit 15 is approximately synchronized with the horizontal synchronizing signal SH. However, in this case, depending on the position where the first reset pulse P2 is generated, the counting operation of the counter circuit 15 may not be synchronized with the normal horizontal synchronizing signal position.
In other words, when the counter circuit 15 is reset by the longest first reset pulse P2, the counting operation of the counter circuit 15 is simply synchronized with the approximate position of the horizontal synchronizing signal SH. Correction for synchronizing the counting operation of the counter circuit 15 with the normal horizontal synchronizing signal position is performed by the counter correction circuit 17.

The counter correction circuit 17 performs the following operations in addition to generating the reset pulse P2. In other words, this counter correction circuit 17 detects at what position the reset pulse P2 has occurred during the generation period of the prohibition pulse P4, and uses this detection result to calculate the generation of the prohibition pulse P4 one period (one horizontal scanning period) before. Add to the detection results for the period. In this way, the distribution state of the reset pulse P2 can be known by cyclically detecting the generation position of the reset pulse P2 for each horizontal scanning period and accumulating the detection results. When a predetermined accumulation result is obtained in this way, the accumulation operation is stopped and the position where the reset pulse P2 is generated the most is detected. This detected position can be regarded as the regular horizontal synchronization signal SH position. Once the position where the set pulse P2 is generated the most is detected, the counter correction circuit 17 forcibly adjusts the counter circuit 15 based on the detected position during the generation period of the inhibition pulse P4 in the next horizontal scanning period. Set. This means that the counting operation of the counter circuit 15 is synchronized with the normal horizontal synchronizing signal position. Therefore, the reference signal P3 generated from the ROM circuit 16 is also synchronized with the desired position of the television signal. By the way, in the system in which this synchronous circuit is used as described above, the prohibition pulse P4 is acceptable for obtaining a predetermined operation, or the set pulse P2 is
Since the time width is set to be greater than the deviation range of the reset pulse P2, even after the counter circuit 15 is reset based on the cumulative result of the generation position of the reset pulse P2, the counter circuit of the reset pulse P2 can be reset using the inhibit pulse P4. If supply to 15 is prohibited, the following problems will occur. That is,
Even if the phase of the television signal changes for some reason and is fixed at the changed position, and the reset pulse P2 deviates beyond the allowable deviation range to obtain the specified operation of the system, the time width of the inhibit pulse P4 Since the time is long, a situation where the counter circuit 15 is not reset is likely to occur. Therefore, the counter correction circuit 17 does not correct the counting operation of the counter circuit 15, and the reference signal P3
Problems arise when the signal remains synchronized with the television signal at a position that is out of phase with the desired position. Therefore, when the counter correction circuit 17 finishes correcting the counting operation of the counter circuit 15, the ROM circuit 16 outputs a prohibition pulse P5 instead of the prohibition pulse P4.
is supplied. The time width of the inhibit pulse P5 is set to be approximately equal to the deviation range of the set pulse P2, which is allowable for obtaining a predetermined operation in the system, for example. Therefore, even after the counter circuit 15 has been corrected, if the reset pulse P2 deviates even slightly from the range in which the system can obtain a predetermined operation,
The counter circuit 15 is corrected by the counter correction circuit 17. In this case, the inhibit pulse is now P4 rather than P5.
can be switched to As described above, the set pulse P
The accumulation operation of 2 and the correction of the counter circuit 15 are repeated. It goes without saying that while the counter correction circuit 17 is performing the accumulation operation, the reference signal P3 may be generated or may not be generated.

Further, the prohibition pulses P4, P, are generated and derived in the ROM circuit 16 as pulses for n clock signals and m (n>m) clock signals for each horizontal period, respectively, and are accumulated by this ROM circuit 16. The prohibition pulses P, →P4, and P4→P are switched at timings substantially equal to the start and end of , respectively. FIG. 5 shows an example of a specific circuit configuration of the counter correction circuit 17.

1? A is a sampling circuit which derives the set pulse P2 by sampling the output pulse P of the horizontal AFC circuit 13 using the clock signal CP.

Then, when switching the power supply, switching channels, or when synchronization is disturbed, the sampling circuit 1? When the set pulse P2 is sampled approximately first by a, the set pulse P2 is sent to the counter circuit 15 via the set pulse switching circuit 17b.
is supplied and reset. This roughly synchronizes the counting operation of the counter circuit 15 with respect to the horizontal synchronizing signal. This also sets pulse switching circuit 17
A prohibition pulse P4 is also supplied to b, which prohibits approximately the second and subsequent reset pulses P2 from being supplied to the counter circuit 15. The set pulse P2 sampled by the sampling circuit 17a is also applied to the buffer memory 1? at the timing of the repetition period of the clock signal Cp during the generation period of the inhibit pulse P4. It is stored in c.

That is, the time width of the inhibit pulse P4 is equal to the clock signal CP.
Buffer memory 17c4:,
It has n storage units. Therefore, sampling circuit 1
? In the sampling operation of a, the digital signals of "1" (reset pulse) and "0" obtained during the generation period of the prohibition pulse P4 are sequentially written into the corresponding storage section of the buffer memory 17c.In this way, the generation of the prohibition pulse P4 During the period, when writing of the reset pulse P2 information to the buffer memory January Ic is completed, the following operation is performed until the next horizontal synchronizing signal is separated.

That is, the data stored in the buffer memory 17c is added to the data stored in the memory circuit Ile by the addition circuit 17d. That is, this memory circuit 17e has n storage sections corresponding to the n storage sections of the buffer memory 17c(1). Each storage section of this memory circuit 17e is, for example, l.
It is said that it is possible to create bit digital data. In the above configuration, data in each storage section of the buffer memory 17c is sequentially read out to the addition circuit 17d. At this time, the adder 17d is further provided with a memory circuit 17e in synchronization with the data reading timing from the buffer memory 17c.
The 1-bit digital data in each storage section is also sequentially read out. During this operation, the data in the storage section of the buffer memory 17c is added to the data in the corresponding storage section of the memory circuit 17e by the addition circuit 17d. The l-bit digital data after the addition operation is stored in memory circuit 1? It is written again to the same storage unit as when it was read during e. When the above operation is completed for n corresponding storage units, the addition operation in a certain horizontal scanning period is completed. By performing the above operation every horizontal scanning period, the digital data value of the memory section corresponding to the position where the set pulse P2 is generated most frequently among the n memory sections of the memory circuit 17e increases. 1? f is an accumulation judgment circuit; for example, if the most significant bit of one of the n memory sections of the memory circuit 17e becomes "1", after the addition operation is completed up to the n memory sections, the accumulation judgment circuit is executed. A calculation stop signal P6 is derived.

This accumulation stop signal P6 stops the timing pulses generated from the ROM circuit 16 to drive and control, for example, the buffer memory 17c, addition circuit 17d, and memory circuit 17e, thereby stopping the accumulation operation. When the accumulation of the reset pulse P2 is completed, during the period of the inhibition pulse P4 that occurs immediately thereafter, the accumulation determination circuit 17f stores the most significant bits of the n storage sections of the memory circuit 17e (7) by repeating the clock signal. It is read out at the same timing as the cycle and supplied to the reset pulse switching circuit 17b.

This reset pulse switching circuit 17b is connected to the memory circuit 17e.
The read data of the most significant bit from the counter circuit 1
Supply to 5. As a result, the counter circuit 15 becomes "1"
It is reset at the timing when the most significant bit in which is stored is read out. Further, at a timing substantially equal to this timing, the inhibit pulse supplied from the ROM circuit 16 is switched from P4 to P5. The reset pulse switching circuit 17b also switches between the prohibition pulse P5 and the set pulse P5.
2, an accumulation operation stop release signal P7 is supplied to the ROM circuit 16.

As a result, the ROM circuit 16 supplies timing pulses for driving and controlling the buffer memory 17c, the adder circuit 17d1 and the memory circuit 17e, so that the above-mentioned accumulation operation of the set pulse P2 is performed. Further, in this case, the prohibition pulse P5 is switched to P4. This embodiment described in detail above has the following effects.

First, the configuration is such that the distribution state of the generation positions of the reset pulses P2 is detected and the counter circuit 15 is reset at the position where the most reset pulses P2 are generated.
There is a very high probability that the counting operation of the counter circuit 15 will be synchronized with the normal horizontal synchronizing signal position. Therefore, it is possible to obtain the reference signal P3 that is precisely synchronized with the desired position of the television signal, and it is also possible to obtain a reference pulse for signal processing or circuit control that requires strict synchronization with the television signal. It is convenient for generation and derivation. In addition, by using the reset pulse P2 obtained from the output pulse P of the horizontal AFC circuit 13 to roughly synchronize the counting operation of the counter circuit 15 with the horizontal synchronization signal SH, the inhibition pulse P4 can be synchronized with the set pulse P2. Phase matching is performed, and the time width of the inhibition pulse P4 is set larger than necessary.

Therefore, even if the reset pulse P2 jitters during the accumulation operation of the reset pulse P2, it will not deviate from the prohibited pulse P4 period, so that the accumulation operation of the reset pulse P2 can be performed accurately. The reliability of the counter correction information obtained by the accumulation operation is high.
Furthermore, when the counter correction circuit 17 is not performing an accumulation operation, P5 is supplied as an inhibit pulse, so that
When the reset pulse P2 deviates from a range that is allowable for obtaining a predetermined operation in the system, the counter circuit 15 can be reliably corrected, and the counter circuit 1
5 can improve the reliability of the operation. In the previous embodiment, the prohibition pulse P4 is used to detect the position where the set pulse P2 is generated the most, and the counter circuit 1
After correcting the count operation of 5, the prohibition pulse is switched from P4 to P5, and the reset pulse P2 is changed to the prohibition pulse P.
5, the inhibit pulse is switched from P5 to P4, the reset pulse P2 is accumulated, and the counter circuit 1
Although a case has been described in which the operation of correcting the count operation of 5 is repeated, the following implementation is also possible.

That is, the prohibition pulse P4 is used to detect the phase change of the reset pulse P2, and the prohibition pulse P is used to detect the phase change of the output of the accumulation determination circuit 17f.
Therefore, when the power is turned on, approximately the first reset pulse P2 is supplied to the counter circuit 15 to reset it. Then, the prohibition pulse P4 is synchronized with the reset pulse P2 after the reset, and the reset pulse P2 is read into the buffer memory 17c during the generation period of the prohibition pulse P4.
Accumulated data is written into the memory circuit 17e. Then, when the accumulation operation is completed and the most significant bit of each storage section of the memory circuit 17e is read out, and the correction of the counting operation of the counter circuit 15 is completed, the ROM circuit 16 is transferred to the memory circuit 17.
Reset e to the initial state. At this time, the phase of the prohibition pulse P5 is controlled so as to be synchronized with the readout timing of the most significant bit in which data "1" is stored.As described above, the memory circuit 17e is set to the initial state. Then, the ROM circuit 16 drives the buffer memory 17c, addition circuit 17d, and memory circuit 17e to perform the accumulation operation again.The accumulation operation is thus completed and reading of the most significant bit begins, but if there is no phase change, The reading timing of the most significant bit "1" corresponds to the generation period of the inhibition pulse P5, and the counter circuit 15 is not reset. After accumulating the reset pulses P2 in this manner and reading out the most significant bit, the memory circuit 17e is reset, and the accumulation and reading of the most significant bit are repeated. In this case, if the phase of the set pulse P2 changes for some reason, the readout timing of the most significant bit to which data "1" has been written will deviate from the generation period of the prohibition pulse P5, so the counting operation of the counter circuit 15 will be corrected. Ru. With such a configuration, the counter circuit can be more accurately synchronized with the horizontal synchronization signal than in the previous embodiment.

In other words, since the phase change of the horizontal synchronizing signal SH is determined from the cumulatively processed signal, the correction of the counter circuit 15 is less susceptible to the effects of jitter, etc. of the output pulse P1 of the horizontal AFC circuit 13. This is because faithful synchronization can only be achieved with static phase changes in which the phase of the signal changes and the phase is fixed at the position of the change. Also, reset pulse P
There is also the advantage that 2 can be made narrower. Note that the present invention is not limited to the above embodiments.

For example, the counter circuit 15 may always be reset only by the result of the cumulative operation, without directly supplying the reset pulse P2 to the counter circuit 15. In this case, the second reference pulse referred to in the present invention does not have the function of prohibiting the supply of the second reference pulse P2 and the cumulative result of the reset pulse P2 to the counter circuit 15; Of course, the counter circuit 15 is reset every time the cumulative result of the set pulse P2 deviates from the generation period of the first and second reference pulses. Furthermore, the synchronization circuit of the present invention may be applied to a reference signal generation circuit that obtains a reference signal using a vertical synchronization signal, or to a reference signal generation circuit that synchronizes a signal different from a television signal. You may do so. Furthermore, the application is not limited to only reference signal generation circuits.
As described above, according to the present invention, it is possible to provide a synchronization circuit that can accurately synchronize the counting operation of a counter circuit with a repetition signal.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing a conventional synchronous circuit, FIGS. 2 a to d are signal waveform diagrams of various parts to explain the operation of the circuit in FIG. 1, and FIG. 3 is a block diagram of a synchronous circuit according to the present invention. 4a to 4e are signal waveform diagrams of various parts to explain the operation of the circuit of FIG. 3, and FIG.
FIG. 2 is a block configuration diagram showing an example of a specific circuit configuration of a main part of the circuit shown in the figure. 15...Counter circuit, 16...RO
M circuit, 17... Counter correction circuit, 17a.
... Sampling circuit, 17b ... Reset pulse switching circuit, 17c ... Buffer memory,
17d...addition circuit, 17e...memory circuit, 17f...accumulation determination circuit.

Claims (1)

[Claims] 1. A synchronizing pulse generating means that outputs a pulse that follows the separated synchronizing signal, and detecting the average phase of the synchronizing pulse by cyclically extracting the output pulses of the synchronizing pulse generating means and accumulating them. sample phase information generating means for generating sample phase information in response to this; a counter circuit that is reset by the sample phase information generating means and counts a predetermined clock signal;
Depending on the output state of the counter circuit, a first reference pulse having a wider pulse width than the pulse width of the sample phase information generating means or a second reference pulse having a narrower pulse width than the first reference pulse is generated. At the same time, the first
and determining whether or not the output pulse of the sample phase information generating means exists during the second reference pulse period, and only when the output pulse exists during the first or second reference pulse period, the counter Counter correction means for resetting a circuit, and switching for selectively switching the first or second reference pulse supplied to the counter correction means according to the output state of the counter circuit reset by the counter correction means. A synchronous circuit comprising means.