JPS6029258B2 - Unlock detection circuit for PLL synthesizer - Google Patents
Unlock detection circuit for PLL synthesizerInfo
- Publication number
- JPS6029258B2 JPS6029258B2 JP53047450A JP4745078A JPS6029258B2 JP S6029258 B2 JPS6029258 B2 JP S6029258B2 JP 53047450 A JP53047450 A JP 53047450A JP 4745078 A JP4745078 A JP 4745078A JP S6029258 B2 JPS6029258 B2 JP S6029258B2
- Authority
- JP
- Japan
- Prior art keywords
- detection circuit
- output
- outputs
- signal
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
- H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
- H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
- H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
【発明の詳細な説明】
本発明はPLLシンセサィザにおいてPLLが正常なロ
ック状態であるか否かを判定し、正常でない場合PLL
の可変周波発振器(VCO)出力信号を遮断するための
VCO出力遮断制御信号を出力する所謂アンロツク検出
回路に関する。Detailed Description of the Invention The present invention determines whether or not the PLL is in a normal lock state in a PLL synthesizer, and if the PLL is not in a normal lock state, the PLL
The present invention relates to a so-called unlock detection circuit that outputs a VCO output cutoff control signal for cutting off a variable frequency oscillator (VCO) output signal.
現在一般的に用いられているアンロック検出回路を含む
PLLシンセサィザの構成を第1図〜第3図を用いて説
明する。The configuration of a PLL synthesizer including an unlock detection circuit that is commonly used at present will be explained with reference to FIGS. 1 to 3.
ここで第1図はPLLの構成例図、第2図はPLLシン
セサィザ中の位相比較器の動作説明図、第3図は同じく
アンロック検出回路の動作説明図である。第1図におい
て、1は基準周波数発振回路、2は該基準周波数発振回
路1の出力信号を分周する固定分周器、3は該固定分周
器2の出力(第2図a)を参照信号として入力され、可
変分周器6の出力信号(第2図b)との位相比較を行な
い、第2図c,dに示す如き位相差信号PDまたはLD
を出力する位相比較器、4は譲位相比較器3の出力信号
PDを発振周波数制御用直流信号に変換するローパスフ
ィルタ(LPE)、5は該LPF4の出力信号によって
発振周波数が制御される可変周波数発振器(VCO)で
あり、前記可変分周器6はVC05の出力信号をコード
コンバータ7で指定された分周比Nでもつて分周する。Here, FIG. 1 is a diagram showing an example of the configuration of a PLL, FIG. 2 is a diagram illustrating the operation of a phase comparator in a PLL synthesizer, and FIG. 3 is a diagram illustrating the operation of an unlock detection circuit. In Fig. 1, 1 is a reference frequency oscillation circuit, 2 is a fixed frequency divider that divides the output signal of the reference frequency oscillation circuit 1, and 3 is the output of the fixed frequency divider 2 (see Fig. 2a). It is input as a signal, and the phase is compared with the output signal of the variable frequency divider 6 (FIG. 2b), and the phase difference signal PD or LD as shown in FIG. 2c and d is obtained.
4 is a low-pass filter (LPE) that converts the output signal PD of the yielding phase comparator 3 into a DC signal for controlling the oscillation frequency; 5 is a variable frequency whose oscillation frequency is controlled by the output signal of the LPF 4; The variable frequency divider 6 divides the output signal of the VC05 by a division ratio N specified by the code converter 7.
ここでPLLシンセサィザがロック状態のときVC05
の出力周波数〆vco,基準周波数発振回路1の周波数
ナr、可変分周器の分周比Nとの間には〆VC。Here, when the PLL synthesizer is in the locked state, VC05
There is a voltage limit VC between the output frequency ↑vco, the frequency r of the reference frequency oscillation circuit 1, and the frequency division ratio N of the variable frequency divider.
=NXナrの関係がある。= There is a relationship between NX and N.
上記1〜6がPLLシンセサィザの基本構成である。前
記コードコンバータ7はチャンネル番号をBCDコード
あるいはバイナリーコード等のチャンネル選択コード信
号イで入力され、その一方の出力である分周比指定信号
口により可変分局器6の分周比を指定し、チャンネル番
号に対応するVCO出力周波数が得られるように動作す
る。1 to 6 above are the basic configurations of a PLL synthesizer. The code converter 7 receives the channel number as a channel selection code signal such as a BCD code or a binary code, and specifies the frequency division ratio of the variable division divider 6 through the frequency division ratio designation signal port, which is one output, and selects the channel number. It operates to obtain the VCO output frequency corresponding to the number.
8は該コードコンバータ7へ入力されるチャンネル選択
コードが不正規のコードか否かを判定する不正規コード
検出回路で、不正親のコードの時は“1”を出力し、正
規のコードの時は“0”を出力する(第3図a)。Reference numeral 8 denotes an irregular code detection circuit that determines whether the channel selection code input to the code converter 7 is an irregular code or not, and outputs "1" when the code is from an unauthorized parent, and outputs "1" when the code is a regular code. outputs "0" (Figure 3a).
9は前記位相比較器3の出力信号LDのパルス中を検出
するLDパルス中検出回路で、該出力信号LDが一定時
間7以上‘‘0’’になっているか杏かを判定し、一定
時間7を越えて“0”になっている間は“1”を出力し
、その他の間は“0”を出力する(第3図b,c)。Reference numeral 9 denotes an LD pulse detection circuit that detects when the output signal LD of the phase comparator 3 is in a pulse state, and determines whether the output signal LD is ``0'' for a certain period of time or more, and detects whether the output signal LD is ``0'' for a certain period of time. While it exceeds 7 and becomes "0", it outputs "1", and during other times it outputs "0" (Fig. 3 b, c).
10は前記VC05の出力を遮断するVCO出力遮断制
御回路で、前記不正親コード検出回路3の出力と前記L
Dパルス中検出回路9の出力とが入力され、前記2入力
のうち、いずれか一方または両方が“1”となっている
間および“1”から“0”になってから一定時間Tの間
は“0”を出力し、そに他の間は“1”を出力する(第
3図d)。10 is a VCO output cutoff control circuit that cuts off the output of the VC05, which connects the output of the fraudulent parent code detection circuit 3 and the L
While the output of the D-pulse detecting circuit 9 is input, one or both of the two inputs is "1", and for a certain period of time T after it changes from "1" to "0". outputs "0" during the other times, and outputs "1" during the other times (Fig. 3d).
11は前記VCO出力遮断制御回路10の出力が“1”
の間はVC05出力を通し、“0”の間は遮断するスイ
ッチ回路である。11 indicates that the output of the VCO output cutoff control circuit 10 is “1”
This is a switch circuit that passes the VC05 output during the period between 0 and 1, and cuts off the VC05 output during the period of "0".
上記8〜10でアンロック検出回路Aが構成されている
。上記のPLLシンセサイザにおいて、コードコンバー
タ7に入力されるチャンネル選択コード信号イが正常で
かつ位相比較器3の出力信号LDのパルス中が一定時間
?以内すなわち正常なロック状態では、VC05出力は
スイッチ回路1 1を通して出力されているが、位相比
較器3の出力信号LDのパルス中が一定時間を越えてい
る場合すなわちアンロック状態の時あるいはコードコン
バータ7の入力コード信号イが不正現なコードの時はV
C05出力はスイッチ回路1 1により遮断され、後段
に出力されることがない。8 to 10 above constitute an unlock detection circuit A. In the above PLL synthesizer, is it true that the channel selection code signal A input to the code converter 7 is normal and the output signal LD of the phase comparator 3 is in the pulse for a certain period of time? Within this period, that is, in a normal locked state, the VC05 output is output through the switch circuit 11, but if the pulse of the output signal LD of the phase comparator 3 exceeds a certain period of time, that is, in an unlocked state or the code converter V when the input code signal A of 7 is an invalid code.
The C05 output is cut off by the switch circuit 11 and is not output to the subsequent stage.
しかし上記の如き構成においては次の如き問題が発生す
る。However, in the above configuration, the following problems occur.
すなわちVC05の出力信号はPLLシンセサィザがア
ンロック状態になった場合即座に遮断されなければなら
ないのに対し、位相比較器3での位相比較‘サ秒毎‘こ
なされるため最大影の遅れを生じることである。またア
ンロック検出回路Aの感度を上げるためには前記LDパ
ルス中検出回路9の↑を小さくする必要があるがこれを
一定値以下にするとPLLシンセサイザ中の信号ライン
、電源ライン、等に車畳している極く低レベルの雑音、
スイッチ回路11のON−OFF、あるいは装置全体の
振動等によってT以上のパルス中の信号が出力され、ア
ンロック検出回路Aが動作し、VC05の出力を遮断す
る必要のないときに屡々遮断されてしまう。また前記ィ
を大きくするとPLLシンセサイザのアン。ツク時VC
05出力を遮断するタイミングが遅れたり、全く遮断さ
れないことになり、その間正常でないVC05出力が後
段に送られることになる。さらに、チャンネル切換時、
チャンネル選択コ−ド信号イが変更されても即時にァン
ロック状態雌出できず。跡働く欧ケ秒の時間遅れが生じ
る。In other words, the output signal of VC05 must be cut off immediately when the PLL synthesizer becomes unlocked, whereas the phase comparison in the phase comparator 3 is performed 'every subsecond', which causes a maximum delay. It is. In addition, in order to increase the sensitivity of the unlock detection circuit A, it is necessary to reduce the value ↑ of the LD pulse detection circuit 9, but if this is made below a certain value, the signal line, power supply line, etc. in the PLL synthesizer will be very low level noise,
When the switch circuit 11 is turned ON and OFF or the entire device vibrates, a pulse signal of T or more is output, and the unlock detection circuit A is activated, which often causes the output of VC05 to be cut off when there is no need to do so. Put it away. Also, if you increase the above value, the value of A of the PLL synthesizer increases. VC when picking
The timing of cutting off the 05 output may be delayed or may not be cut off at all, and during that time, the abnormal VC05 output will be sent to the subsequent stage. Furthermore, when switching channels,
Even if the channel selection code signal is changed, the lock state cannot be immediately activated. However, there will be a time delay of 1 second.
従ってコード信号イの変更時より所定の時間(最大ナ砂
経過しなし、とアンロッ状態が検出できないので、VC
05の出力信号の遮断が遅れてしまう。このような状態
でもアンロツク状態の検出を早くするためには、LDパ
ルス中検出回路9の7を小さくすればよいが、7を小さ
くすると、前述の如く雑音等によりアンロック検出回路
が謀動することになる。本発明は上記各問題点を解決し
たもので、位相比較器出力の位相差信号LDのパルス中
が一定時間7を越えた場合すなわちアンロック状態にな
った時、あるいはコードコンバータの入力コード信号が
不正規になった時もしくはチャンネル切換時肌し、て・
位相比較の最大ウ秋遅れは機動作を防止できるPLLシ
ンセサィザ用アンロック検出回路を提供することを目的
としている。Therefore, since the predetermined time (maximum number) has not elapsed since the code signal A was changed and the unlocked state cannot be detected, the VC
05's output signal is delayed. In order to detect the unlocked state quickly even in such a state, it is possible to make the value 7 of the LD pulse detection circuit 9 small.However, if 7 is made small, the unlock detection circuit will be disturbed by noise etc. as mentioned above. It turns out. The present invention solves each of the above-mentioned problems.When the pulse of the phase difference signal LD output from the phase comparator exceeds a certain period of time 7, that is, when the unlock state is reached, or when the input code signal of the code converter is When it becomes illegal or when changing channels,
The purpose of the maximum fall delay of phase comparison is to provide an unlock detection circuit for a PLL synthesizer that can prevent mechanical operation.
このため、本発明は、位相比較器出力パルス中が一定値
以上となったとき、チャンネル選択信号入力が正規のチ
ャンネルに対応するコードでないとき、およびチャンネ
ル選択信号が変化したときの3つの条件の内、少なくと
も1つを満足した場合、および満足しなくなってから一
定時間可変周波数発振器(VCO)の出力を遮断するも
のである。以下その一実施例を図面に基づいて説明する
。Therefore, the present invention satisfies three conditions: when the phase comparator output pulse exceeds a certain value, when the channel selection signal input is not a code corresponding to a regular channel, and when the channel selection signal changes. The output of the variable frequency oscillator (VCO) is cut off for a certain period of time when at least one of these conditions is satisfied and after the condition is no longer satisfied. One embodiment will be described below based on the drawings.
第4図において、6,7は第1図と同じものである。1
2はコードコンバータ7の出力である分周比指定信号口
を一定時間7′遅延させる遅延回路で、その出力の遅延
分周比指定信号口により可変分周器6の分周比Nの指定
はそれだけ遅延される。In FIG. 4, 6 and 7 are the same as in FIG. 1
Reference numeral 2 denotes a delay circuit that delays the frequency division ratio designation signal port, which is the output of the code converter 7, by a certain period of time 7', and the frequency division ratio N of the variable frequency divider 6 is specified by the delayed frequency division ratio designation signal port of the output. It will be delayed accordingly.
13はコードコンバータ7の出力口と遅延回路12の出
力口′を比較する不一致検出回路で、一致していない間
は“1”を出力し、一致している間は“0”を出力する
。Reference numeral 13 denotes a mismatch detection circuit that compares the output port of the code converter 7 and the output port ' of the delay circuit 12, and outputs "1" when they do not match, and outputs "0" when they match.
これら12,13でチャンネル切≠奥検出回路Bが構成
されている。14はVCOの出力を遮断するVCO出力
遮断制御回路で、不正親コード検出回路8、LDパルス
中検出回路9および不一致検出回路13の出力のうち少
なくとも一出力が“1”となっている間および“1”か
ら“0”になってから一定時間Tの間は“0”を出力し
、その他の間は“1”を出力する。These 12 and 13 constitute a channel cut≠back detection circuit B. Reference numeral 14 denotes a VCO output cutoff control circuit that cuts off the output of the VCO, and when at least one of the outputs of the invalid parent code detection circuit 8, the LD pulse detection circuit 9, and the mismatch detection circuit 13 is "1", After changing from "1" to "0", "0" is output for a certain period of time T, and "1" is output for the rest of the time.
従ってアンロック検出回路8,9,12〜14で構成さ
れることになる。次にその動作について説明する。Therefore, the unlock detection circuit is composed of unlock detection circuits 8, 9, 12-14. Next, its operation will be explained.
チャンネルが切換えられた瞬間、可変分周器6への分周
比指定信号口は遅延回路12により時間丁′だけ遅れて
可変分周器6に到達する。従って遅延分周比指定信号口
′が発生するまでの間は不一致検出回路13は“1”を
出力し、VCO出力遮断制御回路14は“0”を出力し
、スイッチ回路1 1はVCO出力を遮断する。次に時
間7′経過後以後は不一致回路13は‘‘0’’を出力
し、さらに時間T経過後以後はVCO出力遮断制御回路
14は“1”を出力し、スイッチ回路11はVCO出力
を通す。従ってチャンネル選択コードが変化した瞬間す
なわちチャンネルが切換えられた瞬間は不一致検出回路
13の動作によりスイッチ回路1 1でVCO出力が遮
断されることになり、LDパルス中検出回路9の感度を
上げる(?を4・さくすること)ことなしで、PLLシ
ンセサイザがアンロツクになった瞬間から不正常なVC
O出力を後段に出力しないようにスイッチ回路11を動
作させることができる。なお第4図においては遅延回路
12はコードコンバータ7と可変分周器6の間に挿入さ
れているがコードコンバータ7の前段(チャンネル選択
コード入力端子とコードコンパ−夕の間)に挿入されて
もよいことは云うまでもない。At the moment when the channel is switched, the frequency division ratio designation signal input to the variable frequency divider 6 reaches the variable frequency divider 6 after being delayed by the delay circuit 12 by a time t'. Therefore, until the delayed frequency division ratio designation signal port is generated, the mismatch detection circuit 13 outputs "1", the VCO output cutoff control circuit 14 outputs "0", and the switch circuit 11 outputs "0". Cut off. Next, after time 7' has passed, the mismatch circuit 13 outputs ``0'', and after time T has passed, the VCO output cutoff control circuit 14 outputs "1", and the switch circuit 11 outputs ``1''. Pass. Therefore, at the moment the channel selection code changes, that is, the moment the channel is switched, the VCO output is cut off by the switch circuit 11 due to the operation of the mismatch detection circuit 13, and the sensitivity of the LD pulse detection circuit 9 is increased (? 4) Abnormal VC occurs from the moment the PLL synthesizer is unlocked.
The switch circuit 11 can be operated so as not to output the O output to the subsequent stage. In FIG. 4, the delay circuit 12 is inserted between the code converter 7 and the variable frequency divider 6, but it is inserted before the code converter 7 (between the channel selection code input terminal and the code converter). Needless to say, it's a good thing.
以上本発明によれば、位相比較器出力パルス中が一定値
を越えた時、コードパターン入力コード信号が不正親に
なった時あるいはチャンネル切換時1こおし、て・位相
比較の最大方砂の遅れはる問題点を解消し、誤動作の少
ないァンロック検出回路を得ることができる。As described above, according to the present invention, when the output pulse of the phase comparator exceeds a certain value, when the code pattern input code signal becomes an invalid parent, or when switching channels, the maximum value of the phase comparison is It is possible to solve the problem of delay and obtain an unlock detection circuit with fewer malfunctions.
第1図は従来のPLLシンセサィザ構成例図、第2図お
よび第3図は該PLL中の位相比較器およびアンロック
検出回路の動作説明図、第4図は本発明の一実施例を示
す構成図である。
3…・・・位相比較器、5……可変周波数発振器(VC
O)、6・・・・・・可変分周器、7・・・・・・コー
ドコンバータ、8…・・・不正規コード検出回路、9…
・・・LDパルス中検出回路、10・…・・可変周波数
発振器出力遮断制御回路、11・・・・・・スイッチ回
路、12・・・・・・遅延回路、13…・・・不一致検
出回路、14・・・・・・可変周波数発振器出力遮断制
御回路。
第1図第2図
第3図
第4図FIG. 1 is an example of the configuration of a conventional PLL synthesizer, FIGS. 2 and 3 are diagrams explaining the operation of the phase comparator and unlock detection circuit in the PLL, and FIG. 4 is a configuration showing an embodiment of the present invention. It is a diagram. 3... Phase comparator, 5... Variable frequency oscillator (VC
O), 6... variable frequency divider, 7... code converter, 8... irregular code detection circuit, 9...
...LD pulse detection circuit, 10...Variable frequency oscillator output cutoff control circuit, 11...Switch circuit, 12...Delay circuit, 13...Discrepancy detection circuit , 14... Variable frequency oscillator output cutoff control circuit. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
し、一定値以上の間信号を出力するパルス巾検出回路と
、チヤンネル選択信号入力が正規のチヤンネルに対応す
るコードか否かを判定し、不正規のコードが入力された
場合これが解除されるまで不正規コード検出信号を出力
する不正規コード検出回路と、チヤンネル選択信号が変
化したか否かを検出し、変化した瞬間一定時間中のチヤ
ンネル切換信号を出力するチヤンネル切換検出回路と、
前記3回路出力のうち少なくとも一出力がある間および
全出力が消去してから一定時間可変周波数発振器出力遮
断信号を出力する可変周波数発振器出力遮断制御回路と
を有することを特徴とするPLLシンセサイザ用アンロ
ツク検出回路。1 A pulse width detection circuit that determines whether the phase comparator output pulse width is a certain value or more and outputs a signal while it is over a certain value, and a pulse width detection circuit that determines whether the channel selection signal input is a code that corresponds to a regular channel. However, if an irregular code is input, there is an irregular code detection circuit that outputs an irregular code detection signal until it is released, and a circuit that detects whether or not the channel selection signal has changed, and detects whether or not the channel selection signal has changed, and detects whether or not the channel selection signal has changed. a channel switching detection circuit that outputs a channel switching signal;
A variable frequency oscillator output cutoff control circuit that outputs a variable frequency oscillator output cutoff signal while at least one of the three circuit outputs is present and for a certain period of time after all outputs are erased. detection circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53047450A JPS6029258B2 (en) | 1978-04-20 | 1978-04-20 | Unlock detection circuit for PLL synthesizer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53047450A JPS6029258B2 (en) | 1978-04-20 | 1978-04-20 | Unlock detection circuit for PLL synthesizer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54139365A JPS54139365A (en) | 1979-10-29 |
JPS6029258B2 true JPS6029258B2 (en) | 1985-07-09 |
Family
ID=12775482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53047450A Expired JPS6029258B2 (en) | 1978-04-20 | 1978-04-20 | Unlock detection circuit for PLL synthesizer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029258B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56102129A (en) * | 1980-01-18 | 1981-08-15 | Nec Corp | Frequency synthesizer |
US4409564A (en) * | 1981-03-20 | 1983-10-11 | Wavetek | Pulse delay compensation for frequency synthesizer |
-
1978
- 1978-04-20 JP JP53047450A patent/JPS6029258B2/en not_active Expired
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Publication number | Publication date |
---|---|
JPS54139365A (en) | 1979-10-29 |
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