JPS6029258B2 - Unlock detection circuit for PLL synthesizer - Google Patents

Description

Detailed Description of the Invention The present invention determines whether or not the PLL is in a normal lock state in a PLL synthesizer, and if the PLL is not in a normal lock state, the PLL
The present invention relates to a so-called unlock detection circuit that outputs a VCO output cutoff control signal for cutting off a variable frequency oscillator (VCO) output signal.

The configuration of a PLL synthesizer including an unlock detection circuit that is commonly used at present will be explained with reference to FIGS. 1 to 3.

Here, FIG. 1 is a diagram showing an example of the configuration of a PLL, FIG. 2 is a diagram illustrating the operation of a phase comparator in a PLL synthesizer, and FIG. 3 is a diagram illustrating the operation of an unlock detection circuit. In Fig. 1, 1 is a reference frequency oscillation circuit, 2 is a fixed frequency divider that divides the output signal of the reference frequency oscillation circuit 1, and 3 is the output of the fixed frequency divider 2 (see Fig. 2a). It is input as a signal, and the phase is compared with the output signal of the variable frequency divider 6 (FIG. 2b), and the phase difference signal PD or LD as shown in FIG. 2c and d is obtained.
4 is a low-pass filter (LPE) that converts the output signal PD of the yielding phase comparator 3 into a DC signal for controlling the oscillation frequency; 5 is a variable frequency whose oscillation frequency is controlled by the output signal of the LPF 4; The variable frequency divider 6 divides the output signal of the VC05 by a division ratio N specified by the code converter 7.

Here, when the PLL synthesizer is in the locked state, VC05
There is a voltage limit VC between the output frequency ↑vco, the frequency r of the reference frequency oscillation circuit 1, and the frequency division ratio N of the variable frequency divider.

= There is a relationship between NX and N.

1 to 6 above are the basic configurations of a PLL synthesizer. The code converter 7 receives the channel number as a channel selection code signal such as a BCD code or a binary code, and specifies the frequency division ratio of the variable division divider 6 through the frequency division ratio designation signal port, which is one output, and selects the channel number. It operates to obtain the VCO output frequency corresponding to the number.

Reference numeral 8 denotes an irregular code detection circuit that determines whether the channel selection code input to the code converter 7 is an irregular code or not, and outputs "1" when the code is from an unauthorized parent, and outputs "1" when the code is a regular code. outputs "0" (Figure 3a).

Reference numeral 9 denotes an LD pulse detection circuit that detects when the output signal LD of the phase comparator 3 is in a pulse state, and determines whether the output signal LD is ``0'' for a certain period of time or more, and detects whether the output signal LD is ``0'' for a certain period of time. While it exceeds 7 and becomes "0", it outputs "1", and during other times it outputs "0" (Fig. 3 b, c).

10 is a VCO output cutoff control circuit that cuts off the output of the VC05, which connects the output of the fraudulent parent code detection circuit 3 and the L
While the output of the D-pulse detecting circuit 9 is input, one or both of the two inputs is "1", and for a certain period of time T after it changes from "1" to "0". outputs "0" during the other times, and outputs "1" during the other times (Fig. 3d).

11 indicates that the output of the VCO output cutoff control circuit 10 is “1”
This is a switch circuit that passes the VC05 output during the period between 0 and 1, and cuts off the VC05 output during the period of "0".

8 to 10 above constitute an unlock detection circuit A. In the above PLL synthesizer, is it true that the channel selection code signal A input to the code converter 7 is normal and the output signal LD of the phase comparator 3 is in the pulse for a certain period of time? Within this period, that is, in a normal locked state, the VC05 output is output through the switch circuit 11, but if the pulse of the output signal LD of the phase comparator 3 exceeds a certain period of time, that is, in an unlocked state or the code converter V when the input code signal A of 7 is an invalid code.
The C05 output is cut off by the switch circuit 11 and is not output to the subsequent stage.

However, in the above configuration, the following problems occur.

In other words, the output signal of VC05 must be cut off immediately when the PLL synthesizer becomes unlocked, whereas the phase comparison in the phase comparator 3 is performed 'every subsecond', which causes a maximum delay. It is. In addition, in order to increase the sensitivity of the unlock detection circuit A, it is necessary to reduce the value ↑ of the LD pulse detection circuit 9, but if this is made below a certain value, the signal line, power supply line, etc. in the PLL synthesizer will be very low level noise,
When the switch circuit 11 is turned ON and OFF or the entire device vibrates, a pulse signal of T or more is output, and the unlock detection circuit A is activated, which often causes the output of VC05 to be cut off when there is no need to do so. Put it away. Also, if you increase the above value, the value of A of the PLL synthesizer increases. VC when picking
The timing of cutting off the 05 output may be delayed or may not be cut off at all, and during that time, the abnormal VC05 output will be sent to the subsequent stage. Furthermore, when switching channels,
Even if the channel selection code signal is changed, the lock state cannot be immediately activated. However, there will be a time delay of 1 second.

Therefore, since the predetermined time (maximum number) has not elapsed since the code signal A was changed and the unlocked state cannot be detected, the VC
05's output signal is delayed. In order to detect the unlocked state quickly even in such a state, it is possible to make the value 7 of the LD pulse detection circuit 9 small.However, if 7 is made small, the unlock detection circuit will be disturbed by noise etc. as mentioned above. It turns out. The present invention solves each of the above-mentioned problems.When the pulse of the phase difference signal LD output from the phase comparator exceeds a certain period of time 7, that is, when the unlock state is reached, or when the input code signal of the code converter is When it becomes illegal or when changing channels,
The purpose of the maximum fall delay of phase comparison is to provide an unlock detection circuit for a PLL synthesizer that can prevent mechanical operation.

Therefore, the present invention satisfies three conditions: when the phase comparator output pulse exceeds a certain value, when the channel selection signal input is not a code corresponding to a regular channel, and when the channel selection signal changes. The output of the variable frequency oscillator (VCO) is cut off for a certain period of time when at least one of these conditions is satisfied and after the condition is no longer satisfied. One embodiment will be described below based on the drawings.

In FIG. 4, 6 and 7 are the same as in FIG. 1
Reference numeral 2 denotes a delay circuit that delays the frequency division ratio designation signal port, which is the output of the code converter 7, by a certain period of time 7', and the frequency division ratio N of the variable frequency divider 6 is specified by the delayed frequency division ratio designation signal port of the output. It will be delayed accordingly.

Reference numeral 13 denotes a mismatch detection circuit that compares the output port of the code converter 7 and the output port ' of the delay circuit 12, and outputs "1" when they do not match, and outputs "0" when they match.

These 12 and 13 constitute a channel cut≠back detection circuit B. Reference numeral 14 denotes a VCO output cutoff control circuit that cuts off the output of the VCO, and when at least one of the outputs of the invalid parent code detection circuit 8, the LD pulse detection circuit 9, and the mismatch detection circuit 13 is "1", After changing from "1" to "0", "0" is output for a certain period of time T, and "1" is output for the rest of the time.

Therefore, the unlock detection circuit is composed of unlock detection circuits 8, 9, 12-14. Next, its operation will be explained.

At the moment when the channel is switched, the frequency division ratio designation signal input to the variable frequency divider 6 reaches the variable frequency divider 6 after being delayed by the delay circuit 12 by a time t'. Therefore, until the delayed frequency division ratio designation signal port is generated, the mismatch detection circuit 13 outputs "1", the VCO output cutoff control circuit 14 outputs "0", and the switch circuit 11 outputs "0". Cut off. Next, after time 7' has passed, the mismatch circuit 13 outputs ``0'', and after time T has passed, the VCO output cutoff control circuit 14 outputs "1", and the switch circuit 11 outputs ``1''. Pass. Therefore, at the moment the channel selection code changes, that is, the moment the channel is switched, the VCO output is cut off by the switch circuit 11 due to the operation of the mismatch detection circuit 13, and the sensitivity of the LD pulse detection circuit 9 is increased (? 4) Abnormal VC occurs from the moment the PLL synthesizer is unlocked.
The switch circuit 11 can be operated so as not to output the O output to the subsequent stage. In FIG. 4, the delay circuit 12 is inserted between the code converter 7 and the variable frequency divider 6, but it is inserted before the code converter 7 (between the channel selection code input terminal and the code converter). Needless to say, it's a good thing.

As described above, according to the present invention, when the output pulse of the phase comparator exceeds a certain value, when the code pattern input code signal becomes an invalid parent, or when switching channels, the maximum value of the phase comparison is It is possible to solve the problem of delay and obtain an unlock detection circuit with fewer malfunctions.

[Brief explanation of the drawing]

FIG. 1 is an example of the configuration of a conventional PLL synthesizer, FIGS. 2 and 3 are diagrams explaining the operation of the phase comparator and unlock detection circuit in the PLL, and FIG. 4 is a configuration showing an embodiment of the present invention. It is a diagram. 3... Phase comparator, 5... Variable frequency oscillator (VC
O), 6... variable frequency divider, 7... code converter, 8... irregular code detection circuit, 9...
...LD pulse detection circuit, 10...Variable frequency oscillator output cutoff control circuit, 11...Switch circuit, 12...Delay circuit, 13...Discrepancy detection circuit , 14... Variable frequency oscillator output cutoff control circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 A pulse width detection circuit that determines whether the phase comparator output pulse width is a certain value or more and outputs a signal while it is over a certain value, and a pulse width detection circuit that determines whether the channel selection signal input is a code that corresponds to a regular channel. However, if an irregular code is input, there is an irregular code detection circuit that outputs an irregular code detection signal until it is released, and a circuit that detects whether or not the channel selection signal has changed, and detects whether or not the channel selection signal has changed, and detects whether or not the channel selection signal has changed. a channel switching detection circuit that outputs a channel switching signal;
A variable frequency oscillator output cutoff control circuit that outputs a variable frequency oscillator output cutoff signal while at least one of the three circuit outputs is present and for a certain period of time after all outputs are erased. detection circuit.