JPH09162726A - Clock signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction by controlling the inhibition of clock signal output by measuring an input frequency, comparing it with a prescribed value and also discriminating that the input frequency gets out of a prescribed range even in the case of input interruption. SOLUTION: In a clock signal generator for generating the clock signal of N-fold frequency phase-locked with an input signal, the input signal is branched and measured by a frequency measuring circuit 21. A measured value 108 is decoded by a decoder 22 and compared with a prescribed value and it is discriminated whether that measured value is included in the prescribed numerical range or not. When it is discriminated that the frequency value is not included in the prescribed value, the decoder 22 generates an output 109 and while receiving this signal, an ON/OFF circuit 15 inhibits the output of clock signal output 105. Even when there is no input signal 101, the decoder 22 also discriminates that the input signal frequency gets out of the prescribed range. Thus, the malfunction of clock signal generator caused by any abnormal input signal is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generator for generating a clock signal having a frequency N times (N is a predetermined constant) in phase with an input signal, and more particularly from a predetermined frequency range. The present invention relates to a clock signal generator that prevents a malfunction due to a deviated input signal.

[0002]

2. Description of the Related Art N times (N is
There is already known a clock signal generator that generates a clock signal having a frequency of a predetermined constant) and has a function of cutting off the output of the clock signal when the input signal becomes abnormal. ing. FIG. 2 is a block diagram showing a configuration of a conventional clock signal generator having such a function. That is, the clock signal generator includes a phase comparator 12 supplied with an input reference signal 101 from an input terminal 11, a low pass filter (LPF) 13 supplied with the output signal 103, and a voltage supplied with the output signal. Controlled oscillator 14, output ON / OFF circuit 15 to which this output signal is supplied, 1 / N frequency divider 16 to which the output signal of LPF 13 is branched, and input terminal 1
It is composed of an input break detection circuit 19 to which the input reference signal 101 from 1 is branched and supplied. And 1 / N divider 16
The frequency division ratio is controlled by the frequency division ratio setting signal 106 from the terminal 17, the frequency division output signal 102 is supplied to the phase comparator 12 as a comparison input signal, and the output of the input disconnection detection circuit 19 is output. It is supplied to the ON / OFF circuit 15 as a control signal, and the output of the output ON / OFF circuit 15 is taken out to the output terminal 18.

Next, the circuit operation of such a conventional clock signal generator will be described.

Input reference signal 101 and divided output signal 102
Are compared by the phase comparator 12, and the phase comparison output 103 output according to the comparison result of the phase comparator 12 is integrated and smoothed by the LPF 3 to control the output frequency of the voltage controlled oscillator 14. On the other hand, when the input reference signal 101 is disconnected, the input disconnection detection circuit 19 detects the input disconnection, outputs the input disconnection signal 107, and the output ON / OFF circuit 15 outputs the output from the output terminal 18 of the clock signal output 105. It was prohibited.

Further, Japanese Patent Application Laid-Open No. 5-14760 discloses that
PLL having a frequency measuring unit, a polarity determining unit, and a pulse width measuring unit for each of the horizontal synchronizing signal and the vertical synchronizing signal
A clock recovery circuit including a circuit is disclosed. This clock recovery circuit measures the frequency, polarity, and pulse width of the horizontal sync signal and the frequency, polarity, and pulse width of the vertical sync signal, determines the type of signal source, and determines the division ratio according to that signal source. Is automatically set.

[0006]

The conventional clock signal generator shown in FIG. 2 prohibits the clock signal output only when the input signal is in the cutoff state, but the abnormal input signal is out of the predetermined frequency range. When is input, there is a problem that the clock signal output is sent out.

Further, in the clock reproducing circuit described in Japanese Patent Laid-Open No. 5-14760, even if the frequency of the input signal becomes abnormal, the setting of the frequency division ratio is changed and the clock signal output is similarly sent out.

Therefore, an object of the present invention is to provide a clock signal generator which prevents malfunction due to an input reference signal outside a predetermined frequency range.

[0009]

According to the present invention, a phase comparator supplied with an input reference signal from an input terminal, a low-pass filter supplied with an output signal of the phase comparator, and a low-pass filter of the low-pass filter A voltage-controlled oscillator to which an output signal is supplied, an output ON / OFF circuit to which the output signal of the voltage-controlled oscillator is supplied, and an output signal of the low-pass filter are branched and supplied, and the divided output thereof is supplied to the phase comparator. A 1 / N frequency divider supplied as a comparison input signal, a frequency measuring circuit to which an input reference signal from the input terminal is branched and supplied, and a frequency measurement value by this frequency measuring circuit are supplied, and this value is a predetermined value. It is determined whether or not it is included in the range, and if it is not included, the output is turned ON / O by its output.
A clock signal generator comprising a frequency range determination circuit for switching an FF circuit to a cutoff state.

Further, according to the present invention, the frequency range determination circuit is also provided when the input reference signal is in a disconnected state.
A clock signal generator characterized in that it is determined that the frequency of the input reference signal is not within a predetermined range, and the output thereof is switched to a cutoff state by the output thereof. .

Further, according to the present invention, the frequency range determination circuit is a decoder which is supplied with a frequency measurement value by the frequency measurement circuit and compares whether or not the value is within a predetermined range. A clock signal generator that operates is obtained.

[0012]

According to the clock signal generator of the present invention, the frequency of the input reference signal is measured, and the measured value is compared with a predetermined value. As a result, when the frequency of the input reference signal is out of the predetermined range, The output ON / OFF circuit is switched to the cutoff state to prohibit the clock signal output.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the drawings. 1 is a block diagram of a clock signal generator according to an embodiment of the present invention. In FIG. 1,
The same parts as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, this clock signal generator
The phase comparator 11 to which the input reference signal 101 from the input terminal 11 is supplied, and the output signal 103 of this phase comparator 11.
Is supplied to the low-pass filter (LPF) 13, a voltage-controlled oscillator 14 to which the output signal 104 of the LPF 13 is supplied, an output ON / OFF circuit 15 to which an output signal 105 of the voltage-controlled oscillator 14 is supplied, LPF1
3 output signal 104 is branched and supplied, and its frequency division output 102
Is supplied to the phase comparator 12 as the comparison input signal 102 and the frequency measuring circuit 22 to which the input reference signal 101 from the input terminal 11 is branched.
And the frequency measurement value 108 by this frequency measurement circuit 22.
Is supplied, and it is determined whether or not this value falls within a predetermined range, and if it does not, a decoder 22 which is a frequency range determination circuit that switches the output ON / OFF circuit to the cutoff state by its output 109. It is configured. The 1 / N frequency divider 16 is supplied with the frequency division ratio setting signal 106 from the terminal 17 to control the frequency division ratio.

Next, this operation will be described.

Input reference signal 101 and divided output signal 102
Are compared by the phase comparator 12, and the phase comparison output 103 output according to the comparison result of the phase comparator 12 is integrated and smoothed by the LPF 3 to control the output frequency of the voltage controlled oscillator 14. On the other hand, a part of the input reference signal 101 is branched and supplied to the frequency measuring circuit 22, where the frequency is measured. The counted measurement value 108 is decoded by the decoder 22, and then the decoded value is compared with a predetermined value to determine whether or not it is included in a predetermined numerical value range. When the decoder 22 determines that the frequency value does not fall within the predetermined range, it generates the output 109, supplies it to the output ON / OFF circuit 15, switches it to the cutoff state, and outputs it from the output terminal 18 of the clock signal output 105. Prohibit output.

The decoder 22 also includes an input reference signal 101.
The predetermined range is set so that it is determined that the frequency of the input reference signal 101 is out of the predetermined range even when is disconnected.

[0017]

According to the present invention described above, not only when the input reference signal is cut off, but also when the frequency of the input reference signal is out of the predetermined range, the output ON / OFF circuit is cut off. Since the clock signal output is prohibited and controlled, it is possible to prevent malfunction of the clock signal generator due to an abnormal input signal outside the predetermined frequency range.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock signal generator according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventionally known clock signal generator.

[Explanation of symbols]

 11 Input Signal Terminal 12 Phase Comparator 13 LPF 14 Voltage Controlled Oscillator 15 Output ON / OFF Circuit 16 1 / N Divider 17 Dividing Ratio Setting Signal Terminal 18 Output Signal Terminal 19 Input Loss Detection Circuit 21 Frequency Measurement Circuit 22 Decoding Circuit 101 Input reference signal 102 Frequency division output signal 103 Phase comparator output 104 LPF output 105 Clock signal output 106 Frequency division ratio setting signal 107 Input disconnection signal 108 Frequency value output 109 Output prohibition signal

Claims (3)

[Claims] 1. A phase comparator supplied with an input reference signal from an input terminal, a low-pass filter supplied with an output signal of the phase comparator, and a voltage controlled oscillator supplied with an output signal of the low-pass filter. An output ON / OFF circuit to which the output signal of the voltage controlled oscillator is supplied, and an output signal of the low pass filter are branched and supplied, and the divided output thereof is supplied to the phase comparator as a comparison input signal 1 / N. A frequency divider, a frequency measurement circuit to which the input reference signal from the input terminal is branched, and a frequency measurement value by this frequency measurement circuit are supplied, and it is determined whether or not this value falls within a predetermined range. And a frequency range determination circuit that switches the output ON / OFF circuit to a cutoff state by its output when not included. 2. The frequency range determination circuit determines that the frequency of the input reference signal is not within a predetermined range even when the input reference signal is in a disconnected state, and outputs the output to turn on / off the output. The clock signal generator according to claim 1, wherein the clock signal generator is configured to switch the OFF circuit to a cutoff state. 3. The frequency range determination circuit is a decoder supplied with a frequency measurement value by the frequency measurement circuit and comparing whether the value is within a predetermined range or not. Clock signal generator.