JPH11136124A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an output signal that synthesizes with an input signal even at the time of switching the output signal by switching the output signal when the frequency of the input signal becomes in an oscillation frequency range that is partially overlapped. SOLUTION: A 1st VCO 1 outputs an oscillation output of a prescribed oscillation frequency to a 1st frequency divider 4 in accordance with voltage that is inputted from a 1st LPF 2. A 2nd VCO 6 outputs an oscillation output of the prescribed oscillation frequency to a 2nd frequency divider 9 in accordance with voltage that is inputted from a 2nd LPF 7. The VCOs 1 and 6 have different oscillation frequency ranges to input voltage and also overlap a part of the oscillation frequency ranges in a prescribed range of input voltage. A voltage detection circuit 5 outputs a selection signal which selects either of frequency outputs from the divider 4 or the divider 9 to a selection circuit 10 by detecting input voltage from the LPFs 2 and 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit for generating a signal synchronized with an input signal.

[0002]

2. Description of the Related Art P which generates a signal synchronized with an input signal
In an LL circuit, one of PLL circuits for synchronizing with an input signal having a wide frequency range includes a plurality of voltage controlled oscillators having different oscillation frequency ranges, and a plurality of voltage controlled oscillators according to the frequency of the input signal. There is a countermeasure by switching. Hereinafter, the configuration of the conventional PLL circuit will be described with reference to the block diagram shown in FIG.

In FIG. 4, reference numeral 21 denotes a first voltage controlled oscillator (hereinafter, referred to as "VCO"), and reference numeral 22 denotes a second VC.
O, 23 are low-pass filters (hereinafter referred to as “LPF”), 24 is a phase comparator, 25 is a voltage detector, 26 is a selection circuit (MPX), 27 is a frequency divider, 28 is an input terminal,
9 is an output terminal.

[0004] The operation of the conventional PLL circuit configured as described above will be described below with reference to an example in which the frequency division ratio of the frequency divider 27 is 1.

[0005] The phase comparator 24 compares the phase of the input signal input from the input terminal 28 with the phase of the output signal output to the output terminal 29, and outputs the comparison result to the LPF 23. In the LPF 23, the output from the phase comparator 24 is DC
After being converted into a signal, the converted signal is output to the first VCO 21, the second VCO 22, and the voltage detector 25. At this time, the first VCO 21 and the second VCO 22 are voltage controlled oscillators having different oscillation frequency ranges, and oscillate at different frequencies with respect to the output from the LPF 23. First VC
The output of O21 and the output of the second VCO 22 are input to the selection circuit 26, one of which is selected by the output from the voltage detector 25, and the selected signal is output to the frequency divider 27. The signal divided by the divider 27 is outputted to the output terminal 29 and outputted to the phase comparator 24.

As described above, when the phases of the input signal and the output signal are different, the comparison result is output from the phase comparator 24 to the LPF2.
3 to the first VCO 21 and the second VCO 22, and the first VCO 21 according to the comparison result of the phase comparator 24.
The input voltages of the O21 and the second VCO 22 change, and the oscillation frequency serving as the output signal changes accordingly. By repeating this series of operations, an output signal synchronized with the input signal can be obtained.

FIG. 5 shows a characteristic diagram of the oscillation frequency with respect to the input voltage of the first VCO 21 and the second VCO 22 in the conventional PLL circuit as described above. In a conventional PLL circuit having an input voltage-oscillation frequency characteristic as shown in FIG. 5, when the input signal changes from a low frequency to a high frequency, the input frequencies are changed to the first VCO 21 and the second VCO.
When the frequency f1 is covered by both of the VCOs 22, the voltage-controlled oscillator to be used is switched from the first VCO 21 that covers the low frequency side to the second VCO 22 that covers the high frequency side. An output signal synchronized with an input signal up to a high frequency can be obtained.

[0008]

However, in the above-described conventional configuration, when the frequency of the input signal becomes f1, the voltage-controlled oscillator to be used is switched from the first VCO 21 to the second VCO 22. As shown in the timing chart of FIG. 6, the second VC used after the switching
Since O22 is not synchronized with the input signal before switching, the selection circuit 26 switches the first VC0 21 to the second VC02.
There is a problem that an output signal output at the moment of switching to O22 is a signal that is not synchronized with the input signal.

The present invention has been made to solve the above-mentioned conventional problems, and responds to a wide frequency change of an input signal by switching output signals of a plurality of PLL circuits having different oscillation frequency ranges. Another object of the present invention is to provide a PLL circuit which can obtain an output signal synchronized with an input signal even when switching the output signal of the PLL circuit.

[0010]

In order to solve the above problems, a PLL circuit according to the present invention comprises a first PLL circuit having a first voltage-controlled oscillator having a first oscillation frequency range;
A second PLL circuit having a second voltage-controlled oscillator having a second oscillation frequency range in which the first oscillation frequency range partially overlaps with the first oscillation frequency range; the first PLL circuit and the second PLL circuit; And a selection circuit that receives an output signal of the second PLL circuit and selects and outputs one of the output signals, wherein an output signal of the first PLL circuit and an output signal of the second PLL circuit are provided. Each is synchronized with the input signal, and when the frequency of the input signal falls within the frequency range where the partial oscillation frequency range overlaps, switching of the output signal is performed by the selection circuit. I do.

According to this configuration, the oscillating frequency ranges of the first voltage controlled oscillator and the second voltage controlled oscillator partially overlap, and the output signal of the first PLL circuit and the second And the output signal of the PLL circuit is synchronized with the input signal. Therefore, when the frequency of the input signal enters the overlapping frequency range, the selection circuit outputs the second signal from the output signal of the first PLL circuit. , Or from the output signal of the second PLL circuit to the output signal of the first PLL circuit, an output signal always synchronized with the input signal can be obtained.

The PLL circuit detects input voltages of a first voltage-controlled oscillator and a second voltage-controlled oscillator,
Based on the detection result, the first PLL circuit or the second PLL
By providing a voltage detection circuit that outputs a selection signal for selecting one of the output signals of the L circuit to the selection circuit, the output signal can be automatically switched in response to a change in the input voltage. That is, a first switching voltage for switching from an output signal of the first PLL circuit to an output signal of the second PLL circuit to the voltage detection circuit, and an output of the first PLL circuit from an output signal of the second PLL circuit. If the second switching voltage for switching to the signal is set, a selection signal for switching the output signal is output to the selection circuit when the input voltage reaches the switching voltage, and the switching of the output signal is automatically performed. It can be carried out.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to the present embodiment. In FIG. 1, 1 is the first
VCO, 2 is a first LFP, 3 is a first phase comparator,
4 is a first frequency divider, 5 is a voltage detection circuit, and 6 is a second VC.
O and 7 are second LPFs, 8 is a second phase comparator, 9 is a second frequency divider, 10 is a selection circuit (MPX), 11 is an output terminal, and 12 is an input terminal.

The PLL circuit includes a first VCO 1 and a first VCO 1.
, A first PLL circuit composed of an LPF 2, a first phase comparator 3, and a first frequency divider 4, a second VCO 6 and a second
, A second PLL circuit including a second phase comparator 8 and a second frequency divider 9.

The operation of the PLL circuit of the present invention configured as described above will be described below, taking as an example the case where the frequency division ratio of the first frequency divider 4 and the second frequency divider 9 is 1. .

When an input signal is input to the input terminal 12, the phase of the output signal from the first frequency divider 4 obtained by dividing the output of the first VCO 1 and the input signal in the first phase comparator 3 are output. The comparison is performed, and the result is output to the first LPF 2. The first LPF 2 converts the phase comparison result into a DC signal, and outputs the DC signal to the first VCO 1 and the voltage detection circuit 5. Then, the first VCO 1 outputs an oscillation output having a predetermined oscillation frequency to the first frequency divider 4 as shown in FIG. 2 according to the voltage input from the first LPF 2.

The input signal input to the input terminal 12 is also input to the second phase comparator 8. In the second phase comparator 8, the output signal of the second frequency divider 9 obtained by dividing the output of the second VCO 6 is compared with the input signal, and the result is sent to the second LPF 7. Is output. The second LPF 7 converts the phase comparison result into a DC signal, and outputs the DC signal to the second VCO 6 and the voltage detection circuit 5.
Then, the second VCO 6 outputs an oscillation output having a predetermined oscillation frequency to the second frequency divider 9 as shown in FIG. 2 according to the voltage input from the second LPF 7.

As apparent from FIG. 2, the first VCO 1
The second VCO 6 differs from the second VCO 6 in the oscillation frequency range with respect to the input voltage, and has a characteristic that some oscillation frequency ranges f1 and f2 overlap in the range of the input voltage V1 and V2.

In the voltage detection circuit 5, the first LPF 2
And a selection signal for selecting either the divided output from the first divider 4 or the divided output from the second divider 9 by detecting the input voltage from the second LPF 7 and the input voltage from the second LPF 7. Is output to the selection circuit 10. That is, as shown in FIG. 2, when the input voltage from the first LPF 2 becomes equal to or lower than V1, the selection circuit 10 divides the output of the second VCO 6 from the second frequency divider 9 to divide the output. Select the cycle output and select the second LP
When the input voltage from F7 becomes equal to or higher than V2, the selection circuit 10 selects the divided output from the first divider 4 obtained by dividing the output of the first VCO 1 so as to select the divided output. Outputs a selection signal to the selection circuit 10.

Here, when the input voltage from the first LPF 2 becomes V1, the oscillation frequency of the first VCO1 becomes f1,
When the input voltage from the second LPF 7 becomes V2, the second
If the oscillation frequency of the VCO 6 is f2, f1> f2
The switching voltage of the voltage detection circuit 5 is set so as to satisfy the following relationship.

In the configuration of the present invention which operates as described above, when the input signal changes from low frequency to high frequency, the frequency of the input signal is low and the output voltage of the first LPF 2 is higher than V1. The voltage detection circuit 5 controls the selection circuit 10 so as to select the frequency-divided output from the first frequency divider 4 so that the frequency of the input signal is higher than f1 and the first LPF
When the output voltage of the second frequency divider 2 becomes lower than V1, the voltage detection circuit 5 outputs a selection signal for selecting the frequency division output from the second frequency divider 9 to the selection circuit 10, and switches the output signal. At this time, since the second VCO 6 oscillates in synchronization with the input signal as shown in the timing chart of FIG. 3, the selection circuit 10 switches the first frequency divider 4 to the second frequency divider 9
, The output signal synchronized with the input signal can be continuously obtained.

When the input signal changes from a high frequency to a low frequency, the frequency of the input signal becomes high and the second L
When the output voltage of the PF 7 is lower than V2, the voltage detection circuit 5 controls the selection circuit 10 to select the frequency-divided output from the second frequency divider 9, and the frequency of the input signal is lower than f2. When the output voltage of the second LPF 7 becomes higher than V2, the voltage detection circuit 5 outputs a selection signal for selecting the frequency-divided output from the first frequency divider 4 to the selection circuit 10, and switches the output signal. . At this time, the first VCO 1 oscillates in synchronization with the input signal. Therefore, even if the selection circuit 10 switches from the second frequency divider 9 to the first frequency divider 4, the output synchronized with the input signal is output. The signal can be obtained continuously.

In this embodiment, the first VCO 1
The description has been given of the case where the first PLL circuit having the first PLL circuit and the second PLL circuit having the second VCO 6 are always operated. However, in the period where the frequency of the input signal is f1 to f2, both the first and second PLL circuits If the input signal frequency is higher than f1, only the second PLL circuit is operated, and if the input signal frequency is lower than f2, only the first PLL circuit is operated. Effects can be obtained. Thus, power consumption of the PLL circuit can be reduced.

[0025]

As described above, according to the present invention, the first PLL having the voltage controlled oscillators having different oscillation frequency ranges is provided.
Circuit and the second PLL circuit for use by switching.
It can support input signals having a wide frequency range. Moreover, the first PLL circuit and the second PLL circuit
Oscillation frequency ranges partially overlap, and
Since each output signal is synchronized with the input signal, it is possible to always obtain an output signal synchronized with the input signal by switching the output signal when the frequency of the input signal enters the overlapping frequency range. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an input voltage-oscillation frequency characteristic of the voltage controlled oscillator according to the embodiment of the present invention.

FIG. 3 is a timing chart of an output signal according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 5 is a diagram showing an input voltage-oscillation frequency characteristic of a voltage-controlled oscillator in a conventional PLL circuit.

FIG. 6 is a timing chart of an output signal in a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st voltage control type oscillator 2 1st low pass filter 3 1st phase comparator 4 1st frequency divider 5 voltage detection circuit 6 2nd voltage control type oscillator 7 2nd low pass filter 8 2nd Phase comparator 9 Second divider 10 Selection circuit 11 Output terminal 12 Input terminal

 ──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Tamaki Iwasaki 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A first PLL circuit having a first voltage-controlled oscillator having a first oscillation frequency range, and a second oscillation circuit in which the first oscillation frequency range partially overlaps the oscillation frequency range. A second PLL circuit having a second voltage-controlled oscillator having a frequency range, and output signals of the first PLL circuit and the second PLL circuit, and selecting one of the output signals A selection circuit for outputting an output signal of the first PLL circuit and the second PLL circuit.
When the output signal of the L circuit is synchronized with the input signal, and the frequency of the input signal falls within a frequency range in which the partial oscillation frequency range overlaps, the output signal is switched by the selection circuit. Is performed. 2. An input voltage of each of a first voltage-controlled oscillator and a second voltage-controlled oscillator is detected, and based on a result of the detection, an output of one of a first PLL circuit and a second PLL circuit is output. 2. The PLL circuit according to claim 1, further comprising a voltage detection circuit that outputs a selection signal for selecting a signal to the selection circuit.