KR940012944A - Redundancy Control Circuit - Google Patents

Redundancy Control Circuit Download PDF

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Publication number
KR940012944A
KR940012944A KR1019920022290A KR920022290A KR940012944A KR 940012944 A KR940012944 A KR 940012944A KR 1019920022290 A KR1019920022290 A KR 1019920022290A KR 920022290 A KR920022290 A KR 920022290A KR 940012944 A KR940012944 A KR 940012944A
Authority
KR
South Korea
Prior art keywords
signal
control
error
power
generating
Prior art date
Application number
KR1019920022290A
Other languages
Korean (ko)
Inventor
이동현
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019920022290A priority Critical patent/KR940012944A/en
Publication of KR940012944A publication Critical patent/KR940012944A/en

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Abstract

본 발명은 이중화장치에서 전원 공급시 원하는 장치를 동작장치로 선택하고, 이중화 로직 절체시 서로 제어권을 넘겨주는 발진 현상을 방지하는 회로를 제공한다. 이를 위하여 초기전원공급시 리세트부의 출력과 공급전원을 이용하여 동작장치 및 대기장치를 설정하므로서, 초기전원 공급시점에서 발생되는 제어권의 발진 현상을 제거한다. 이후 상대장치의 동작상태를 감시하여 제어권을 절체하여야 하는 경우 상대 장치가 에러상태이면 제어권을 넘기지 않으므로서, 제어권의 발진현상을 방지한다.The present invention provides a circuit for selecting a desired device as an operation device when supplying power from a redundant device, and preventing oscillation phenomena that give control to each other when the redundant logic is switched. To this end, by setting the operating device and the standby device using the output of the reset unit and the supply power at the initial power supply, the oscillation phenomenon of the control right generated at the initial power supply is eliminated. Then, when the control right is to be transferred by monitoring the operation state of the counterpart device, if the counterpart device is in an error state, the control right is not passed, and the oscillation of the control right is prevented.

Description

이중화 장치의 제어회로Redundancy Control Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 이중화장치의 구성도.2 is a block diagram of a redundancy apparatus according to the present invention.

Claims (1)

이중화장치의 제어회로에 있어서, 전원온리세트부와 제1전원을 논리합하고, 상기 전원온리세트부와 제2전원을 논리합하여 초기전원온시 동작장치 및 대기장치를 설정하기 위한 상이한 논리신호를 발생하며, 초기전원리세트 후 동일한 논리 신호를 발생하는 선택수단과, 자기장치 내의 가종 에러신호들을 수신하여 논리곱하여 에러신호를 발생하는 제1수단과, 상대에러신호를 수신하여 상대보드가 에러상태일시 절체를 방지하기 위한 제어신호를 발생하는 제어수단과, 상기 제1수단과 제어수단의 출력을 수신하여 논리곱하여 에러발생시 자기에러신호를 발생하여 상대장치로 출력하는 제2수단과, 출력단이 자기장치의 인에이블단자로 연결되는 동시에 상대장치의 대기신호로 인가되고, 입력단이 상기 선택수단 및 제2수단의 출력단과 연결되는 동시에 상대장치의 대기신호와 연결되며, 수신 신호를 부논리곱하여 동작신호를 발생하는 수단으로 구성된 것을 특징으로 하는 이중화장치의 제어회로.In the control circuit of the redundancy device, the power ON reset unit and the first power supply are ORed together, and the power ON reset unit and the second power supply are ORed to generate different logic signals for setting the operation device and the standby device at the initial power on. Selecting means for generating the same logic signal after the initial power reset, first means for receiving and multiplying the error type signals in the magnetic device to generate an error signal, and receiving the relative error signal to cause the opponent board to be in an error state. Control means for generating a control signal for preventing switching, second means for receiving and logically multiplying the outputs of the first means and the control means to generate a magnetic error signal when an error occurs, and outputting the magnetic error signal to a counterpart device; Connected to the enable terminal of the device and simultaneously applied as a standby signal of the counterpart device, and an input terminal is connected to an output terminal of the selection means and the second means. Is connected with the wait signal of the external device, the control of the redundant devices, characterized in that consists of means for generating an operation signal by multiplying a received signal logic circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920022290A 1992-11-25 1992-11-25 Redundancy Control Circuit KR940012944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920022290A KR940012944A (en) 1992-11-25 1992-11-25 Redundancy Control Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920022290A KR940012944A (en) 1992-11-25 1992-11-25 Redundancy Control Circuit

Publications (1)

Publication Number Publication Date
KR940012944A true KR940012944A (en) 1994-06-24

Family

ID=67211078

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920022290A KR940012944A (en) 1992-11-25 1992-11-25 Redundancy Control Circuit

Country Status (1)

Country Link
KR (1) KR940012944A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315710B1 (en) * 1999-06-18 2001-12-12 윤종용 Duplication controlling circuit of duplicated processor unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100315710B1 (en) * 1999-06-18 2001-12-12 윤종용 Duplication controlling circuit of duplicated processor unit

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