JPH04350730A - Duplexing circuit - Google Patents

Duplexing circuit

Info

Publication number
JPH04350730A
JPH04350730A JP3153898A JP15389891A JPH04350730A JP H04350730 A JPH04350730 A JP H04350730A JP 3153898 A JP3153898 A JP 3153898A JP 15389891 A JP15389891 A JP 15389891A JP H04350730 A JPH04350730 A JP H04350730A
Authority
JP
Japan
Prior art keywords
trouble
systems
occurrence
preventing
duplexing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3153898A
Other languages
Japanese (ja)
Inventor
Keiichi Tezuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3153898A priority Critical patent/JPH04350730A/en
Publication of JPH04350730A publication Critical patent/JPH04350730A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the reliability of a built-in system by preventing the double occurrence of trouble.
CONSTITUTION: In a duplexing circuit which is provided with dual systems and properly switches systems to perform trouble processing, a trouble detection flag is set and held at the time of detecting trouble in each system, and the holding state of the trouble detection flag of one system is checked when that of the other system is set by the occurrence of trouble in this system, and systems are switched only when trouble does not occur in one system, thereby preventing the double occurrence of trouble.
COPYRIGHT: (C)1992,JPO&Japio
JP3153898A 1991-05-28 1991-05-28 Duplexing circuit Pending JPH04350730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3153898A JPH04350730A (en) 1991-05-28 1991-05-28 Duplexing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3153898A JPH04350730A (en) 1991-05-28 1991-05-28 Duplexing circuit

Publications (1)

Publication Number Publication Date
JPH04350730A true JPH04350730A (en) 1992-12-04

Family

ID=15572523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3153898A Pending JPH04350730A (en) 1991-05-28 1991-05-28 Duplexing circuit

Country Status (1)

Country Link
JP (1) JPH04350730A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897750A (en) * 1994-09-22 1996-04-12 Nec Commun Syst Ltd Clock reception distribution system
JP2011013796A (en) * 2009-06-30 2011-01-20 Toshiba Corp Information processing apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897750A (en) * 1994-09-22 1996-04-12 Nec Commun Syst Ltd Clock reception distribution system
JP2011013796A (en) * 2009-06-30 2011-01-20 Toshiba Corp Information processing apparatus
US9170617B2 (en) 2009-06-30 2015-10-27 Kabushiki Kaisha Toshiba Information processing apparatus to selectively disable or throttle an external graphics controller

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