JPS57157657A - Receiving clock generating circuit - Google Patents

Receiving clock generating circuit

Info

Publication number
JPS57157657A
JPS57157657A JP56043428A JP4342881A JPS57157657A JP S57157657 A JPS57157657 A JP S57157657A JP 56043428 A JP56043428 A JP 56043428A JP 4342881 A JP4342881 A JP 4342881A JP S57157657 A JPS57157657 A JP S57157657A
Authority
JP
Japan
Prior art keywords
phase difference
clock signal
prescribed
generating
clock generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56043428A
Other languages
Japanese (ja)
Inventor
Masuo Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56043428A priority Critical patent/JPS57157657A/en
Publication of JPS57157657A publication Critical patent/JPS57157657A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make a postable radio apparatus small-sized and light, by changing and switching the timing for generating a clock signal, by a prescribed phase difference, in case when a phase shift has been detected. CONSTITUTION:A clock generating part 16 operates independently in the receiving side, and generates a clock signal for sampling a receiving digital signal, having prescribed pulse width. A phase difference detecting part 9 detects a phase shift by detecting the overlapping of the prescribed pulse width of the clock signal, and the conversion point of the receiving digital signal. In case when this phase difference detecting part 9 has detected a phase shift, the timing for generating the clock signal in the clock generating part 16 is changed and switched by a prescribed phase difference.
JP56043428A 1981-03-25 1981-03-25 Receiving clock generating circuit Pending JPS57157657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56043428A JPS57157657A (en) 1981-03-25 1981-03-25 Receiving clock generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56043428A JPS57157657A (en) 1981-03-25 1981-03-25 Receiving clock generating circuit

Publications (1)

Publication Number Publication Date
JPS57157657A true JPS57157657A (en) 1982-09-29

Family

ID=12663420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56043428A Pending JPS57157657A (en) 1981-03-25 1981-03-25 Receiving clock generating circuit

Country Status (1)

Country Link
JP (1) JPS57157657A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63173434A (en) * 1987-01-13 1988-07-18 Mitsubishi Electric Corp Bit phase synchronizing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63173434A (en) * 1987-01-13 1988-07-18 Mitsubishi Electric Corp Bit phase synchronizing circuit

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