JP2001186200A - Digital signal relay transmitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal relay transmitting device, capable of preventing decrease in transmission efficiency due to excessive preamble transmission by improving the number of received preamble losses. SOLUTION: This digital signal relay transmitting device used for a half- duplex transmission system is provided with a carrier sensing function 14, which detects the change point of a received signal and controls the transmission output, a transmission switching circuit 2 and a function 1, which generates transmission preamble signals during the period when a DPLL 13 establishes synchronization from the start signal of the transmission output, and performs reproduction compensation of lost preambles, until the DPLL performs synchronous establishment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal transmission repeater applied to a digital signal transmission system.

[0002]

2. Description of the Related Art In a conventional signal transmission system using a digital signal relay transmission device incorporating a DPLL for relay transmission of a digital signal, a preamble signal is added to the head of transmission data to establish DPLL synchronization. I have. The preamble signal is, for example, “101010”.
The transmission station forms the number of bits required for the DPLL of the digital signal relay transmission apparatus to establish synchronization as the number of transmission preambles by using the maximum number of relay multi-stage connections. Fig. 3 shows a configuration in which a digital signal repeater transmission device is connected to a conventional half-duplex transmission system, and data transmission is performed by a two-wire transmission line 110. Transmitting stations 111 to 1
13 and transmission line 1 between stations 111 and 112
10 shows an example of a digital signal relay transmission apparatus 114 installed in the digital signal transmission apparatus 10. The received data received at the port A (or B) of the digital signal relay transmission device 114 via the transmission line 110 is transmitted / transmitted to the transmission line 110 via the port B (or A). FIG. 4 is a functional block diagram of the digital signal repeater transmission apparatus shown in FIG. In the figure,
11 is a receiver for receiving and reproducing received data of received data.
Reference numeral 12 denotes a driver having a control input function of a transmission output of relay data. This driver 12 can transmit and output when the control input is at a high level. Reference numeral 13 denotes a DPLL circuit that extracts a synchronization establishment signal and a reception clock from received data. The establishment of synchronization by the DPLL circuit 13 is performed by preamble bit pattern matching or the like. 14 detects a change point of the received data and determines whether or not there is a change b
This is a bit carrier sense timer circuit. Reference numeral 15 denotes a reproduced data circuit which samples received data with a reception clock from the DPLL. An AND circuit 16 controls the output of the transmission data of the driver 12 based on the AND condition of the output signal of the carrier sense timer circuit 14 and the synchronization establishment signal. (Note that although not shown, the system is actually a bidirectional channel). FIG. 5 is a diagram showing a relay operation timing of the digital signal relay transmission device shown in FIG. Next, the operation will be described with reference to the drawings. Received data in a format as shown in FIG. 5A is input to the carrier sense timer circuit 14, the DPLL circuit 13, and the data reproduction circuit 15. The carrier sense timer circuit 14 detects a change point of the preamble signal and turns on. The DPLL circuit 13 starts synchronizing with the preamble signal, and extracts the synchronization establishing signal and the reception clock after M bits. In the reproduction data circuit 5, the reception data is sampled by the reception clock from the DPLL circuit 13, output, and input to the driver 12. During the period when the carrier sense timer circuit 14 and the synchronization establishment signal are ON, the control signal becomes a high level output as shown in FIG. 5B, and the reproduction data is transmitted from the driver 12 as shown in FIG. 5C. .

[0003]

However, in the above conventional example, as shown in FIG. 5, the preamble bit L1 is set to L3 until the synchronization is established by the DPLL.
When relay devices are connected in multiple stages, it is necessary for the transmitting station to add at least the number of connected multi-stages at the beginning of the transmission data in anticipation of the number of preambles to be lost, which reduces transmission efficiency. There was a problem. Therefore, the present invention reduces the number of preambles that are lost on the way due to synchronization establishment processing or the like, and can set the maximum number of preambles to be added to transmission data to be small, thereby preventing a reduction in transmission efficiency due to excessive preamble transmission. It is an object of the present invention to provide a digital signal transmission repeater.

[0004]

In order to achieve the above object, the present invention relates to a digital signal repeater transmission apparatus used in a half-duplex transmission system, which detects a change point of a received signal and controls a transmission output. It is characterized by having a sense function and a function of generating a transmission preamble signal during a period from the start signal of the transmission output to the establishment of the DPLL synchronization. According to this digital signal relay transmission apparatus, when the preamble of the received signal is detected by the carrier sense timer function, the reproduction preamble signal is transmitted and output by the transmission preamble generation function until the synchronization is established by the DPLL, and is output when the synchronization by the DPLL is established. Is switched and the reproduction reception data is transmitted and output.
The preamble signal lost by the synchronization establishment process by the LL can be compensated in the relay device by reproducing and adding the preamble signal from the preamble generation function.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a functional block diagram of a digital signal relay transmission apparatus according to an embodiment of the present invention. FIG. 2 is a diagram showing a relay operation timing of the digital signal relay transmission apparatus shown in FIG. In FIG. 1, FIG.
The difference from the conventional configuration shown in FIG. 1 is that the preamble generation circuit 1 that generates a preamble during the period from when the carrier sense timer circuit 14 is turned on to the time when the DPLL circuit 13 establishes synchronization, and the AND circuit 16 are deleted. The difference is that a transmission signal switching circuit 2 for switching the output of the reproduction data circuit 15 and the output of the preamble generation circuit 1 with the establishment signal output is added. The same components as those in FIG. 4 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the operation will be described with reference to the drawings. As shown in FIG. 1, received data is transmitted from a receiver 11 to a carrier sense timer circuit 14 and a DPLL circuit 13.
Is input to the reproduction data circuit 15. First, the carrier sense timer circuit 14 detects a change point of the head preamble signal of the received data as shown in FIG. 2A and turns on (determines that there is a carrier). The carrier sense timer circuit 14 includes a b-bit detection circuit for detecting a preamble and a timer function for starting after detecting the preamble and covering one frame of the received data as shown in FIG. ing. When the carrier sense timer circuit 14 is turned on, the preamble generation circuit 1 operates to reproduce the preamble, and is output to the driver 12 via the transmission switching circuit 2 (for example, a selector circuit). The preamble generating circuit 1 may use a general preamble signal generator. On the other hand, the DPLL circuit 13 starts pulling in the synchronization by the preamble of the received data as shown in FIG. 2A, and compares the phase with the generated clock divided by n to obtain M
After a bit, the synchronization is established as shown in FIG. 2B, the synchronization establishment signal and the reception clock are extracted, the synchronization establishment signal is sent to the transmission switching circuit 2 and the preamble generation circuit 1, and the reception clock is reproduced. The data is sent to the data circuit 15.
In the reproduction data circuit 15, the received data to be input is
The timing is adjusted by sampling with the reception clock extracted and phase-adjusted by the L circuit 13 and output as retransmission data. When the synchronization establishment signal from the DPLL circuit 13 is input to the preamble generation circuit 1, the preamble generation circuit 1 stops outputting the preamble signal, and when the synchronization establishment signal is input to the transmission switching circuit 2 as a selection signal, The transmission switching circuit 2 switches the reproduction data circuit 15
And outputs the reproduction transmission data from the driver 12 to the driver 12. Then, during the ON period of the carrier sense timer circuit 14 (during the timer period of one frame), the driver 12 outputs retransmission data following the reproduction preamble output, as shown in FIG. 2C. As described above, according to the present embodiment, carrier sense timer circuit 14, DPLL
The operations of the circuit 13 and the reproduction data circuit 15 are the same as those in the conventional example, but the carrier sense timer circuit 14 is turned on and the DP
During the period until the LL circuit 13 establishes synchronization, the preamble signal generation circuit 1 outputs a reproduced preamble, and as shown in FIG. 2 (c), compensates the preamble which has conventionally disappeared and becomes L3 up to L2. After that, the synchronization establishment signal turns ON
Then, since the transmission switching circuit 2 switches the output from the preamble transmission to the output of the retransmission data, a simple and low-cost relay transmission device capable of transmitting normal transmission data in which the preamble that is lost by the synchronization establishment process is reproduced and added is provided. Can be provided by configuration.

[0007]

As described above, according to the present invention,
A simple configuration is achieved by adding a switching function of reproducing and transmitting a preamble pattern during a period from a change point of a leading preamble of received data to the establishment of synchronization of the DPLL circuit and transmitting reproduction data from the point of synchronization of the DPLL circuit. As a result, the loss of the number of received preambles can be improved, and the transmission efficiency can be prevented from lowering due to excessive preamble transmission.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a digital signal relay transmission apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a timing of a relay operation of the digital signal relay transmission device shown in FIG. 1;

FIG. 3 is a diagram showing a configuration of a conventional half-duplex transmission system.

4 is a functional block diagram of the digital signal relay transmission device shown in FIG.

5 is a diagram showing a timing of a relay operation of the digital signal relay transmission device shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Preamble generating circuit 2 Transmission switching circuit 11 Receiver 12 Driver 13 DPLL circuit 14 Carrier sense timer circuit 15 Reproduction data circuit

Claims (1)

[Claims] 1. A digital signal repeater for use in a half-duplex transmission system, comprising: a carrier sense function for detecting a change point of a received signal to control a transmission output;
And a function for generating a transmission preamble signal during a period until synchronization is established.