JPH07231316A - Duplex communication equipment - Google Patents

Abstract

PURPOSE:To provide a duplex communication equipment which is suitable for phase locked loop (PLL) clock reproducing technique and can surely establish synchronism at high speed while reducing circuit scale. CONSTITUTION:A master communication equipment 101 transmits a bit synchronizing signal to a slave communication equipment, and while using that signal, the slave communication equipment establishes bit synchronism corresponding to the successively, the bit synchronizing signal is transmitted to the master communication equipment 101, and while using that signal the master communication equipment 101 establishes bit synchronism corresponding to a PLL 110. Then, a frame synchronizing signal is transmitted to the slave communication equipment, and while using that signal, the slave communication equipment establishes frame synchronism. Afterwards, the frame synchronizing signal is transmitted to the master communication equipment 101, and while using that signal, the master communication equipment 101 establishes the frame synchronism.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-way communication device which establishes bit synchronization and frame synchronization, converts parallel data into serial data and transmits the serial data.

[0002]

2. Description of the Related Art In recent years, due to the progress of IC technology, synchronous communication technology has been expanding its application range from large-scale applications typified by trunk lines to small-scale applications typified by LAN. Along with this, it is required to further improve the versatility of the synchronous communication device.

In such a synchronous communication device, when bit synchronization and frame synchronization are not established between the transmitter and the receiver after the power is turned on, it is necessary to establish the synchronization according to a certain procedure, and it is necessary to establish the synchronization for each system. The procedure for establishing synchronization that the transmitter and receiver should follow is defined in advance, but due to the request for generalization as described above, even for devices that control the procedure for establishing synchronization between these transmitters and receivers. , Various requests are mentioned.

First, in response to frequent power interruptions, after the power is turned on, bit synchronization is ensured at high speed and reliably.
It is required to establish frame synchronization and establish communication promptly.

In order to reduce the price, it is also important to share parts, and one type of transceiver is used to
It must be possible to construct a communication system in which the transmission clock frequency and frequency accuracy are different. A clock recovery technology using a phase-locked loop (hereinafter referred to as PLL) satisfies such requirements of flexibility, and is extremely important because it can be downsized, low cost, and power can be saved by using an IC.
There is a need for a synchronization establishment technique suitable for the clock recovery technique by LL.

Conventionally, there are two types of bidirectional communication devices: a device in which transmission / reception bit clocks are independent of each other and a device in which transmission / reception bit clocks are synchronized with each other. If the transmission and reception clocks are not synchronized with each other, various additional devices are required. For example, in order to loop back the received data, an additional device that adds stuff bits is required, and operates with a single clock. A special additional circuit is required when interfacing with a device such as a mobile terminal. On the other hand,
A communication device that uses a bit clock synchronized with each other for transmission and reception does not need these additional circuits, and the circuit of the communication device can be simplified. Therefore, a communication device technology using bit clocks synchronized with each other for transmission and reception is important, and a synchronization establishment technology adapted to this technology is required.

On the other hand, as a system in which a procedure for establishing synchronization from a state where bit synchronization has not been established conventionally has been implemented, 1) an independent procedure control dedicated line is provided separately from the data transmission line,
The system that controls the procedure between the transmitter and the receiver.

2) No control signal is exchanged between the transmitter and the receiver, the transmitting side transmits a signal including a bit synchronizing signal and a frame synchronizing signal for a predetermined period, and the receiving side synchronizes within a period during which these are received. system.

3) A system for transmitting control information by mutually transmitting a predetermined unique bit pattern in a bidirectional transmission device. And so on.

[0010]

However, when considering the small-scale application as described above, a dedicated control line for control is provided in addition to the data transmission line as in 1) of the above example. Is unacceptable in terms of cost and volume.

When clock extraction by the PLL is used on the receiver side, depending on the state of the PLL on the receiver side, sometimes a long synchronization pull-in time may occur. Therefore, in order to ensure reliable synchronization, especially in a method in which control information is not exchanged, such as 2) in the above example, it is necessary to provide a considerably long synchronization period in advance. Will increase.

In the example of 3) in which control information is exchanged by a bit pattern, there are problems such as incorrect control information identification due to bit synchronization deviation and pseudo synchronization of frame synchronization before and after establishment of bit synchronization. For,
Strict error correction and a long protection period are required, which causes an increase in circuit scale and an increase in the time required to establish communication. Further, since a large transmission capacity is required for strict error correction, the amount of data that can be transmitted / received during transmission of control information is small, and the transmission capacity is wasted.

Further, in a communication device which uses bit clocks synchronized with each other for transmission and reception, unless proper control is performed, an erroneous received signal is generated, and therefore a bit clock having an erroneous phase or frequency is used. There is a possibility that a bit synchronization signal or a frame synchronization signal may be transmitted, and such a situation must be avoided to establish synchronization. From these viewpoints, in the synchronous communication device,
There is a demand for a high-speed, small-scale, and reliable circuit for PLL clock reproduction and means for establishing synchronization suitable for a communication device using a clock synchronized for transmission and reception.

In consideration of such problems of the conventional bidirectional communication device, the present invention provides a bidirectional communication device which has a small circuit size, is suitable for a PLL clock recovery technique, and can establish synchronization at high speed and reliably. That is the purpose.

[0015]

SUMMARY OF THE INVENTION The invention of claim 1 is a first communication having a first phase-locked loop for establishing bit synchronization and a first frame synchronization circuit for establishing frame synchronization. And a second communicator having a second phase-locked loop for establishing bit synchronization and a second frame synchronization circuit for establishing frame synchronization. The first communication device establishes bit synchronization by the first phase-locked loop based on the signal obtained by multiplexing the bit synchronization signal received from the second communication device, and the second communication device determines the first communication. After establishing bit synchronization by the second phase-locked loop based on the signal obtained by multiplexing the bit synchronization signal received from the device, and after the bit synchronization is established by both the first communication device and the second communication device. , The first communication device is On the basis of a signal frame synchronizing signal received is multiplexed from communication apparatus, the first frame synchronization circuit to establish the frame synchronization, the second communication device is
A two-way communication device that establishes frame synchronization by a second frame synchronization circuit based on a signal obtained by multiplexing a frame synchronization signal received from a first communication device.

According to the second aspect of the present invention, a first communication device having a first phase locked loop for establishing bit synchronization and a first frame synchronization circuit for establishing frame synchronization, and bit synchronization are provided. A two-way communication device comprising a second phase-locked loop for establishing and a second communication device having a second frame synchronization circuit for establishing frame synchronization, the first communication device comprising: When the signal A in which the bit synchronization signal is multiplexed is transmitted to the second communication device, and the second communication device establishes the bit synchronization by the second phase-locked loop based on the signal A, the bit synchronization is performed. When a signal B in which the signals are multiplexed is transmitted to the first communication device, and the first communication device establishes bit synchronization by the first phase-locked loop based on the signal B, the frame synchronization signal is The multiplexed signal C The second communication device transmits the signal D to which the frame synchronization signal is multiplexed to the first communication device when the second frame synchronization circuit establishes the frame synchronization based on the signal C. And the first communicator
A two-way communication device that establishes synchronization between the first communication device and the second communication device by establishing frame synchronization by the first frame synchronization circuit based on the signal D.

[0017]

According to the present invention, the first communication device establishes the bit synchronization by the first phase-locked loop based on the received signal in which the bit synchronization signal is multiplexed, and the second communication device operates. After establishing the bit synchronization by the second phase-locked loop, the first communication device establishes the frame synchronization by the first frame synchronization circuit based on the received signal in which the frame synchronization signal is multiplexed, The second communication device establishes frame synchronization by the second frame synchronization circuit.

According to the present invention, the first communication device transmits the signal A in which the bit synchronization signal is multiplexed to the second communication device,
Based on the signal A, the second communication device establishes bit synchronization by the second phase-locked loop, and then transmits the signal B multiplexed with the bit synchronization signal to the first communication device, Based on the signal B, the communication device establishes bit synchronization by the first phase-locked loop and then transmits a signal C in which a frame synchronization signal is multiplexed to the second communication device, and the second communication device , The frame synchronization is established by the second frame synchronization circuit based on the signal C, and then the signal D multiplexed with the frame synchronization signal is transmitted to the first communication device, and the first communication device transmits the signal. Based on D, the frame synchronization is established by the first frame synchronization circuit, and the first communication device and the second communication device are connected.
Establish synchronization between the communicators.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. (Embodiment 1) FIG. 1 and FIG. 2 are block diagrams of a bidirectional communication apparatus according to a first embodiment of the present invention (of a communication system for performing a synchronization establishing procedure according to claim 1 of the claims). An example is shown). That is, the two-way communication device is
The parent communication device 101, which is the first communication device shown in FIG. 1, and FIG.
The slave communication device 102, which is the second communication device shown in FIG. 3, is connected to the master communication device 101 and the slave communication device 102 by transmission lines 111 and 112.

The master communicator 101 is a parallel-serial converter 103 for converting 4-bit parallel data (in this embodiment, transmission data composes one frame of 4 bits) into serial data, and a multiplexer 113 for switching data to be transmitted. A controller 115 for controlling the multiplexer 113 according to the synchronization state, a serial / parallel converter 106 for converting the received serial data into parallel data, a PLL (phase locked loop) 110 for establishing bit synchronization, a frame synchronization pattern, and It is configured by a 4-bit comparator 119 or the like that compares the received data. In addition, the slave communication device 102, like the master communication device 101, has a parallel-serial converter 104 and a multiplexer 1.
14, controller 116, serial-parallel converter 1
05, PLL 109, 4-bit comparator 120 and the like. A part of the serial / parallel converter 106 and the 4-bit comparator 119 and the like constitute a first frame synchronization circuit, and a part of the serial / parallel converter 105 and the 4-bit comparator 120 and the like are a second frame synchronization circuit. Are configured.

The multiplexer 113 of the master communication device 101
Outputs data 121, bit patterns 125, 12
6, the multiplexer 114 of the slave communication device 102 switches the output to one of the data 122 and the bit patterns 125, 126, 127.

In the master communication device 101, the controller 115 controls the multiplexer 113 according to the synchronization state, and the 4-bit parallel data 121 and the bit pattern 12 are used.
5 or 126 is selected and input to the parallel-serial converter 103, which is converted into a serial bit string in accordance with the clock from the clock generator 107, and the transmission line 1
11 is sent.

Similarly, the slave communication device 102 is the controller 1
16 controls the multiplexer 114, and the 4-bit parallel data 122 and the bit patterns 122, 12
5, 126, 127 is selected and input to the parallel-to-serial converter 104, and this is input to the clock generator 10.
It is converted into a serial bit string according to the clock from 8 and sent to the transmission line 112.

Next, the operation of the bidirectional communication device of the first embodiment will be described.

In the following, both parent and child communication devices 101 and 102 will be described.
However, in the initial state after the power is turned on, it is assumed that the PLLs 110 and 109 for reproducing the bit synchronization signals have not established the bit synchronization with respect to the received signal, and similarly, that the frame synchronization has not been established. The procedure for sequentially performing frame synchronization will be described.

First, in the initial state, the slave communication device 102 is set to 0.
A continuous idling pattern 127 is selected and transmitted. On the other hand, the parent communication device 101 transmits the [0101] pattern 125. In this way, at the stage of performing bit synchronization, a signal such as the [0101] pattern 125, which particularly contains many bit synchronization signals and does not include frame information, is transmitted.

Next, the slave communicator 102 receives the [0101] pattern, and the PLL 109 for the received signal.
To establish bit synchronization. The bit synchronization pull-in time by the PLL 109 generally becomes shorter as the received signal contains more bit synchronization signals, but since this [0101] pattern consists of only the bit synchronization signals, the PLL.
There is an advantage that the pull-in time by 109 can be minimized, and in particular, it contributes to shortening the bit synchronization establishment time on the receiver side. In the slave communication device 102, the controller 116
Monitors the PLL 109, and upon detecting the establishment of bit synchronization, controls the multiplexer 114 to start transmitting the [0101] pattern 125. Then, the parent communication device 10
1 receives this signal, and the PLL 110 extracts the bit synchronization signal to establish the bit synchronization. At this stage, bit synchronization between both communication devices 101 and 102 is established.

At this time, the serial / parallel converter 106 of the master communication device 101 serial-parallel converts the transmission path signal received from the transmission path 112 according to the reproduction clock from the PLL 110 to obtain reception data 123. On the other hand, the serial / parallel converter 105 of the slave communication device 102 is a PLL
The transmission line signal received from the transmission line 111 is serial-parallel converted into reception data 124 according to the reproduction clock from 109.

Next, the 4-bit comparator 1 of the master communication device 101
19 compares the received parallel data 123 with the frame synchronization pattern 126, and generates a hunt signal 130 if they do not match. Similarly, the 4-bit comparator 120 of the slave communication device 102 compares the received parallel data 124 with the frame synchronization pattern 126, and generates a hunt signal 131 when they do not match.

Here, since the frame synchronization signal cannot be received until the bit synchronization is established, the controller 115 closes the gate 128 and the hunt signal 13 in the parent communication device 101 to avoid erroneous frame synchronization establishment.
0 is ignored, and the controller 116 in the slave communication device 102.
Closes gate 129 and hunt signal 131 is ignored. Both the communication devices 101 and 102 confirm the establishment of bit synchronization to the received transmission path signal and at the same time, these gates 12
Although 8 and 129 are opened to enter the hunting mode, immediately after this, only the clock signal is received, and the hunting is repeated and waits until the reception of the signal having the frame synchronization information. As described above, in the present embodiment, when the hunting mode is entered, bit synchronization has already been established, and the reception signal remains until the transmission side multiplexes the frame synchronization signal as the control signal and transmits the data. Since the frame synchronization signal is not included at all, the probability of accidentally performing frame synchronization is extremely low, and as a result, the number of stages of frame synchronization backward protection can be reduced and the synchronization process can be speeded up.

Next, the controller 11 of the master communication device 101
5 detects the establishment of bit synchronization in the PLL 110,
The [0001] pattern 126 is selected as the data including the frame synchronization signal and the bit synchronization signal, converted into a serial bit string, and transmission is started. This [000
1] The slave communication device 102, which has received the pattern, performs a hunting operation using this to establish frame synchronization. When the frame synchronization is established by the hunting, the rear protection counter 118 notifies the controller 116 of the establishment of the synchronization after a predetermined time elapses after the hunting signal is not generated. Then, the controller 116 sets [000
1] Select the pattern 126 to start transmission.

Finally, the parent communication device 101 and the child communication device 102
The frame synchronization is established in the same manner as described above, and the backward protection counter 11
When 7 notifies the controller 115 of the establishment of synchronization, it is determined that the two-way communication device has established synchronization, and the master communication device 10
In 1, the transmission data 121 is selected and transmission is started,
The reception data 124 is received by the slave communication device 102. Alternatively, the slave communication device 102 selects the transmission data 122 to start transmission, and the master communication device 101 receives the reception data 123.

As described above, the procedure implemented in the present invention is fast and highly reliable, and the device for performing this is a dedicated control line in the conventional example and an error correction circuit for error protection. It can be configured with a simple circuit without requiring the above. (Embodiment 2) FIGS. 3 and 4 are block diagrams of a two-way communication apparatus according to a second embodiment of the present invention (showing an example of a communication system for performing the synchronization establishing procedure according to claim 3). Exist). That is, the two-way communication device is the first communication device shown in FIG.
4 and a slave communication device 202 which is a second communication device shown in FIG. 4, and the master communication device 201 and the slave communication device 202 are connected by transmission lines 228 and 229.
Connected by.

The master communication device 201 is a parallel-to-serial converter 203 for converting 4-bit parallel data (in this embodiment, transmission data constitutes one frame of 4 bits) into serial data, and the converted serial data. C
CMI encoder 207 for MI encoding, CMI decoder 210 for decoding received data, serial / parallel converter 205 for converting the decoded serial data into parallel data, and PLL 2 for establishing bit synchronization.
13, a bit sync detector 217 for detecting bit sync,
The frame signal generator 214, which generates a frame signal, is configured. Further, the slave communication device 202 includes a parallel-serial converter 204 that converts 4-bit parallel data into serial data, a CMI encoder 208 that performs CMI encoding of the converted serial data, and a CMI decoding that decodes the received data. 209, serial / parallel converter 206 for converting the decoded serial data into parallel data, and PLL for establishing bit synchronization
212, bit sync detector 218 for detecting bit sync
Etc. The CMI decoder 210 described above
Of the CMI decoder 209 constitutes part of the first frame synchronization circuit, and part of the CMI decoder 209 constitutes part of the second frame synchronization circuit.

In the master communication device 201, the clock generator 211 generates the reference clock 230, and the frame signal generator 214 generates the frame signal 236 once every four clocks. The parallel-serial converter 203 reads the input signal 224, which is 4-bit parallel data, according to the frame signal 236, and outputs 1 according to the reference clock 230.
Convert bit by bit into a serial bit string. The serial bit string is input to the CMI encoder 207 through the gate 219, becomes a CMI code transmission line signal, and is transmitted to the transmission line 228. In addition, the gate 22 is provided to the CMI encoder 207.
When the frame synchronization signal 236 is input through 1,
According to the frame synchronization signal 236, the CMI encoder 207 has a one-to-four-bit CRV (CMI coding rule violation /
Coding Rule Violation) is multiplexed on the data.

In the slave communication device 202, the PLL 212 extracts the bit synchronization signal component from the transmission path signal received from the master communication device 201 and generates the reproduction clock 231. Further, the CMI decoder 209 identifies the CRV in the transmission path signal received from the parent communication device 201, and accordingly generates the frame synchronization signal 233 once every four clocks. When the gate 222 is opened and the distribution of the frame signal 233 is permitted, the parallel-serial converter 204 follows the input signal 225, which is 4-bit parallel data, accordingly.
Is read and converted into a serial bit string bit by bit according to the reproduction clock 231. The serial bit string is input to the CMI encoder 208 through the gate 220 and C
It becomes a transmission path signal of MI code and is sent to the transmission path 229 through the gate 223. When the gate 222 is opened and the distribution of the frame signal 233 is permitted, CM
The I encoder 208 follows the frame sync signal 233
CRV of 1 bit is multiplexed with data of 4 bits.

Next, the operation of the bidirectional communication device of the second embodiment will be described.

In the following, both the parent and child communication devices 201, 202
However, in the initial state after the power is turned on, it is assumed that the PLLs 213 and 212 for reproducing the bit synchronization signals have not established the bit synchronization with respect to the received signal and the frame synchronization has not been established. Describe the steps that take place.

First, the PLL of the slave communication device 202 in the initial state
212 does not establish bit synchronization with the received signal from the transmission path 228. The bit synchronization detector 218 is PL
When L212 is monitored and bit synchronization is not established, the signal to the transmission line 229 is fixed to 0 by the gate 223 so that it is not transmitted. The backward protection counter 216 in the initial state closes the gate 220 to fix the input to the CMI encoder 208 to 0, and the gate 222 prohibits the distribution of the reproduction frame synchronization signal 233.

In the CMI decoder 210 of the parent communication device 201 in the initial state, only 0 is input from the transmission line 229, and no bit synchronization signal is input, so that bit synchronization is not yet established. The bit sync detector 217 is a PLL
213 is monitored, and when the bit synchronization is not established, the gate 221 prohibits multiplexing the frame signal 236 with the data. The backward protection counter 215 in the initial state fixes the input to the CMI encoder 207 to 0 by the gate 219. Therefore, the CMI encoder 207 transmits the [01010101] pattern obtained by CMI-encoding the [0000] pattern to the transmission line 228.

Next, the slave communication device 202 receives this [0101
0101] receives the pattern and responds to the PLL 21
2 establishes bit synchronization. Since this pattern is a perfect clock, the bit synchronization establishment time can be shortened as in the case of the first embodiment. In this way, when the bit synchronization pull-in by the PLL is performed, C which deteriorates the bit synchronization pull-in characteristic
Since it is guaranteed that the RVs are not multiplexed, there is an advantage that a good pull-in characteristic can be obtained. PLL
When 212 establishes bit sync, bit sync detector 2
18 releases gate 223, allowing signal transmission. At this time, since the gate 220 is still closed and only 0 is input to the CMI encoder 208, the CMI encoder 2
In accordance with the reproduction clock 231, 08 starts transmission of the [01010101] pattern obtained by CMI-coding the [0000] pattern to the transmission path 229.

Then, the master communicator 201 receives this [0
1010101] pattern is received and PL is received
Bit synchronization is established at L213. Even in the parent communication device 201, as with the child communication device 202, good pull-in characteristics are guaranteed with respect to bit synchronization. When the PLL 213 establishes bit synchronization, the bit synchronization detector 217 causes the gate 2
21 is opened, and the multiplexing of the frame signal 236 is started.
In this embodiment, if CRV is multiplexed on the first bit of data, the CMI-coded pattern transmitted at this time is [1001010101].

Next, in the slave communication device 202, the CMI decoder 209 receives this transmission path signal, identifies the CRV, and reproduces it as the frame signal 233. The backward protection counter 216 detects this frame signal 233, and after a predetermined backward protection period, opens the gate 222 to permit the distribution of the frame signal 233, and at the same time, the CMI encoder 20.
Allow bit string input to 8. In this way, until the bit synchronization is established, the operation related to the frame synchronization is not performed, and the transmission line signal to be received is the frame synchronization signal until the transmitting side multiplexes the frame synchronization signal as data as the control signal and transmits it. Is not included at all, the probability of erroneous frame synchronization is extremely low, and as a result, the number of frame synchronization backward protection steps can be reduced and the synchronization process can be speeded up.

When the distribution of the frame signal 233 is permitted, the serial / parallel converter 206 and the parallel / serial converter 204 start operating according to the frame signal 233.

When the parallel-serial converter 204 starts its operation, the transmission signal 225 is converted into a serial bit string, input to the CMI encoder 208 through the gate 220, and CMI encoded by the CMI encoder 208.
In addition, CR is performed once every 4 bits according to the frame signal 233.
The V signal is multiplexed, and the transmission line 229 is transmitted through the gate 223.
Sent to.

Next, in the parent communication device 201, the CMI decoder 210 receives this transmission path signal, identifies the CRV, and reproduces it as the frame signal 234. The serial-to-parallel converter 205 reads the serial bit string according to the reproduction clock 232, and according to the frame signal 234, 4
The received data 227 converted into bit parallel is sent out. At this point, the transmission data 225 on the slave communication device 202 side
Can be received as reception data 227 on the parent communication device side, and communication is established from the child communication device 202 to the parent communication device 201.

On the other hand, when the backward protection counter 215 detects the frame signal 234, the gate 219 is opened after a predetermined backward protection period to open the parallel-serial converter 2.
The input of the serial bit string from 03 to the CMI encoder 207 is permitted, and the transmission of the transmission data 224 to the transmission line 228 is thereby started.

Then, the CMI decoder 209 of the slave communication device 202 receives this transmission path signal, the serial-parallel converter 206 reads the serial bit string in accordance with the reproduction clock 231, and makes it 4-bit parallel in accordance with the frame signal 233. The converted reception data 226 is sent out. At this point, the transmission data 224 on the master communication device 201 side can be received as the reception data 226 on the slave communication device 202 side, communication is established from the master communication device 201 to the slave communication device 202, and bidirectional data communication is started. To be done.

As described above, the procedure carried out by the present invention is fast and highly reliable, and the device for performing this has a dedicated control line as in the conventional example and an error correction for error protection. No circuit required. In addition, bit synchronization by the CMI code, which can be originally composed of a relatively simple circuit, and CRV
A communication device having a synchronization establishment control function of the present invention can be realized by simply adding a backward protection circuit having a simple function, a bit synchronization detector, and a gate to a communication device that performs frame synchronization according to the above, and transmission capacity is wasted. It produces an excellent effect such as not causing

As described above, as the first step, bit synchronization is established in a loop-like order starting from the master communication device. In this way, each communication device first establishes bit synchronization with respect to the received signal, and starts clock transmission after the establishment, so when the side receiving the transmission path signal detects the clock component in the signal, It is assured that the device on the side of transmitting the transmission path signal is operating normally, and the bit synchronization pull-in by the PLL can be immediately started without the fear of false pull-in.

As the second step, frame synchronization is established according to the loop-shaped control sequence starting from the master communication device. In this way, the periods for obtaining the frame synchronization and the bit synchronization are separated, and the frame synchronization pull-in can be started immediately without the fear of false pull-in.

When the synchronization is established, the presence or absence of the bit synchronization signal or the frame synchronization signal is a control signal indicating the bit synchronization establishment state or the frame synchronization establishment state of the transmitter communication device. There is an advantage that the transmission capacity is not wasted due to the multiplexing of. Further, at the stage where it is not appropriate for the receiving side to establish synchronization, the bit synchronization signal or the frame synchronization signal itself is not transmitted, so there is little possibility of erroneous synchronization pull-in. Furthermore, in each stage, a control signal is transmitted as soon as the required synchronization is established, and the operation for obtaining the next synchronization is started, which is a high-speed procedure. Moreover, the circuit can be very simple and the circuit scale can be reduced.

Further, in the second embodiment, the property of CMI coding that a strong bit synchronization signal is multiplexed no matter what data is coded, the data coding itself according to the CMI coding rule is bit-synchronized. It is used as a signal multiplexing means. Further, this is used as a frame synchronization signal by utilizing the advantage that the CRV can be multiplexed in the data string regardless of the data content. By these methods, it is possible to prevent the waste of the transmission capacity due to the multiplexing of the bit synchronization signal and the frame synchronization signal, and it is possible to downsize the circuit.

On the other hand, the means for multiplexing the CRV in the CMI coded bit string has the drawback of disturbing the phase of the bit synchronization signal. CR when pulling in PLL bit synchronization
When V is multiplexed, it has an effect of deteriorating the pull-in characteristic, so that an additional device or the like has been conventionally used as a countermeasure against this. As an example of such a device, Japanese Patent Publication No. 02-031
There are 536 mag. On the other hand, according to the present invention, it is ensured that CRVs are not multiplexed at the time of pulling in the clock, so that there is an advantage that a good pull-in characteristic can be obtained without requiring such an additional device. The multiplexing of the bit synchronization signal by CMI coding and the use of CRV as the frame synchronization signal in this way is particularly suitable for the configuration of the present invention.

Further, the slave communication device uses a clock synchronized for transmission and reception. Therefore, in the slave communication device, the circuit for generating the bit synchronization signal and the frame synchronization signal can be simplified, the timing of the interface with the outside is unified, and various additional circuits are not required. Further, according to the procedure of the present invention, even when such a communication device is used as a slave communication device, a bit synchronization signal or a frame synchronization signal is transmitted from the slave communication device unless bit synchronization and frame synchronization are respectively established. Therefore, synchronization can be reliably established without sending an erroneous signal. In addition, since the procedure for establishing synchronization is the same regardless of whether the slave communicator of which the transmission / reception bit clocks are synchronized or the slave communicator of the asynchronous format, the communication using the same master communicator is performed. In the system, you can select and use any type of slave communication device, and it is easy to configure a slave communication device that can support both types with one model. , Flexibility is increased and equipment can be shared.

In the first embodiment, the master communication device 1
The bit synchronization signal and the frame synchronization signal to be transmitted to 01 are generated in the slave communication device 102, but instead of this, the bit synchronization signal and the frame synchronization reproduced from the transmission path signal received from the master communication device 101. The signal may be used again for the bit synchronization signal and the frame synchronization signal transmitted to the master communication device 101.

Further, in the above-mentioned embodiment, one frame is composed of 4 bits of transmission data, but the number of bits composing one frame is not limited to this.

[0058]

As is apparent from the above description, the present invention has the advantages that the circuit scale is small, it is compatible with the PLL clock recovery technology, and that synchronization can be reliably established at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first communication device in a bidirectional communication device according to a first exemplary embodiment of the present invention.

FIG. 2 is a second part of the two-way communication device of the first embodiment.
3 is a block diagram showing the communication device of FIG.

FIG. 3 is a block diagram showing a first communication device in a two-way communication device according to a second embodiment of the present invention.

FIG. 4 is a second part of the two-way communication device of the second embodiment.
3 is a block diagram showing the communication device of FIG.

[Explanation of symbols]

101, 201 Parent communication device 102, 202 Slave communication device 103, 104, 203, 204 Parallel / serial converter 105, 106, 205, 206 Serial / parallel converter 107, 108, 211 Clock generator 109, 110, 212, 213 PLL 113, 114 Multiplexer 115, 116 Controller 117, 118, 215, 216 Backward protection counter 119, 120 4 bit comparator 207, 208 CMI encoder 209, 210 CMI decoder 214 Frame signal generator 217, 218 bit sync detection vessel

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04L 29/08

Claims (4)

[Claims] 1. A first communication device having a first phase-locked loop for establishing bit synchronization and a first frame synchronization circuit for establishing frame synchronization, and a second communication device for establishing bit synchronization. Second phase-locked loop for establishing a phase-locked loop and frame synchronization of the second
And a first communication device based on a signal multiplexed with a bit synchronization signal received from the second communication device. A bit synchronization is established by a loop, and the second
The second communication device establishes bit synchronization by the second phase-locked loop based on the signal obtained by multiplexing the bit synchronization signal received from the first communication device, and the first communication device and the second communication device. After the bit synchronization is established in both of the first communication device and the second communication device, the first communication device is configured to detect the first frame synchronization circuit based on a signal obtained by multiplexing the frame synchronization signal received from the second communication device. Frame synchronization is established by the second communication device, and the second communication device establishes frame synchronization by the second frame synchronization circuit based on a signal in which the frame synchronization signal received from the first communication device is multiplexed. Two-way communication device characterized by. 2. A first communication device having a first phase-locked loop for establishing bit synchronization and a first frame synchronization circuit for establishing frame synchronization, and a second communication device for establishing bit synchronization. Second phase-locked loop for establishing a phase-locked loop and frame synchronization of the second
And a second communication device, wherein the first communication device transmits a signal A in which a bit synchronization signal is multiplexed to the second communication device, , Based on the signal A, the second
When bit synchronization is established by the phase locked loop of
A signal B in which a bit synchronization signal is multiplexed is transmitted to the first communication device, and the first communication device, based on the signal B, transmits the signal B to the first communication device.
When bit synchronization is established by the phase locked loop of
A signal C in which a frame synchronization signal is multiplexed is transmitted to the second communication device, and the second communication device, based on the signal C, transmits the second signal.
When frame synchronization is established by the frame synchronization circuit of, the signal D in which a frame synchronization signal is multiplexed is transmitted to the first communication device, and the first communication device is configured to transmit the signal D based on the signal D.
A two-way communication device, characterized in that frame synchronization is established by the frame synchronization circuit. 3. The bit synchronization signal transmitted from the second communication device to the first communication device is a signal reproduced from a signal obtained by multiplexing the bit synchronization signal transmitted by the first communication device, Further, the frame synchronization signal transmitted from the second communication device to the first communication device is a signal reproduced from a signal obtained by multiplexing the frame synchronization signal transmitted by the first communication device. The bidirectional communication device according to claim 1 or 2. 4. The two-way communication apparatus according to claim 1, 2 or 3, wherein the bit synchronization signal multiplexing means is CMI coding and the frame synchronization signal multiplexing means is a CMI coding rule violation. .