JPS6388943A - Demodulator control system - Google Patents

Abstract

PURPOSE:To quickly perform the synchronizing establishment of a carrier reproducing circuit by matching the receiving channel of a non-operated demodulator to a control channel frequency beforehand and holding a control voltage at the holding capacitor of a reproducing part. CONSTITUTION:A synthesizer 22 of a demodulator 3 during the non-operation is controlled to the same channel as the receiving channel of a demodulator 2 for a control line by the control of a CSC circuit 4. In this condition, when a receiving channel is designated to the demodulator 3 from a control station, the CSC circuit 4 turns off a holding switch 213 and holds a preceding VCO control voltage at a holding capacitor 214. Thereafter, the synthesizer 22 synchronizes to the designating channel outputted from the CSC circuit 4. Then, the CSC circuit 4 turns on the switch 213, a VCO 212 is controlled by the output of a loop filter 211 and a carrier reproducing device 23 executes the usual carrier reproducing action. Thus, the synchronizing time of the demodulator 3 can be made smaller.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulator control system, and more particularly to a common line signaling communication system having a control line demodulator connected to a control station and other demodulators. This invention relates to a demodulator control method in the present invention.

BACKGROUND OF THE INVENTION In a demodulator control method in such a communication system, the receiving channel of another demodulator that is not in operation is designated by an instruction from a control station via a demodulator for a control line connected to the control station. It has become. In this case, as a method to synchronize the frequency of the carrier regeneration circuit of the demodulator that is not in operation, the conventional method is to sweep control the generation frequency (or synchronization frequency) of this carrier regeneration circuit to synchronize the frequency of the designated reception channel. This method detects the

In general, in a satellite communication system, the frequency fluctuation of the satellite repeater is around ±35 to 112, but the frequency offset at which the JU adjuster can reliably synchronize is about 1750 within the symbol rate, which is the signal transmission speed. Therefore, for example, on a line with a symbol rate of 641 BAND, it is impossible for the demodulator to reliably perform synchronization. Therefore, as described above, a method of sweeping the oscillation frequency (or synchronization frequency) is used to establish synchronization.

In synchronization establishment by such a frequency sweep, before)! lS
In the case of a communication system with a signal transmission speed based on a symbol rate, a time of about 2 to 3 seconds is required, and therefore, there is a drawback that prompt line connection control is difficult.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and its purpose is to provide a demodulator that can quickly establish synchronization of a carrier regeneration circuit of a demodulator. The objective is to provide a device control method.

Structure of the Invention According to the present invention, there is provided a demodulator control method in a communication system having a control line demodulator connected to a control station and other demodulators, which The reception channel of the demodulator is specified in advance as the channel of the control line demodulator, and when the operating channel is specified for the demodulator that is not in operation, the synchronization frequency of the carrier recovery circuit of this demodulator is The demodulator control method is characterized in that the carrier regeneration circuit is controlled to be held at the frequency immediately before the channel is specified, and after setting the frequency synthesizer of the demodulator, the holding state of the synchronized frequency of the carrier regeneration circuit is released. can get.

1-1 Below, embodiments of the present invention will be described in detail with reference to the drawings.

The figure is a block diagram of an embodiment of the present invention, in which a power divider 1
The distributed received signals are input to each of demodulators 2 and 3. The demodulator 2 is connected to a control station (not shown) to form a control line, and the demodulator 3 is a special demodulator, and reception channel designation control is performed via the demodulator 2 according to instructions from the control station. be exposed. The demodulated output of the demodulator 2 is sent to a control circuit, C3C (Common Channel Signa).
ling Control: common line signal control) circuit 4
Control signals 101 and 102, etc., which are input to and control the demodulator 3 are generated.

The input signal of the demodulator 2 is frequency-mixed with the signal of the frequency synthesizer 12 by the frequency converter 11, frequency-converted, and supplied to the next-stage detector. This detector uses a synchronous detection method, and the carrier reproduced by the carrier regenerator 13 is multiplied by O in multipliers 14 and 15 and detected. This carrier regenerator 13 is a so-called Kostas (CO8TA).
S) type carrier extraction method is adopted, and the multiplier 14
A phase difference detector 110 that detects the phase difference between both outputs of 15 degrees.
, a loop filter 111 for noise compression, and a VCO whose oscillation frequency changes depending on the output of this loop filter.
voltage controlled oscillator) 112.

The output of this VCO 112 becomes the single power of the multiplier 15 and also becomes the single power of the n multiplier 14 via the 7r/2 phase shifter 16. The double product output of the multipliers 14 and 15 is the waveform shaper 1
At step 7.18, the signal is shaped based on the recovered clock by the clock regenerator 19 and introduced into the C8C circuit 4.

The demodulator 3 has substantially the same configuration as the demodulator 2, and the input signal is mixed with the signal from the frequency synthesizer 22 in the frequency converter 21, frequency-converted, and input to the synchronous detector.

In this synchronous detector, the carrier reproduced by the carrier regenerator 23 is multiplied by the multipliers 24 and 25 and detected. The carrier regenerator includes a phase difference detector 210, a loop filter 211, a VCO 212, and a hold switch 21 that turns on and off the output of the loop filter 211.
3, and a hold capacitor 214 that holds the output of the loop filter 211. This ■CO2
The output of 12 becomes the single power of the multiplier 25, and π/2
The multiplier 24 is operated by one person via the phase shifter 26 . The double product outputs of the multipliers 24 and 25 are shaped by waveform shapers 27 and 28 based on the clock reproduced by the clock regenerator 29, and are supplied to a communication unit (not shown).

In this configuration, it is assumed that the demodulator 2 connected to the control station and formed by the control line is already in a synchronized state,
The other demodulators 3 are not in operation. The C8C circuit 4 learns that the demodulator 3 is not in operation because the designated data is not derived from the reception channel designation signal line 101, and instructs the demodulator 3 to have the same reception channel as the demodulator 2. The channel is designated via the signal line 101. As a result, the frequency synthesizer 22 and the carrier regenerator 23 operate and become synchronized so as to receive the same reception channel as the reception channel of the demodulator 2. At this time, a control signal for turning on the hold switch 213 is sent to the signal line 102, and the carrier regenerator is in a synchronization established state.

In this state, when the control station designates a reception channel to the demodulator 3 via the demodulator 2, the C8C circuit 4 sends a control signal to the signal line 102 to turn off the hold switch 213. Therefore, hold capacitor 2
14, the immediately previous VCO controlled voltage t11 is held. Thereafter, the C8C circuit 4 sends a control signal instructing the designated channel to the signal line 101, and in response, the synthesizer 22 performs a synchronous operation to generate a frequency corresponding to the designated channel. When this synthesizer 22 establishes synchronization, the C8C circuit 4 detects this and sends an ON control signal of the hold switch 213 to the signal line 1.
Send to 02. In response to this, the hold switch 21
3 is turned on, and the V CO212 is connected to the loop filter 21.
1, the carrier regenerator 23 performs a normal carrier regeneration operation.

The difference between the synchronization frequency of the carrier regenerator and the input frequency at this point is only the frequency difference between the transmitting stations corresponding to demodulator 2 and demodulator 3, respectively, and this frequency difference is generally extremely small, for example, 1 KIIZ or less. Therefore, demodulator 3
The synchronization establishment time of the carrier regenerator 23 is so small that it can be ignored, so that the line connection delay time can be minimized.

Effects of the Invention As described above, according to the present invention, a demodulator that is not in operation is controlled in advance so that the receiving channel is the same as that of the control line demodulator, and the demodulator that is not in operation is In response to the channel designation for the demodulator, the synchronization state of the carrier regenerator of this demodulator is held in the state immediately before the channel designation, the frequency synthesizer is operated, and then the synchronization state of the carrier regenerator is released. As a result, the synchronization time of the demodulator can be made extremely short. Therefore, even in a communication system where there is a large frequency fluctuation factor in the transmission path, it is possible to significantly shorten the synchronization time of the demodulator.

[Brief explanation of the drawing]

The figure is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 2...Control line demodulator 3...Other demodulators

Claims (1)

[Claims] A demodulator control method in a communication system having a control line demodulator connected to a control station and other demodulators, wherein the receiving channel of the other demodulator that is not in operation is controlled in advance. When the operating channel is specified for the demodulator for the line, and the operating channel is specified for the demodulator that is not in operation, the synchronization frequency of the carrier regeneration circuit of this demodulator is maintained at the frequency immediately before the channel was specified. A demodulator control method, characterized in that, after setting a frequency synthesizer of the demodulator, the carrier regeneration circuit is controlled to release the synchronous frequency holding state.