KR0135812B1 - Clock generator of composite image apparatus - Google Patents

Clock generator of composite image apparatus

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Publication number
KR0135812B1
KR0135812B1 KR1019940035084A KR19940035084A KR0135812B1 KR 0135812 B1 KR0135812 B1 KR 0135812B1 KR 1019940035084 A KR1019940035084 A KR 1019940035084A KR 19940035084 A KR19940035084 A KR 19940035084A KR 0135812 B1 KR0135812 B1 KR 0135812B1
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South Korea
Prior art keywords
signal
synchronization
phase difference
external
detector
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KR1019940035084A
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Korean (ko)
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KR960028167A (en
Inventor
최해민
최광식
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김광호
삼성전자주식회사
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Priority to KR1019940035084A priority Critical patent/KR0135812B1/en
Priority to JP7327584A priority patent/JPH08256291A/en
Priority to CN95120855A priority patent/CN1129305C/en
Priority to US08/575,016 priority patent/US5633688A/en
Publication of KR960028167A publication Critical patent/KR960028167A/en
Application granted granted Critical
Publication of KR0135812B1 publication Critical patent/KR0135812B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Synchronizing For Television (AREA)

Abstract

The clock generator of a composite video apparatus comprises a horizontal synchronous separator for detecting an outer horizontal synchronous signal from an outer composite synchronous signal; a phase difference detector for detecting a phase difference between an inner horizontal synchronous signal and the outer horizontal synchronous signal; a synchronous detector for detecting whether there is an outer composite synchronous signal and generating a synchronous detecting signal; a first oscillator for generating a first oscillation signal having a first frequency; a signal selector which selects a second oscillation signal having a second frequency and which selects and outputs the second oscillation signal if there is not the outer synchronism; a gate means for controlling the phase difference detecting signal responding to the synchronous detecting signal.

Description

복합영상장치의 클럭발생기Clock Generator of Complex Image Device

제1도는 본 발명에 의한 복합영상장치의 클럭발생기의 회로도.1 is a circuit diagram of a clock generator of a composite imaging apparatus according to the present invention.

본 발명은 클럭발생기에 관한 것으로서, 특히 영상장치에서 제 1 영상신호에 추종하는 제 2 영상신호처리장치의 클럭신호를 발생하는 클럭발생기에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator, and more particularly, to a clock generator for generating a clock signal of a second video signal processing apparatus that follows a first video signal in an image device.

최근에 다양한 기록매체의 출현으로 서로 다른 기록매체들로부터 얻어지는 영상신호들 간의 중첩이 요구되고 있으나 신호 포맷 차이로 인한 신호매칭기술이 요구되고 있다. 특히, 노래반주장치에서는 외부 배경영상신호에 노래가사의 자막신호를 중첩시키거나 내부 배경영상신호와 외부 배경영상신호의 절환이 요구되는 바, 배경영상신호에 따라서 내부신호처리의 클럭타이밍이나 동기를 매칭시켜야 하는 기술이 요구된다.Recently, with the advent of various recording media, overlapping between image signals obtained from different recording media is required, but signal matching techniques are required due to signal format differences. Particularly, in the song accompaniment apparatus, the subtitle signal of the song lyrics is superimposed on the external background video signal or the internal background video signal and the external background video signal are switched. Therefore, the clock timing or synchronization of the internal signal processing is performed according to the background video signal. There is a need for a technique to match.

본 발명의 목적은 이와같은 요구에 부응하여 외부 영상신호에 위상로크된 영상장치의 클럭발생기를 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a clock generator of a video device which is phase locked to an external video signal in response to such a requirement.

상기 목적을 달성하기 위하여 본 발명의 클럭발생기는 외부 복합동기신호(ECSYNC)로부터 외부 수평동기신호(EHSY)를 검출하는 동기신호분리기와, 내부 수평동기신호(IHSY)와 상기 동기신호분리기에서 검출된 외부 수평동기신호(EHSY)의 위상차를 검출하여 위상차 검출신호를 발생하는 위상차 검출기와, 외부 복합동기신호(ECSYNC)의 유무를 검출하여 동기검출신호를 발생하는 동기검출기와, 제1주파수를 가지는 제1발진신호를 발생하는 제1발진기와, 제2주파수를 가지는 제2발진신호를 발생하는 제2발진기와, 상기 동기검출기에서 발생된 동기검출신호에 응답하여 외부동기입력시에는 상기 제1발진기에서 발생된 제1발진신호를 선택하고, 외부동기가 없을 경우에는 상기 제2발진기에서 발생된 제2발진신호를 선택하여 출력하는 신호선택기와, 상기 동기검출기에서 발생된 동기검출신호에 응답하여 상기 위상차 검출기에서 발생된 위상차 검출신호의 통과여부를 제어하는 게이트 수단과, 상기 신호선택기에서 선택된 발진신호를 입력하여 분주하되, 상기 게이트 수단을 통과한 위상차 검출신호에 응답하여 외부 동기시에는 상기 위상차 만큼 지연시켜서 분주하고 상기 분주된 신호를 클럭신호로 발생하는 분주기와, 상기 분주기에서 발생된 신호로부터 내부 수평동기신호(IHSY)를 발생하여 상기 위상차 검출기에 제공하는 내부 동기신호발생기를 구비한 것을 특징으로 한다.In order to achieve the above object, the clock generator includes a synchronization signal separator for detecting an external horizontal synchronization signal EHSY from an external composite synchronization signal ECSYNC, and an internal horizontal synchronization signal IHSY and a signal detected by the synchronization signal separator. A phase difference detector for detecting a phase difference of the external horizontal synchronization signal EHSY and generating a phase difference detection signal, a synchronous detector for detecting the presence or absence of the external composite synchronization signal ECSYNC and generating a synchronization detection signal, and a first frequency having a first frequency. A first oscillator for generating a first oscillation signal, a second oscillator for generating a second oscillation signal having a second frequency, and a first oscillator for an external synchronous input in response to a synchronous detection signal generated by the synchronous detector; A signal selector for selecting a generated first oscillation signal and selecting and outputting a second oscillation signal generated by the second oscillator when there is no external synchronization; Gate means for controlling the passage of the phase difference detection signal generated by the phase difference detector in response to the synchronous detection signal generated by the input signal and the oscillation signal selected by the signal selector to be divided, and the phase difference detection signal passed through the gate means. In response to the external synchronization, the frequency divider divides the signal by delaying the phase difference and generates the divided signal as a clock signal, and generates an internal horizontal synchronization signal IHSY from the signal generated by the frequency divider to the phase difference detector. Characterized in that it comprises an internal synchronization signal generator to provide.

따라서, 본 발명에 의하면 외부동기신호에 위상로크된 클럭신호를 발생할 수 있다.Therefore, according to the present invention, a clock signal phase locked to the external synchronization signal can be generated.

첨부한 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.The present invention will be described in more detail with reference to the accompanying drawings.

제 1 도는 본 발명에 의한 영상신호의 클럭발생기의 회로도를 나타낸다. 클럭발생기는 동기신호분리기(10)와, 위상차 검출기(20)와, 동기검출기(30)와, 제 1 발진기(40)와, 제 2 발진기(50)와, 신호선택기(60)와, 게이트수단(70)와, 분주기(80)와, 내부 동기신호발생기(90; SYNCGEN)를 포함한다.1 is a circuit diagram of a clock generator of a video signal according to the present invention. The clock generator includes a synchronous signal separator 10, a phase difference detector 20, a synchronous detector 30, a first oscillator 40, a second oscillator 50, a signal selector 60, and gate means. 70, a divider 80, and an internal synchronizing signal generator 90 (SYNCGEN).

동기신호분리기(10)는 외부 복합동기신호(ECSYNC)를 인버터(G1)를 통해 저항(R1) 및 캐패시터(C1)로 구성된 원샷회로(11)에 인가되고 원샷회로(11)를 거치면서 수직동기신호는 제거되고 수평동기신호(외부수평동기신호:EHSY)만 인버터(G2)를 통해 출력되게 된다.The synchronizing signal separator 10 applies an external composite synchronizing signal ECSYNC to the one shot circuit 11 composed of the resistor R1 and the capacitor C1 through the inverter G1 and passes through the one shot circuit 11 to perform vertical synchronization. The signal is removed and only the horizontal synchronizing signal (external horizontal synchronizing signal EHSY) is outputted through the inverter G2.

위상차 검출기(20)는 제 1 플립플롭(FF1)의 클럭단자에는 상기 동기신호분리기(10)의 출력인 외부수평동기신호(EHSY)가 인가되고 데이타 입력단자와 세트단자에는 5V전원전압이 인가되고 클리어단자에는 제 2 플립플롭(FF2)의 정출력신호가 인가된다. 제 2 플립플롭(FF2)의 클럭단자에는 내부동기신호 발생기(90)에서 발생된 내부수평동기신호(IHSY)가 인가되고 데이타입력단자에는 접지가 연결되고 클리어단자에는 전원전압이 인가되고 세트단자에는 제 1 플립플롭(FF1)의 정출력신호가 인가된다. 제 1 플립플롭(FF1)의 정출력신호가 외부수평동기신호(EHSY)와 내부수평동기신호(IHSY)의 위상차 검출신호(PD)로 제공된다.The phase difference detector 20 receives an external horizontal synchronizing signal EHSY, which is an output of the synchronization signal separator 10, to a clock terminal of the first flip-flop FF1, and a 5V power supply voltage to a data input terminal and a set terminal. The constant output signal of the second flip-flop FF2 is applied to the clear terminal. The internal horizontal synchronization signal IHSY generated by the internal synchronization signal generator 90 is applied to the clock terminal of the second flip-flop FF2, the ground is connected to the data input terminal, the power supply voltage is applied to the clear terminal, and the set terminal is applied to the clock terminal of the second flip-flop FF2. The constant output signal of the first flip-flop FF1 is applied. The positive output signal of the first flip-flop FF1 is provided as a phase difference detection signal PD between the external horizontal synchronization signal EHSY and the internal horizontal synchronization signal IHSY.

동기검출기(30)는 트리거입력단자에 외부 복합동기신호(ECSYNC)를 입력하는 단안정 멀티 바이브레이터(MM1)의 정출력신호와 부출력신호를 신호선택기(60)의 스위칭에어신호로 제공되며 부출력신호는 또한, 게이트수단(70)의 제어신호로 제공된다. 저항(R3) 및 캐패시터(C2)는 단안정멀티바이브레이터(MM1)의 타임을 설정하기 위한 것이고 저항(R2)은 풀업저항이다. 따라서, 외부 복합동기신호(ECSYNC)가 인가될 경우에는 트리거단자에 계속해서 트리거필스가 인가되게 되므로 정출력신호는 하이상태로 유지되고 부출력상태는 로우상태로 유지된다. 그러다가 외부 복합동기신호(ECSYNC)의 입력이 없게 되면 저항 및 캐패시터에 의해 결정되는 시간만큼 정출력신호는 하이상태를 유지하다가 로우상태로 천이되게 된다. 그러므로, 외부 복합동기신호(ECSYNC)가 인가되는 경우에는 신호선택기(60)는 제 1 발진기(40)의 제 1 발진신호(58.5MHz)를 선택하여 출력하고 외부 복합동기신호(ECSYNC)가 사라지게 되면 제 2 발진기(50)의 제 2 발진신호(57.252MHz)를 선택하여 출력하게 된다. 제 1 발진신호(58.5MHz)는 레이저 디스크에서 재생된 영상신호와 동기를 맞추기 위한 기준발진신호이고 제 2 발진신호(57.252MHz)는 NTSC텔레비젼방식의 영상신호와 동기를 맞추기 위한 표준발진신호이다. 또한, 게이트수단(70)은 부출력신호의 로우상태에서는 위상차 검출신호(PD)를 통과시키고 하이상태에서는 차단하게 된다.The synchronous detector 30 provides the positive output signal and the negative output signal of the monostable multivibrator MM1 for inputting the external composite synchronous signal ECSYNC to the trigger input terminal as the switching air signal of the signal selector 60 and the sub output. The signal is also provided as a control signal of the gate means 70. The resistor R3 and the capacitor C2 are for setting the time of the monostable multivibrator MM1 and the resistor R2 is a pullup resistor. Therefore, when the external composite synchronization signal ECSYNC is applied, the trigger field is continuously applied to the trigger terminal, so that the constant output signal is kept high and the negative output state is kept low. Then, when there is no input of the external composite synchronization signal ECSYNC, the constant output signal remains high for a time determined by the resistor and capacitor, and then transitions to the low state. Therefore, when the external composite synchronization signal ECSYNC is applied, the signal selector 60 selects and outputs the first oscillation signal 58.5 MHz of the first oscillator 40 and the external composite synchronization signal ECSYNC disappears. The second oscillation signal 57.252 MHz of the second oscillator 50 is selected and output. The first oscillation signal (58.5MHz) is a reference oscillation signal for synchronizing with the video signal reproduced from the laser disk, and the second oscillation signal (57.252MHz) is a standard oscillation signal for synchronizing with the NTSC television type video signal. In addition, the gate means 70 passes the phase difference detection signal PD in the low state of the sub-output signal and blocks it in the high state.

분주기(80)에서는 내부동기시 제 2 발진신호(57.252Hz)를 입력하여 분주된 클럭신호를 발생하고 외부동기시 1 발진신호(58.5MHz)를 입력하여 외부수평동기신호(EHSY)에 위상로크되고 분주된 클럭신호를 발생한다. 즉, 외부동기시에는 위상차만큼 분주동작이 리세트되어 외부수평동기신호(EHSY)에 매칭된 클럭신호를 발생하게 된다.The divider 80 inputs a second oscillation signal (57.252 Hz) during internal synchronization to generate a divided clock signal, and inputs 1 oscillation signal (58.5 MHz) during external synchronization to phase lock the external horizontal synchronization signal (EHSY). And generate a divided clock signal. That is, during external synchronization, the division operation is reset by the phase difference to generate a clock signal matched to the external horizontal synchronization signal EHSY.

내부동기신호발생기(90)는 상기 분주된 클럭신호를 입력하여 수직동기신호, 수평동기신호, 수직블랭킹신호, 수평블랭킹신호 등을 발생하게 된다. 발생된 내부수평동기신호(IHSY)는 위상차검출기(20)에 제공된다. 따라서, 위상로크루프를 형성하게 되어 외부동기시에는 외부동기신호에 위상로크된 신호를 발생하게 된다.The internal synchronous signal generator 90 inputs the divided clock signal to generate a vertical synchronous signal, a horizontal synchronous signal, a vertical blanking signal, a horizontal blanking signal, and the like. The generated internal horizontal synchronizing signal IHSY is provided to the phase difference detector 20. Therefore, the phase lock loop is formed to generate a phase locked signal to the external synchronization signal during external synchronization.

이상과 같이 본 발명에서는 영상장치의 외부동기시에는 외부동기신호에 동기된 내부 클럭신호를 발생할 수 있으므로 영상중첩시에 매칭된 중첩신호를 발생할 수 있다.As described above, since the internal clock signal synchronized with the external synchronization signal may be generated when the image apparatus is externally synchronized, the overlapped signal may be generated when the image is overlapped.

Claims (1)

외부 복합동기신호(ECSYNC)로부터 외부 수평동기신호(EHSY)를 검출하는 동기신호분리기(10); 내부수평동기신호(IHSY)와 상기 동기신호분리기(10)에서 검출된 외부 수평동기신호(EHSY)의 위상차를 검출하여 위상차 검출신호를 발생하는 위상차 검출기(20); 외부 복합동기신호(ECSYNC)의 유무를 검출하여 동기검출신호를 발생하는 동기검출기(30); 제1주파수를 가지는 제1발진신호를 발생하는 제1발진기(40); 제2주파수를 가지는 제2발진신호를 발생하는 제2발진기(50); 상기 동기검출기(30)에서 발생된 동기검출신호에 응답하여 외부동기입력시에는 상기 제1발진기(40)에서 발생된 제1발진신호를 선택하고, 외부동기가 없을 경우에는 상기 제2발진기(50)에서 발생된 제2발진신호를 선택하여 출력하는 신호선택기(60); 상기 동기검출기(30)에서 발생된 동기검출신호에 응답하여 상기 위상차 검출기(20)에서 발생된 위상차 검출신호의 통과여부를 제어하는 게이트 수단(70); 상기 신호선택기(60)에서 선택된 발진신호를 입력하여 분주하되, 상기 게이트 수단(70)을 통과한 위상차 검출신호에 응답하여 외부동기시에는 상기 위상차만큼 지연시켜서 분주하고 상기 분주된 신호를 클럭신호로 발생하는 분주기(80); 및 상기 분주기(80)에서 발생된 신호로부터 내부 수평동기신호(IHSY)를 발생하여 상기 위상차 검출기(20)에 제공하는 내부 동기신호발생기(90)를 구비한 것을 특징으로 하는 영상장치의 클럭발생기.A synchronization signal separator 10 for detecting an external horizontal synchronization signal EHSY from the external composite synchronization signal ECSYNC; A phase difference detector 20 for detecting a phase difference between an internal horizontal synchronization signal IHSY and an external horizontal synchronization signal EHSY detected by the synchronization signal separator 10 and generating a phase difference detection signal; A synchronization detector 30 that detects the presence or absence of an external composite synchronization signal ECSYNC and generates a synchronization detection signal; A first oscillator 40 generating a first oscillation signal having a first frequency; A second oscillator 50 for generating a second oscillation signal having a second frequency; When the external synchronization is input in response to the synchronization detection signal generated by the synchronization detector 30, the first oscillation signal generated by the first oscillator 40 is selected, and when there is no external synchronization, the second oscillator 50 is selected. A signal selector 60 for selecting and outputting the second oscillation signal generated by the < RTI ID = 0.0 > Gate means (70) for controlling the passage of the phase difference detection signal generated by the phase difference detector (20) in response to the synchronization detection signal generated by the synchronization detector (30); The oscillation signal selected by the signal selector 60 is input and divided, and in response to the phase difference detection signal passing through the gate means 70, the external signal is delayed and divided by the phase difference, and the divided signal is converted into a clock signal. Generating frequency divider 80; And an internal synchronization signal generator 90 for generating an internal horizontal synchronization signal IHSY from the signal generated by the divider 80 and providing it to the phase difference detector 20. .
KR1019940035084A 1994-12-19 1994-12-19 Clock generator of composite image apparatus KR0135812B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019940035084A KR0135812B1 (en) 1994-12-19 1994-12-19 Clock generator of composite image apparatus
JP7327584A JPH08256291A (en) 1994-12-19 1995-12-15 Image superposing device
CN95120855A CN1129305C (en) 1994-12-19 1995-12-18 Image superimposing apparatus
US08/575,016 US5633688A (en) 1994-12-19 1995-12-19 Image superimposing apparatus for superimposing the encoded color televison signal with the external composite video signal

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KR1019940035084A KR0135812B1 (en) 1994-12-19 1994-12-19 Clock generator of composite image apparatus

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KR0135812B1 true KR0135812B1 (en) 1998-04-27

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