JP3045393B2 - Video camera - Google Patents

Description

The present invention relates to, for example, a consumer video camera.

[Summary of the Invention]

The present invention relates to a video camera, and outputs a character signal by superimposing an arbitrary character signal on a video signal, generates a character signal by a synchronization signal from a synchronization generation circuit, and superimposes a synchronization signal from the generation circuit on the character signal. In addition, a character signal can be displayed on the viewfinder even when there is no video signal.

[Conventional technology]

For example, in a consumer video camera, a so-called character signal such as a tape counter, a mode display, or characters, symbols, or graphics for performing various warnings is superimposed on a video signal and displayed on a viewfinder or output on a line. It is considered that the image is projected on a monitor receiver or the like through a terminal. In such a case, conventionally, a synchronizing signal of the video signal is separated, a character generating circuit is driven by the synchronizing signal, and the generated character signal is superimposed on the video signal.

[Problems to be solved by the invention]

However, in the above-described configuration, for example, when the line input is selected and no signal is supplied to the terminal, when the reception is not performed in the built-in tuner mode, or when the video signal is recorded only on the unrecorded tape or AFM signal When a video signal is not obtained, as in the case of reproducing a tape on which no character signal is recorded, the above-mentioned character signal cannot be generated and no image can be projected. However, even in such a case, the above information is required.

The present application has been made in view of such points.

[Means for solving the problem]

The present invention provides a supply means (terminal (1)) for supplying a video signal, a separation means (circuit (7)) for separating a horizontal / vertical synchronization signal from the supplied video signal, Synchronizing signal generating means (12) for generating a horizontal / vertical and composite synchronizing signal synchronized with the horizontal / vertical synchronizing signal from a signal via a PLL circuit (phase comparator circuit (9) to VCO (11)); Detecting means (detection circuit (28)) for detecting the presence / absence, and when a video signal is detected by the detecting means, outputting at least a horizontal / vertical synchronization signal based on the separated horizontal / vertical synchronization signal; When it is detected by the means that there is no video signal, the synchronous signal generating means is separated from the separating means and the PLL circuit is freely driven to output the horizontal / vertical and composite synchronous signals generated. Switching means for (switch (10)) and the character signal generating means for generating a character signal in response to the horizontal and vertical synchronizing signals generated as above (15)
And inputting the video signal, and when the video signal is not detected by the detection means, forms an internal output signal based on the composite synchronization signal from the synchronization signal generation means,
When there is a predetermined display mode instruction (terminal (18)), first output means (switch (3)) for superimposing a character signal from the character signal generating means on the video signal or the internal output signal and outputting the superposed signal. To (5)), an output terminal (6) for extracting a signal from the first output means, the video signal or the internal output signal, and when there is no instruction for the predetermined display mode, the video signal is output. A second output for outputting a signal from the first output means when the signal or the internal output signal is superimposed with a character signal from the character signal generation means and outputting the predetermined display mode instruction; Means (resistors (22) and (27)) and the second
And a view finder (terminal (24)) to which a signal from the output means is supplied.

(Operation)

According to this, when there is no video signal, the PLL circuit is freely driven to drive the synchronizing circuit and the character generating circuit, and the generated synchronizing signal and the character signal are superimposed to display a good character signal. be able to.

〔Example〕

In FIG. 1, (1) is a recording / reproducing system (not shown).
The video signal from this terminal (1) is supplied to a clamp circuit (2) to fix the DC level. A signal from the clamp circuit (2) is taken out to a line output terminal (6) through a series circuit of switches (3), (4) and (5).

Further, a signal from the clamp circuit (2) is supplied to the synchronization separation circuit (7). The synchronization signal separated by the separation circuit (7) is further supplied to a horizontal synchronization separation circuit (8) to separate the horizontal synchronization signal HD. The horizontal synchronizing signal HD is supplied to the phase comparison circuit (9), and the comparison output is set to the switch (1).
0) is supplied to a variable oscillator (VCO) (11), and this oscillation output is supplied to a synchronization generation circuit (12). Then, the generated horizontal synchronizing signal HD is supplied to the phase comparison circuit (9) to form a PLL circuit, and the phase of the horizontal synchronizing signal HD from the synchronization generating circuit (12) matches the input video signal.

Further, the synchronization signal separated by the separation circuit (7) is further supplied to the vertical synchronization separation circuit (13) to separate the vertical synchronization signal VD. This vertical synchronization signal VD is supplied to the reset of the synchronization generation circuit (12) through the OR circuit (14). The phase of the vertical synchronizing signal thus generated is matched with the input video signal.

The horizontal / vertical synchronization signals HD / VD generated by the synchronization generation circuit (12) are supplied to a character generation circuit (15). As a result, an arbitrary character signal synchronized with the input video signal and its background signal are generated from the character generation circuit (15). The character signal and the background signal are respectively AND circuits (16) (1
7) supplied to. The terminal (18) is supplied with a control signal (data screen ON / ▲ ▼) for superimposing the character signal on the line output video signal, and the control signal is supplied to the AND circuits (16) and (17). Is done. As a result, when the character signal is superimposed on the line output video signal (data screen ON), the character signal and the background signal are output through the AND circuits (16) and (17). The background signal from the AND circuit (17) is supplied to the control of the switch (3) through the OR circuit (19), during which the switch (3) is switched to the DC voltage source (20) of the black level. The character signal from the AND circuit (16) is supplied to the control of the switch (4), during which the switch (4) is switched to the white level DC voltage source (21).

In this way, the character signal is superimposed on the video signal in the above circuit, and the superimposed signal is sent to the line output terminal (6).
Is taken out. When this circuit is applied to a video camera, a signal taken out from a line output terminal (6) is supplied to the base of a buffer transistor (23) through a resistor (22). twenty three)
Is supplied to an output terminal (24) for an electronic viewfinder (EVF).

If the above circuit does not superimpose the character signal on the line output video signal (data screen OFF),
The output signals from the AND circuits (16) and (17) are cut off.
On the other hand, the character signal from the character generation circuit (15) is supplied to the AND circuit (25), and the control signal from the terminal (18) is supplied to the AND circuit (25) through the inverter (26). The signal from the AND circuit (25) is supplied to the base of the transistor (23) through the resistor (27). As a result, a video signal on which a character signal is not superimposed is extracted from the line output terminal (6), and the character signal from the AND circuit (25) is synthesized with the video signal by resistors (22) and (27). The composite signal is output to the EVF output terminal (24) through the transistor (23).

Then, for this circuit, the synchronization signal from the synchronization separation circuit (7) is supplied to the detection circuit (28), and the presence or absence of the synchronization signal (video signal) is determined. When there is a video signal from the detection circuit (28), the high potential signal is inverted and supplied to the OR circuit (29). A control signal for muting the video signal is supplied to the terminal (30), and the control signal is supplied to the OR circuit (29). The signal from the OR circuit (29) is supplied to the OR circuits (14) and (19),
This is supplied to the control of the switch (10), during which the switch (1
0) is turned off. Further, a signal is supplied from the OR circuit (29) to the control of the switch (31), during which the switch (31)
The composite synchronizing signal Sync from the synchronizing circuit (12) is supplied to the control of the switch (5) through this, and the switch (5) is switched to the sync tip level DC voltage source (32) during this time.

Therefore, in this circuit, when the control signal from the terminal (18) is at a high potential and the output signal of the OR circuit (29) is at a high potential, the switch (10) is turned off and the OR circuit (14) is turned off.
Is cut off, the VCO (11) is freely driven (free-run), and the synchronization generation circuit (12) is driven by the oscillation output of the VCO (11). The signal from the synchronization generation circuit (12) is supplied to a character generation circuit (15), and a character signal synchronized with the signal is generated. The switch (4) is controlled through an AND circuit (16), and the background is changed. The output of the OR circuit (19) is set to a high potential, and the switch (3) is switched to the entire black level. Further, a composite synchronizing signal Sync from the synchronizing circuit (12) is supplied to the control of the switch (5) through the switch (31), a synchronizing signal is added, and a character signal is superimposed on the background of the black level. The internal output signal to which the signal is added is output to the line output terminal (6) and the EVF output terminal (2
4) is taken out.

When the control signal from the terminal (18) is at a low potential, the AND circuit (16) is shut off, and the internal output signal with the composite synchronization signal added to the black level background is output to the line output terminal (6).
At the same time, this signal is combined with the character signal from the AND circuit (25) by the resistors (22) and (27), and is output to the EVF output terminal (24).

When the above circuit is applied to a VTR having a jog mode, the pseudo vertical synchronizing signal (jog VD) supplied to the terminal (33) is supplied to the control of the switch (5) through the switch (31). Screen stability in the jog mode. In the above circuit, terminals (18) (30)
The control signal and jog VD supplied to (33) are supplied from a control microcomputer (μ-COM) or the like.

Thus, according to the above-described circuit, when there is no video signal, the PLL circuit is freely driven to drive the synchronization generation circuit and the character generation circuit, and the generated synchronization signal and the character signal are superimposed, thereby displaying a good character signal. Can go out.

That is, in the circuit described above, the operation can be summarized as the second
As shown in the figure.

FIG. 3 shows a specific example of a main part of a PLL circuit applied to the above-described circuit. In this example, in this example, a so-called charge pump type circuit configuration is used, and an up (UP) or down (DN) control signal from the phase comparison circuit (9) is an OR circuit (10) forming a switch (10), respectively.
a) (10b) through tristate buffer (41a) (4
1b) is supplied to the control. At the time of the up control, the tri-state buffer (41a) is turned on, and the power supply V _DD is _supplied through the resistors (42a) (43) and the capacitors (44) (45).
In the case of down control, the transstate buffer (41b) is turned on and the ground potential is supplied to the VCO through the resistors (42b) (43) and the capacitors (44) (45).
Supplied to (11). This controls the VCO (11). In this case, the characteristics of the loop filter of the PLL circuit can be obtained by the resistors (42a) (42b) (43) and the capacitors (44) (45).

On the other hand, the switch (10) (OR circuit (10a) (10
When b)) is switched, the high potential from the OR circuit (29) is supplied to both the tri-state buffers (41a) and (41b). This allows the tri-state buffer (41
a) (41b) are both turned on, and the power supply _VDD and the ground potential are connected by the resistors (42a) and (42b). Therefore, the resistors (42a) and (42b) serve as a bias circuit for the VCO (11). For example, by making these resistance values equal,
A potential of 1/2 V _DD is supplied to the VCO (11), and the VCO (11) is freely driven at a desired frequency.

That is, according to this circuit, when the conventional phase comparison circuit → loop filter → analog switch → bias circuit → VCO is connected, a buffer circuit is required between the loop filter and the bias circuit, or a buffer circuit is required. In the absence of such a problem, it is possible to solve the problem that the gain of the loop filter decreases due to the influence of the bias circuit and the phase lock error increases.

According to the present invention, when there is no video signal, the PLL circuit is freely driven to drive the synchronization generation circuit and the character generation circuit, and the generated synchronization signal and the character signal are superimposed,
A good character signal can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. (1) is a video input terminal, (2) is a clamp circuit,
(3) (4) (5) (10) (31) are switches, (6) is a line output terminal, (7) (8) (13) is a sync separation circuit,
(9) is a phase comparison circuit, (11) is a variable oscillator, (12) is a synchronization generation circuit, (14), (19) and (29) are OR circuits, and (15)
Is a character generation circuit, (16), (17) and (25) are AND circuits,
(18) (30) (33) are terminals, (20) (21) (32) are voltage sources, (22) (27) are resistors, (23) are transistors,
(24) is an EVF output terminal, (26) is an inverter, and (28) is a detection circuit.

Claims (1)

(57) [Claims] A supply unit that supplies a video signal; a separation unit that separates a horizontal / vertical synchronization signal from the supplied video signal; and a horizontal / vertical synchronization from the separated horizontal / vertical synchronization signal via a PLL circuit. Synchronizing signal generating means for generating a horizontal / vertical and composite synchronizing signal synchronized with the signal; detecting means for detecting the presence / absence of the video signal; and when the detecting means detects a video signal, the separated horizontal / vertical signal is output. By outputting at least a horizontal / vertical synchronization signal based on the synchronization signal, and when the detection means detects that there is no video signal, the synchronization signal generation means is separated from the separation means to freely drive the PLL circuit. Switching means for outputting the generated horizontal / vertical and composite synchronization signals; and a sentence for generating a character signal according to the generated horizontal / vertical synchronization signals. A signal generating means for inputting the video signal, and when the video signal is not detected by the detecting means, forming an internal output signal based on a composite synchronizing signal from the synchronizing signal generating means, and instructing a predetermined display mode When there is, first output means for superimposing and outputting a character signal from the character signal generating means on the video signal or the internal output signal, an output terminal for extracting a signal from the first output means, The video signal or the internal output signal is input, and when there is no instruction of the predetermined display mode, a character signal from the character signal generating means is superimposed on the video signal or the internal output signal and output. When there is a display mode instruction, a second output means for outputting a signal from the first output means, and a signal from the second output means Video camera and having a a viewfinder supplied.