JP3137715B2 - Digital still picture device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital still picture apparatus using, for example, a digital memory.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional digital still picture apparatus. This example is provided with two clock sources.

In FIG. 1, a composite video signal SVin supplied to an input terminal 1 is converted into a digital signal by an A / D converter 2 and then supplied to an input side image processing circuit 3. The image processing circuit 3 performs processing such as data compression, and the output data is supplied to the image memory (digital memory) 4 as write data.

The data read from the image memory 4 is supplied to an output side image processing circuit 5. In the image processing circuit 5, processing such as data expansion is performed, and the output data is converted into an analog signal by a D / A converter 6, and is output to an output terminal 7 as an output video signal SVout.

[0005] The video signal SVin supplied to the input terminal 1 is supplied to the AFC circuit 8. The write clock WCK output from the voltage controlled oscillator (VCO) 9 is supplied to the AFC circuit 8. The PLL loop of the AFC circuit 8 is configured as shown in FIG.

The video signal SV is output by the sync separation circuit 81.
The synchronization signal is separated from in, and the synchronization signal is supplied to the phase comparator 82. Clock W output from VCO 9
CK is supplied to the synchronization generator 83, and a synchronization signal synchronized with the clock WCK is output from the synchronization generator 83. The synchronization signal output from the synchronization generator 83 is
And the phase is compared with the synchronization signal separated by the synchronization separation circuit 81. Then, the phase comparison error signal output from the phase comparator 82 is supplied to the VCO 9 as a control signal. Thus, the write clock WCK is controlled so as to synchronize with the synchronization signal of the video signal SVin.

Returning to FIG. 5, the clock WCK output from the VCO 9 is supplied to the A / D converter 2, the image processing circuit 3, and the write timing generator 10 in addition to being supplied to the AFC circuit 8 as described above. Supplied. The timing generator 10 is supplied with horizontal and vertical synchronization signals from the AFC circuit 8.

In the timing generator 10, the clock WC
Based on K and the synchronization signal, various timing signals used in the image processing circuit 3 and a write address signal WAD supplied to the memory 4 are formed.

Reference numeral 11 denotes a clock generator for generating a read clock RCK. The read clock RCK output from the clock generator 11 is
And the D / A converter 6 and the synchronization generator 1
2 and the read timing generator 13.

The synchronization generator 12 generates horizontal and vertical synchronization signals in synchronization with the clock RCK. The synchronization signals are supplied to a read timing generator 13. In the timing generator 13, various timing signals used in the image processing circuit 5 and a read address signal R supplied to the memory 4 are determined based on the clock RCK and the synchronization signal.
AD is formed.

Reference numeral 14 denotes a controller, which controls the operations of the timing generators 10, 13 and the memory 4, and switches between the normal mode and the still mode. In the normal mode, the video signal SVin supplied to the input terminal 1 is sequentially updated and written to the memory 4, and the sequentially updated data is read from the memory 4 to obtain the video signal SVout at the output terminal 7. . On the other hand, when the mode is switched to the still mode, the writing is stopped and the video signal SVin of the predetermined screen is written in the memory 4. Then, in this state, the same data is repeatedly read from the memory 4, and a video signal SVout of a still image is obtained at the output terminal 7.

FIG. 7 shows another example of a conventional digital still picture apparatus. This example is also an example having two clock sources. In the example of FIG. 5, the write clock WCK is synchronized with the synchronization signal of the video signal SVin, but in this example, the clock WCK is synchronized with the color burst of the video signal SVin. 7, parts corresponding to those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the video signal SVin supplied to the input terminal 1 is supplied to the APC circuit 21. AP
The write clock WCK output from the VCO 9 is supplied to the C circuit 21. Reference numeral 22 denotes a synchronization generator. The synchronization generator 22 is supplied with a video signal SVin and a clock WCK. A described above
A burst gate pulse (burst position pulse) BGP is supplied from the synchronization generator 22 to the PC circuit 21. A
The PLL loop of the PC circuit 21 is configured as shown in FIG.

The phase comparator 211 has a video signal SVin
And the clock WCK output from the VCO 9 is supplied. The comparison error signal output from the phase comparator 211 is supplied to the V
It is supplied to CO9 as a control signal. Connection switch 21
2 is supplied with a pulse BGP and turned on corresponding to the burst position. As a result, only the comparison error signal obtained by comparing the phase of the color burst with the clock WCK is supplied to the VCO 9 as a control signal, and the write clock WCK is controlled so as to synchronize with the color burst of the video signal SVin.

The present embodiment is configured as described above, and other configurations and operations are the same as those in the example of FIG. In this example, horizontal and vertical synchronization signals are supplied from the synchronization generator 22 to the write timing generator 10.

[0016]

As described above, the digital still picture apparatus shown in FIGS. 5 and 7 requires two clock sources for writing and reading. For this reason, it is inevitable to reduce the image quality due to the interference between the clocks WCK and RCK, and to complicate the circuit and increase the cost due to having two clock sources.

Here, assuming that the read system is driven by the write clock WCK as shown in FIG. 4, a clock source dedicated to the read system is not required, and the above-described problems such as interference are eliminated. Note that, in FIG. 4, portions corresponding to those in FIG. 5 are denoted by the same reference numerals.

However, in the example of FIG. 4, the following new problem occurs. That is, in the still mode, if the video signal SVin supplied to the input terminal 1 is disturbed or the supply of the video signal SVin is interrupted, the AFC
The operation of the circuit 8 is disturbed, so that the clock WCK output from the VCO 9 is also disturbed.
CK is not output. Such disturbance of the clock WCK affects the operation of the read-out circuit, causing disturbance in the still screen or stopping output of the video signal SVout. Such a situation is considered to occur frequently, for example, when reproducing a VTR or when switching channels of a tuner, which is inconvenient for a still image device.

When the read system is driven by the write clock WCK in the example of FIG. 7, the same problem as described above occurs.

Therefore, in the present invention, even if it is composed of only one clock source, the disturbance of the input video signal does not affect the still screen in the still mode.

[0021]

SUMMARY OF THE INVENTION The present invention relates to a digital still picture apparatus for writing an input video signal to a digital memory and reading a video signal from the digital memory to obtain an output video signal. A common clock is used. In the normal mode, the clock is synchronized with the input video signal, and in the still mode, the state of the clock is maintained at a state immediately before mode switching.

[0022]

In the still mode, the clock state is maintained at the state immediately before the mode switching, so that even if the input video signal SVin is disturbed, the clock WCK is not disturbed. Therefore, the disturbance of the input video signal SVin has no effect on the still screen in the still mode.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, portions corresponding to FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this example, the clock WCK output from the VCO 9 is output from the output side image processing circuit 5,
It is also supplied to the D / A converter 6, the synchronization generator 12, and the read timing generator 13.

The AFC circuit 8 is sent from the controller 14.
Is supplied with a control signal SC. Then, in the normal mode, the clock WCK is controlled so as to be synchronized with the synchronization signal of the video signal SVin, and in the still mode, the state of the clock WCK is held at the state immediately before the mode switching.

When the control signal SC is supplied from the controller 14 to the VCO 9 and the mode is switched from the normal mode to the still mode, the mode output from the phase comparator 82 to the latch means of the control signal input section of the VCO 9 will be described later. The comparison error signal immediately before the switching is held.

FIG. 2 shows a configuration of a PLL loop of the AFC circuit 8. 2, parts corresponding to those in FIG. 6 are denoted by the same reference numerals. The example in FIG. 2 is a case where the comparison error signal output from the phase comparator 82 is a digital signal, and is an example in which a control signal input section of the VCO 9 is provided with latch means (not shown).

In the figure, a connection switch 84 is arranged between the phase comparator 82 and the VCO 9. ON / OFF of the connection switch 84 is controlled by the control signal SC. That is, the connection switch 84 is turned on in the normal mode,
It is turned off in the still mode.

The present example is configured as described above, and the other parts are configured in the same manner as the example of FIG. In the example of FIG. 2, in the normal mode, the connection switch 84 is turned on. Therefore, the comparison error signal output from the phase comparator 82 is VC
O9 is constantly supplied as a control signal, and the clock WCK
Is controlled so as to synchronize with the synchronization signal of the video signal SVin.

On the other hand, when switching from the normal mode to the still mode, the connection switch 84 is turned off and the VCO
The comparison error signal immediately before the mode switching output from the phase comparator 82 is held in the latch means of the control signal input unit 9. Therefore, in the still mode, the frequency of the clock WCK output from the VCO 9 is not affected by the phase of the synchronization signal of the video signal SVin, and a constant frequency determined by the comparison error signal immediately before switching is maintained.

As described above, according to this embodiment, the read system is also driven by the write clock WCK, so that a dedicated clock source for the read system is not required, and there is no problem such as interference between clocks. Further, in the still mode, the state of the clock WCK is held at the state immediately before the mode switching, so that even if the synchronization signal of the input video signal SVin is disturbed, the clock WCK does not disturb, and the still picture is disturbed. Disappears.

FIG. 3 shows another example of the PLL loop of the AFC circuit 8. 3, parts corresponding to those in FIG. 2 are denoted by the same reference numerals. The example of FIG. 3 is a case where the comparison error signal output from the phase comparator 82 is an analog signal, and is an example in which the control signal input unit of the VCO 9 does not include a holding unit.

In the figure, connection switch 84 and VCO 9
A capacitor 85 for holding a voltage is connected between the terminals. ON / OFF of the connection switch 84 is controlled by the control signal SC as in the example of FIG. In this case, even if the mode is switched from the normal mode to the still mode and the connection switch 84 is turned off, the capacitor 85 holds the comparison error signal output from the phase comparator 82 immediately before the mode switching.

Therefore, as in the example of FIG. 2, the frequency of the clock WCK output from the VCO 9 in the still mode is not affected by the phase of the synchronization signal of the video signal SVin, and is a constant frequency determined by the comparison error signal immediately before the mode switching. Is held.

However, in an actual circuit, the connection switch 8
The comparison error signal gradually discharges due to the leak current of the VCO 9 itself, the input terminal of the VCO 9, and the board on which the capacitor 85 is mounted, and the frequency of the VCO 9 is deviated. However, the use of long-time stills, which generally last for more than several tens of minutes, is rare, and seems to be at most about 5 minutes. In this time, the input / output terminals of the connection switch 84 and the VCO 9 are connected to the CM.
By using an OS or the like to achieve high impedance and using a low-leakage film capacitor as the capacitor 85, it is possible to sufficiently hold the capacitor. Therefore, FIG.
The same operation and effect as the case of using the example of FIG. 2 can be obtained by using the example of FIG.

Although the above-described embodiment corresponds to the example shown in FIG. 5, similarly to the example shown in FIG. 7, the clock WCK is configured to be synchronized with the color burst of the video signal SVin. Of course, it can be applied.

[0037]

According to the present invention, since it can be constituted by one clock source, interference between clocks, circuit complexity,
There is no problem such as an increase in cost. Further, in the still mode, the clock state is maintained at the state immediately before the mode switching, so that even if the input video signal is disturbed, the clock is not disturbed, and the disturbance of the input video signal is displayed on the still screen in the still mode. Has no effect.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram illustrating a configuration of a PLL loop of the AFC circuit in the example of FIG. 1;

FIG. 3 is a block diagram showing another configuration of the PLL loop of the AFC circuit.

FIG. 4 is a block diagram illustrating an example of a digital still image device.

FIG. 5 is a block diagram showing a conventional example of a digital still picture device.

FIG. 6 is a diagram illustrating a configuration of a PLL loop of the AFC circuit in the example of FIG. 5;

FIG. 7 is a block diagram showing another conventional example of a digital still picture device.

8 is a diagram illustrating a configuration of a PLL loop of the APC circuit in the example of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 3 Input side image processing circuit 4 Image memory 8 AFC circuit 9 Voltage control oscillator 10 Write timing generator 12 Synchronization generator 13 Read timing generator 14 Controller 81 Synchronization separation circuit 82 Phase comparator 83 Synchronization generator 84 Connection switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/937 G09G 5/00-5/399

Claims (1)

(57) [Claims] 1. A digital still picture device for writing an input video signal to a digital memory and reading a video signal from the digital memory to obtain an output video signal, wherein a clock common to a writing side and a reading side of the memory is used. A digital still picture apparatus wherein the clock is synchronized with the input video signal in a normal mode, and the state of the clock is maintained in a state immediately before a mode switch in a still mode.