JPH0581767A - Device for correcting time base of video signal - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by constituting a time base correcting device eliminating the time base fluctuation of an input video signal by one field memory. CONSTITUTION:The input video signal is written in the field memory 1 by a write clock WCK generated from a horizontal synchronizing signal HD1 in the input video signal and a write address WA from a write address generating circuit 9. The read clock RCK of the field memory 1 is generated by a VXO 15 in a PLL 12. The oscillation frequency of the VXO 15 is controlled by responding to the low frequency component of the phase difference between a vertical synchronizing signal VD1 and a reference vertical synchronizing signal VD2. Thus. the read clock RCK is not free-running but locked to the low frequency component of the time base fluctuation of the input video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal time base correction apparatus applied to remove a time base fluctuation of a video signal recorded in a VTR, for example.

[0002]

2. Description of the Related Art In a video signal reproduced by a VTR,
A time-axis fluctuation component called jitter is included. In the normal time when this reproduced video signal is supplied to the monitor, the remaining time-axis fluctuation is corrected on the monitor side, and there is no problem of noticeable deterioration of image quality. However, when the reproduced video signal is recorded again by the analog or digital VTR, the remaining time-axis fluctuation cannot be ignored.

In order to remove this time-axis fluctuation of the video signal to be recorded on the VTR, a time-axis correction device (T
(Referred to as BC) is used. The conventional TBC is provided with two field memories (that is, a frame memory), the input video signal is written with a write clock synchronized with the horizontal synchronizing signal of the input video signal, and the video is written with a free-running read clock. The signal is being read.
Since there is a time axis variation, the read address approaches the write address and there is a risk of overtaking. This possibility of overtaking is detected by, for example, monitoring the difference between the write address and the read address. After this detection, the video signal of the field that has already been read is read again and the video signal of the current field is skipped.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Requires two field memories, which is disadvantageous in terms of power consumption, cost, and the number of parts. Further, when the difference between the frequencies of the writing and reading clocks is large, field skipping frequently occurs, and as a result, there is a problem that the image quality deteriorates.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an improved TBC of a video signal in which no field skip occurs and only one field memory is required.

[0006]

DISCLOSURE OF THE INVENTION The present invention is a video signal time base correction apparatus for correcting the time base of an input video signal based on a reference signal, which comprises a field memory (1) and an input video. A circuit (9) for writing the input video signal in the field memory (1) by the write clock WCK generated from the horizontal synchronization signal HD1 in the signal, and the vertical synchronization signal VD1 and the reference vertical synchronization signal VD2 in the input video signal. By performing a phase comparison between and, the circuits (13, 14) for generating the control voltage in response to the low frequency component of the time base fluctuation of the input video signal and the frequency of the output signal in response to the control voltage are changed. A variable frequency oscillation circuit (15) and a variable frequency oscillation means (15) are coupled to generate a reference vertical synchronizing signal VD2 and a reference horizontal synchronizing signal HD2. A synchronizing signal generating circuit (11), is combined with the synchronizing signal generating circuit (11), the circuit generates a read clock RCK of the field memory (1) (1
0) and a video signal time base correction device.

[0007]

The read clock of the field memory 1 is not free-running, and the PLL 12 generates the read clock RCK locked to the low frequency component of the phase difference between the vertical synchronizing signal VD1 and the reference vertical synchronizing signal VD2 in the input video signal. . Therefore, in the field memory 1, there is no possibility of overtaking, field skip processing does not occur, and the TBC can be configured with only one field memory 1.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 is a field memory including a semiconductor memory. The field memory 1 is supplied from the input terminal 2 to the A / D converter 3,
The video signal converted into a digital signal by the / D converter 3 is supplied. The digital video signal read from the field memory 1 is supplied to the sync signal adding circuit 4, and the sync signal adding circuit 4 adds the reference sync signal. Then, the analog video signal is taken out from the D / A converter 5 to the output terminal 6. As an example, the input video signal is reproduced by a home VTR, where V
A time axis variation (called jitter) corresponding to the frequency variation of the crystal oscillator provided in the TR reproducing circuit remains. The output video signal is recorded by a rotary head type VTR (not shown).

The sync separation circuit 7 separates the horizontal sync signal HD1 and the vertical sync signal VD1 in the input video signal. The horizontal synchronizing signal HD1 is supplied to the AFC circuit 8 and the write address generating circuit 9, and the vertical synchronizing signal VD1 is supplied to the write address generating circuit 9. The write address generation circuit 9 is mainly composed of an address counter. The AFC circuit 8 generates a write clock WCK synchronized with the horizontal sync signal HD1. This write clock WCK is supplied to the field memory 1 and the write address generation circuit 9. The write address WA from the write address generation circuit 9 is supplied to the field memory 1.

When the write address WA is supplied, the field memory 1 sequentially stores valid signals in the video signals of one field, that is, video signals other than the horizontal and vertical sync signals. The video signal stored in the field memory 1 is read based on the read address RA and the read clock RCK. In order to generate the read clock RCK, a PLL 12 surrounded by a broken line is provided.

The PLL 12 includes a phase comparison circuit 13, a low pass filter 14 and a VXO (voltage controlled solid state oscillator) 1.
It consists of 5. The VXO 15 includes a solid-state oscillator 16 and changes the frequency of its output signal in response to the control voltage from the low pass filter 14. Preferably, the solid-state oscillator 16
Has a lower Q than a crystal such as lithium tantalate. As a result of the low Q, the variable frequency range can be widened, and the frequency change response to the control voltage of the VXO 15 becomes slow. When the Q of the VXO 15 is not sufficiently low, the cutoff frequency of the low pass filter 14 needs to be lowered to about 0.1 Hz to several Hz.

Read clock RC from this VXO 15
K is supplied to the read address generation circuit 10 and the synchronization signal generation circuit 11. The sync signal generation circuit 11 divides the read clock to generate the reference horizontal sync signal H.
D2 and the reference vertical synchronizing signal VD2 are generated. The reference horizontal synchronizing signal HD2 and the vertical synchronizing signal VD2 from the synchronizing signal generating circuit 11 are supplied to the synchronizing signal adding circuit 4,
These reference synchronization signals are added to the video signal read from the field memory 1.

The phase comparison circuit 13 of the PLL 12 is supplied with the reference vertical synchronizing signal VD2 and the input vertical synchronizing signal VD1, and an output signal corresponding to the phase difference between the two is obtained. The control voltage of the VXO 15 is obtained by passing the phase comparison output through the low-pass filter 14. Therefore,
The frequency of the read clock RCK from the VXO 15 changes in response to a considerably low frequency component in the phase difference between the vertical synchronizing signal VD1 of the input video signal and the reference vertical synchronizing signal VD2.

Further, in this example, since the video signal from the output terminal 6 is recorded in the VTR, the reference vertical synchronizing signal VD2 is supplied as a servo reference signal to the drum servo circuit 17 of this VTR.

[0015]

According to the present invention, the frequency of the read clock of the field memory is changed by the PLL 12 in response to a considerably low frequency component of the frequency fluctuation of the input video signal, thereby eliminating the possibility of overtaking. As a result, the field skip processing is not performed and the image quality is not deteriorated. Further, the TBC can be configured with a memory of one field, the power consumption can be reduced, and the number of parts can be reduced, so that the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 Field Memory 2 Input Terminal 6 Output Terminal 9 Write Address Generation Circuit 10 Read Address Generation Circuit 12 PLL

Claims (1)

[Claims] 1. A time axis correction device for a video signal for correcting the time axis of an input video signal based on a reference signal, comprising a field memory and writing generated from a horizontal synchronizing signal in the input video signal. A means for writing the input video signal to the field memory by means of a clock and a phase comparison between the vertical synchronizing signal in the input video and a reference vertical synchronizing signal are used to reduce the time-axis variation of the input video signal. Means for generating a control voltage in response to a frequency component, variable frequency oscillating means for changing the frequency of its output signal in response to the control voltage, and the variable frequency oscillating means for coupling the reference vertical synchronizing signal and the reference A sync signal generating means for generating a horizontal sync signal, and a read-out of the field memory coupled to the sync signal generating means. A time-axis correction device for a video signal, which comprises a means for generating a clock.