JPS6027286A - Video input processing device - Google Patents

Abstract

PURPOSE:To prevent a distortion of picture due to the jitter which is generated at a VTR input time, by using the sampling clock, which is outputted from a counter incorporated in a PLL circuit, as a horizontal synchronizing signal for picture processing. CONSTITUTION:A sampling clock CLK outputted from a counter 24 incorporated in a PLL circuit 20 and a horizontal synchronizing signal H-SYNC' for picture processing (phase comparison signal) are used for the write to a picture memory 18 and are synchronized completely with each other independently of disturbance of synchronization of a video signal VIEDEO in distinction from the relation between the clock CLK and a horizontal synchronizing signal H-SYNC separated from a synchronizing signal separating circuit 12. Consequently, the distortion of pictures due to the jitter for video input from a VTR, laws of a tape (picture recording medium), or the like is prevented in this device in distinction from a device where the horizontal synchronizing signal H-SYNC is used as the horizontal synchronizing signal for picture processing as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a video input processing device that samples a video signal for one frame, converts the sampled data from analog to digital, and stores it in an image memory.

[Technical background of the invention and its n';] Topic 8 people 1] HlVTR (Video Tap) is a video input processing device of this type.
Video signal VIDE from e Recorder) etc.
O is input to the VC video amplifier 11 and the synchronization separation circuit 12 as shown in FIG.
The YNC signal and the vertical synchronizing signal v-5 are separated.

The output of the video amplifier 11 is sampled by a sandal hold amplifier (hereinafter referred to as S/H amplifier) J3 in accordance with a sampling clock CLK. This sampling clock CLKFi and the horizontal synchronizing signal H-i';
YNCVc is generated from the oscillation circuit 14. S/
The sampling output of 4I Ampno 3 is high-speed analog/
Digital converter (hereinafter referred to as A/D converter) 15
Vc supplies the A/D conversion signal to the interface circuit 17Vc with the image bus flow.

This interface circuit 17 receives sampling clocks CLK, l, - and clocks from the oscillation circuit J4.
A horizontal synchronizing signal H-8YNC and a vertical synchronizing signal V-SYNC from the V circuit 12 are also supplied.

The A/D variation data from the A/D converter 15 is written into the image memory 18 under the control of the interface circuit J7 in accordance with the horizontal synchronizing signal H-8YNC and the sampling clock CLK.

In such video input processing tricks, the oscillation circuit 14 is generally a PLL (Phase LockedL).
oop ) circuit is applied o However, in this circuit,
For example, if synchronization disturbance occurs due to VTR jitter or tape scratches, etc., the input signal (horizontal synchronization signal) 1
-5YNC and the sampling clock C which is the output signal
A phase shift with LK occurs. This resulted in screen distortion and video dropouts. In addition, the oscillation circuit 1
A video input processing device is also known in which a synchronous oscillator with di/l line as 4 is applied. However, since this circuit oscillates at a constant period regardless of the period of horizontal synchronization No. 46 H-8YNC, there is a problem in that an error occurs in the screen ratio.

[Purpose of the invention]

This invention has been made in view of the above circumstances, and its purpose is to provide a video input processing device that can eliminate screen distortion caused by jitter and video dropouts caused by tape scratches that occur during VTR input. 0 [Summary of the Invention] The present invention provides a video manual processing device that samples a video signal for one frame in accordance with a sampling clock, A/D converts the sampled data, and writes the sampled data into an image memory. 8, the HL is built in a PLL circuit that generates a sampling clock signal in synchronization with the horizontal synchronization signal separated from the video signal by the synchronization separation circuit.
By using the horizontal sync signal + for screen processing instead of the horizontal sync signal, it is possible to synchronize the horizontal periodic signal for screen processing with the sampling bone clock, and eliminate the distortion of the image 1 caused by disturbances in synchronization. I'm trying to prevent it.

Further, the present invention provides image data recording for one line.
A line memory for A/D converter (analog/digital converter) is provided in this line memory.
One line of conversion data is stored in accordance with the phase difference between the horizontal synchronization signal and the phase comparison signal, and a selection circuit selects either the output of the A/D converter or the output of the line memory as image data, and The configuration is such that the selected data is written to the image memory.0 By doing this, when the phase difference between the horizontal synchronization signal and the phase comparison signal becomes large due to a significant disturbance in synchronization, the selected data is written to the image memory. It becomes possible to use line data as image data.

[Embodiments of the invention]

FIG. 2 shows the configuration of a video input processing device according to an embodiment of the present invention. Note that the same parts as in FIG. 1 are given the same reference numerals and detailed explanations are omitted. Reference numeral 20 in Figure 2
The PLL circuit shown in 2 has a phase detector 2, a low-pass filter 22, and a VCO (Voltage Control
It has a well-known circuit configuration such as an LED (0scillator) 23 and a counter 24. A video signal VID (from a VTR or the like) is connected to one input terminal of a phase detector 21 in this PLL circuit 20 by a synchronization separation circuit 12.
The horizontal synchronizing signal H-8YNC separated from EO is inputted. Also, the other input terminal of the phase detector 2 is connected to the VC
The sampling clock CLK (
The phase comparison signal (frequency f/N) obtained by dividing the frequency f) by i/N by the counter 24 (divider)
) is inputgh. In this example, this phase comparison signal is used as a horizontal synchronization signal for image processing in place of the horizontal synchronization signal H-8YNC.

Therefore, this phase comparison signal is used as the horizontal synchronization signal M for image processing.
It will be referred to as H-SYNC'. This signal H
-8YNC' is the vertical synchronization signal V-8YNC separated from the video signal VIDEO by the synchronization separation circuit 12.
It is also supplied to the interface circuit 30. Also,
The signal H-8YNC' Vi is also supplied to a memory controller 40, which will be described later. In addition, the VCO of the PLL circuit 20 (
Sampling clock CLK output from 2, y)
u interface circuit 30 and memory controller 4
0, and the S/H amplifier 13 and A/D
It is supplied to converter 15.

Adding one frame worth of video signal VID from a VTR etc.
The signal is sampled by the S/H amplifier 13 at the timing of the sampling clock CLK from the PLL circuit 20. This sampling data is sent to the A/D converter 15 in synchronization with the sampling clock CLK.
converted. Output line L1 of A/D converter 15 is connected to memory controller 40 and multiplexer 5Q. The memory controller 40 receives signals (1) as described above. -8YNσ and sampling clock CLK are supplied, and control signal CNT
is further supplied. This control signal CNT is P
This is a binary signal indicating whether the phase difference between the signals H-8YNC and H-8YNC' detected by the phase detector 21 of the LL circuit 20 is greater than or equal to a predetermined value. The control signal CNT is output from a control circuit 60 that compares the detection output of the phase detector 21 with a reference value.

Under normal conditions, signal H-8YNC is stable.

In this state, the signal H-3YNC' is the signal H-8YN
CK is completely synchronized. On the other hand, 12, for example, VTR
To the extent that the synchronization of the video signal VIDEO is disrupted due to jitter, tape loss, expansion/contraction, the signal H-8YNC
The phase of the signal l1-8YNC' is shifted from that of the signal l1-8YNC'. However, if the above synchronization disturbance is not large, the signal H-8YNC
.

The phase difference between l-1-8YNCZ does not exceed a predetermined value. Control circuit 60Fi signal H-8YNC.

If the phase difference between H-8YNC' is not greater than a predetermined value, the control signal CNT of logic ``0'' is output 1''.
Ru. This signal CNT is simultaneously fed to the multiplexer 50, and is also fed to the memory controller 40 as described above.

The memory controller 40 enters the interrupt mode when the signal CNT from the control circuit 60 is logic 1'0''. During the interrupt mode, the memory controller 40 receives the signal H-8YNC/ from the PLL circuit 2o. According to the timing of the sampling clock CLK, for example, 8 bits of A/D conversion data (image data) from the A/D converter 15 are stored in the line memory (one scan line, for example, 512 x 8 bits). The line memory 70 is a RAM having a memory capacity of, for example, 512 words x 8 bits.The output line L2 of the line memory 70 is connected to the multiplexer 50.

Multiplex→)-5O (selection circuit) responds to the logic state of the signal CNT17) from the control circuit 60,
Either one of the output lines L2 of the old line memory 70 and the output line L of the A/D converter J5 is switched to the output line L3 side to the interface circuit 30. C.N.
In this example of T-''''0'', the output line L1 of the A/D converter 15 is selectively switched to the output line L3 side by the multiplexer 5θ. That is,
In the case of CNT-'0'', the A/D conversion data output from the A/D converter 15 is supplied to the interface circuit 30 via the multiplexer 50.The interface circuit 30 includes a PLL as described above. The output of the counter 24 in the circuit 20 (phase comparison +3) is supplied as the horizontal synchronizing signal H-8YNC' for image processing.
In addition, the interface circuit 30 has a → running link.
A clock CLK and vertical synchronization signal V-8YNC are also supplied. The interface circuit 30 inputs the data supplied via the output line L3 to an image memory J8 having a capacity for one frame (for example, 512 x 512 It was noted that 7
) According to K, write in Gaga bus 16 lines.

The sampling clock CLK used for printing to the image plane 18 and the horizontal synchronization signal 1 (-8
YNC' (phase comparison signal), CLK and H-8YNC
Unlike the relationship between the video signals VII) and EO, they are completely synchronized regardless of the synchronization disturbance of the video signal VII)EO. Therefore, according to this embodiment, the horizontal direction ll separated from the synchronization separation circuit is
Unlike conventional equipment that uses the 1j signal (H-5YNC) as it is as a horizontal synchronizing signal for image processing, the VTR (r[1
It is possible to prevent screen distortion caused by jitter or scratches on the tape (image recording medium) in the video input from the image recording device).

Next, for example, due to scratches on the tape (image - [: recording medium), etc., the synchronization of the video signal VIDEO becomes greatly disturbed,
A platform in which the phase difference between the signals H-8YNC and H-8YNC' is equal to or greater than the standard value will be described. In this case, the control circuit 60 controls the logic "1" +-j
Output CNT.

The memory controller 40 enters the read mode when the signal CNT from the control circuit 60 is "1". During the readout mode, the memory controller 40 receives the signal H-8YNC from the PLL circuit 20. ' According to the timing of the sampling clock CLK, the contents stored in the line memory 70 (image data of the preceding line) are read out.

The read data from the line memory 70 is output 4")L
z to multiplexer 50.

The multiplexer 50 selectively switches the output line L2 of the line memory 70 to the output line L3 side while the signal CNT from the control circuit 60 is at logic "1". The data is passed through the multiplexer 5θ [7 to the interface circuit 3
0. The interface circuit 30 writes the data supplied through the output line L3 as image data into an area corresponding to the line after the image memory 18.

The above H:jL operation is performed when the signal CNT is logic "1" (
Igo No. 1 (if the phase difference between -8YNC and H-8YNC/ is greater than a predetermined value), A/D connector 15
Line memo IJ 7 instead of A/D conversion data from
The A/D back/boku data of the preceding line stored in o is used as the 1l17Ii image data of the second line,
Indicates that it is used. By doing so, it is possible to prevent dropout of the image due to tape scratches, etc., in particular.

Eventually, when the phase of KAJI H-8YNC becomes normal, IFI CN T from the control circuit 60 becomes lff1.
The i logic becomes “0”. This allows multiplexano “6”
0 is switched, and the A/Di conversion data from the A/D converter 15 is transferred to the interface circuit 3 at the multiplexer 50.
Supply to 0. 1, the memory controller 40 enters the I write mode due to CNT=ゝゝ0'', and writes the same data as the data supplied to the interface circuit 30 (A/D
The A/D data from the converter 15 is written to the line memory 70. Shinτ2, CNT=
During the period of ``0'', the latest line memory is always stored in the line memory 70. In this embodiment, I) the low filter 22 in the LL circuit 20 is stored in the line memory 70.
1-5 so that the PLL circuit 20 does not follow disturbances in the signal H-8YNC on several lines by setting a large time constant and increasing the lock-in time.

Although the input processing of video signals from a VTR has been described above in 1-j, the present invention can also be applied to input processing of video signals from other image recording devices such as sheet recorders. It can also be applied to a video input processing unit that handles color video signals.

[Efficacy of invention]

As described in detail above, according to the present invention, image distortion and video dropout can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional video input processing device.
FIG. 2 is a block configuration diagram of video input processing and drawing according to one embodiment f1.1 of the present invention. 12... Synchronous separation circuit, 13... Sample-hold amplifier (S/termination amplifier), 15... Analog/digital converter (A/D converter), No. 8... Image memory, 20... ...PLL circuit, 21...phase detector, 24...counter, 3o...interface...multiplexer, 7o...line memory.

Claims (1)

[Claims] The video signal for one frame is sampled according to the sampling clock, and the sampled data is converted from analog to digital by an analog/digital converter (7). a synchronization separation circuit that separates a horizontal synchronization signal and a vertical synchronization signal from the horizontal synchronization signal; and a synchronization separation circuit that generates the sampling clock in synchronization with the horizontal synchronization signal.
) L L circuit, which includes a PLL circuit that divides the sampling clock by l/N to generate a phase comparison signal for phase comparison with the horizontal synchronization signal, and a PLL circuit with a built-in divider and a phase comparison signal for one line. A line memory that stores image data,
a memory control means for storing one line of output data of the analog/digital converter in the line memory according to a phase difference between the horizontal synchronization signal and the phase comparison signal; Or a selection circuit that selects one of the outputs of the line memory according to the phase difference between the horizontal synchronization signal and the phase comparison signal, and the output of this selection circuit as the image memo! J vc writing interface circuit, which performs this data writing by
A video input processing device comprising: an interface circuit that uses the phase comparison signal as a horizontal synchronization signal for image processing.