JPH05197356A - Picture display device - Google Patents

Abstract

PURPOSE:To provide the picture display device which eliminates the change of the duty of a driving voltage to prevent the degradation of the picture quality even at the time of the variance of the horizontal synchronizing signal of a video signal. CONSTITUTION:The picture display device which reads out and displays at least a part of the video signal after storing it in a memory and displays it even in the flyback period of the video signal consists of a synchronous timing control circuit 25 which controls the write timing of the video signal to the memory 29 synchronously with the horizontal synchronizing signal of the video signal and an asynchronous timing control circuit 23 which controls the read timing of the video signal from the memory 29 asynchronously with the horizontal synchronizing signal of the video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device which stores at least a part of a video signal in a memory and then reads and displays it.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional simple matrix type liquid crystal display device. That is, a video signal 1 such as a VTR reproduction signal is supplied to the chroma circuit 2. The chroma circuit 2 receives the composite sync signal CS and the color signal R from the video signal 1,
G, B are generated, the composite synchronizing signal CS is supplied to the PLL circuit 4, and the color signals R, G, B are supplied to the A / D conversion circuit 7. The synchronous timing control circuit 5 generates the comparison signal PH and supplies it to the PLL circuit 4. The PLL circuit 4 synchronizes by phase comparison between the horizontal synchronizing signal of the composite synchronizing signal CS and the comparison signal PH to generate a reference clock OSC, and supplies the reference clock OSC to the synchronous timing control circuit 5. The synchronous timing control circuit 5 includes a sampling clock signal φs, a read / write control signal R / W, a signal electrode drive circuit control signal S from the reference clock OSC.
1. The scan electrode drive circuit control signal S2 is generated, the sampling clock signal φs is supplied to the A / D conversion circuit 7,
The read / write control signal R / W is supplied to the memory 9, the signal electrode drive circuit control signal S1 is supplied to the signal electrode drive circuit 11, and the scan electrode drive circuit control signal S2 is supplied to the scan electrode drive circuit 12. The A / D conversion circuit 7 supplies the color signals R, G, B based on the sampling clock signal φs.
As shown in FIG. 5, fields f1, f2, f3 ...
Each time sampling is performed, digital data 8 is generated and supplied to the memory 9. The memory 9 has a read / write control signal R /
The digital data 8 is written based on W. The digital data stored in the memory 9 is read / write control signal R / W.
And is supplied to the signal electrode drive circuit 11. Signal electrode drive circuit 11 and scan electrode drive circuit 12
Respectively drive the liquid crystal panel 10 based on the signal electrode drive circuit control signal S1 and the scan electrode drive circuit control signal S2, and as shown in FIG. 5, fields f1, f2, f3 ...
…… Displays an image with each display signal.

[0003]

In order to improve the contrast of the conventional simple matrix type liquid crystal display device, in recent years the frame frequency for scanning the liquid crystal panel is 120 Hz, 2
A system of 40 Hz or the like has been developed. The liquid crystal panel is often scanned during the vertical blanking period. Thus, the synchronous timing control circuit 5 is synchronized with the horizontal synchronizing signal of the composite synchronizing signal CS by the PLL circuit 4, but in the reproduction signal of the VTR, the fields f1 and f are used.
The display signal for each of 2, f3, ... May fluctuate due to the disturbance of the composite synchronizing signal CS during the vertical blanking period. or,
The 1H period may fluctuate when the head is switched for each field. The scan electrode selection period when the liquid crystal panel is driven at 120 Hz is 1 / 2H, and the scan electrode selection period is 1/2
In H, the signal electrode drive circuit applies a voltage corresponding to the data by pulse width modulation, but as the display signal changes by 1H, the scan electrode selection period 1 / 2H also changes. In the screen because the duty changes,
There is a drawback in that there is a portion where the brightness changes.

The present invention has been made in view of the above circumstances, and provides an image display device capable of preventing the deterioration of image quality by eliminating the change of the duty of the drive voltage even if the horizontal synchronizing signal of the video signal changes. The purpose is to do.

[0005]

In order to solve the above-mentioned problems, the present invention controls the writing timing of a video signal to a memory by a synchronous timing control circuit which is synchronized with the horizontal synchronizing signal of the video signal, The asynchronous timing control circuit, which is not synchronized with the horizontal synchronizing signal, controls the timing of reading the video signal from the memory.

[0006]

With the above means, the asynchronous timing control circuit which is not synchronized with the horizontal synchronizing signal of the video signal controls the timing of reading the video signal from the memory, so that the horizontal synchronizing signal of the video signal varies. It is possible to prevent the deterioration of the image quality by eliminating the change of the duty of the drive voltage.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a simple matrix type liquid crystal display device according to an embodiment of the present invention. That is, VT
A video signal 21 such as an R reproduction signal is supplied to the chroma circuit 22. The chroma circuit 22 generates the composite sync signal CS and the color signals R, G, B from the video signal 21, and outputs the composite sync signal CS.
Is supplied to the PLL circuit 24, and the color signals R, G, B are A /
It is supplied to the D conversion circuit 27. The synchronous timing control circuit 25 has, for example, a duty cycle of 1H (horizontal scanning period).
A comparison signal PH, which is a reference signal composed of a 0% clock pulse, is generated and supplied to the PLL circuit 24. This PLL
The circuit 24 is configured as shown in FIG. That is, the comparison signal PH, which is a reference signal, is input from the synchronous timing control circuit 25 to the phase comparison analog switch 41, and the composite synchronization signal CS is input from the chroma circuit 22 to the input terminal 4.
2, input as a control signal via the inverter 43. The analog switch 41 is opened and closed according to the horizontal synchronizing signal of the composite synchronizing signal CS input from the terminal 42 via the inverter 43, and outputs the clock pulse PD to the low pass filter 44. The low-pass filter 44 integrates the clock pulse PD input from the analog switch 41 and outputs it to the voltage controlled oscillator (VCO) 45. In this voltage controlled oscillator 45, the low pass filter 4
4 a reference clock OSC of the oscillation frequency f _VCO of the number MH _z which is determined by the input output voltage level generated from the outputs from the output terminal 46 to the synchronous timing control circuit 25. That is, the PLL circuit 24 is a negative feedback circuit composed of the analog switch 41 for phase comparison, the low-pass filter 44, and the voltage controlled oscillator (VCO) 45, and the comparison signal PH as the reference signal and the composite synchronization signal as the control signal. The control voltage of the voltage controlled oscillator 45 is automatically controlled so as to be synchronized with the horizontal synchronizing signal of CS by phase comparison. The synchronous timing control circuit 25 receives the sampling clock signal φ from the reference clock OSC.
s, a write control signal W, and a vertical sync signal VS are generated, the sampling clock signal φs is supplied to the A / D conversion circuit 27, the write control signal W is supplied to the memory 29, and the vertical sync signal VS is asynchronous timing control. Supply to the circuit 23. The A / D conversion circuit 27 samples the color signals R, G, B for each field f1, f2, f3, ... As shown in FIG. 2 based on the sampling clock signal φs to generate digital data 28, Supply to the memory 29. The memory 29 writes the digital data 28 based on the write control signal W at the timing shown in FIG. The asynchronous timing control circuit 23 is self-running at a fixed cycle by the crystal oscillator 26, and only the vertical synchronization signal VS supplied from the synchronous timing control circuit 25 synchronizes each field f1, f2, f3 .... Then, the read control signal R, the signal electrode drive circuit control signal S11, and the scan electrode drive circuit control signal S12 are generated, and the read control signal R is supplied to the memory 29 to generate the signal electrode drive circuit control signal S.
11 is supplied to the signal electrode drive circuit 31, and the scan electrode drive circuit control signal S12 is supplied to the scan electrode drive circuit 32.
The digital data stored in the memory 29 is read at a timing shown in FIG. 2 based on the read control signal R and supplied to the signal electrode drive circuit 31. The signal electrode drive circuit 31 and the scan electrode drive circuit 32 drive the liquid crystal panel 30 based on the signal electrode drive circuit control signal S11 and the scan electrode drive circuit control signal S12, respectively, and as shown in FIG. ……… Displays images with each display signal. Therefore, the one stored in memory
The video signal for the field is read twice during one field period.

When writing data in the memory by the synchronous timing control circuit, scanning lines can be thinned out by operating the write address. Therefore, it can be applied to other systems such as the PAL system by changing the chroma circuit.

[0010]

As described above, according to the present invention, the asynchronous timing control circuit which is not synchronized with the horizontal synchronizing signal of the video signal controls the timing of reading the video signal from the memory, thereby Even if the horizontal synchronizing signal fluctuates, it is possible to prevent the deterioration of the image quality by eliminating the change of the duty of the drive voltage.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an example of operation timing of each unit in FIG.

FIG. 3 is a circuit diagram showing an example of the PLL circuit of FIG.

FIG. 4 is a configuration explanatory view showing a conventional image display device.

5 is a timing chart showing the operation timing of each part of FIG.

[Explanation of symbols]

21 ... Video signal, 22 ... Chroma circuit, 23 ... Asynchronous timing control circuit, 24 ... PLL circuit, 25 ... Synchronous timing control circuit, 26 ... Crystal oscillator, 27 ... A / D conversion circuit, 28 ... Digital data, 29 ... memory, 30 ...
Liquid crystal panel, 31 ... Signal electrode drive circuit, 32 ... Scan electrode drive circuit.

Claims (2)

[Claims] 1. An image display device comprising a memory, wherein at least a part of a video signal is stored in the memory and then read and displayed, and also during the blanking period of the video signal, a horizontal display of the video signal is provided. Synchronous timing control circuit that controls the timing of writing the video signal to the memory in synchronization with the synchronizing signal, and asynchronous that controls the timing of reading the video signal from the memory without synchronizing with the horizontal synchronizing signal of the video signal And an image timing control circuit. 2. The image display device according to claim 1, wherein the video signal for one field stored in the memory is read a plurality of times during one field period.