JPH0260383A - Vtr - Google Patents

Abstract

PURPOSE:To output a character signal even at the time of the absence of a video signal by superposing a synchronizing signal from a synchronizing signal generating circuit onto the character signal from a character generating circuit and taking out the to a line output terminal. CONSTITUTION:The synchronizing signal of a video terminal 1 is separated by a synchronizing signal separating circuit 7, and the separated synchronizing signal is supplied to a synchronizing signal generating circuit 12 through a PLL circuit consisting of a phase comparing circuit 9, a switch 10, and a VCO 11. The synchronizing signal generated by the circuit 12 is supplied to a character generating circuit 15, and an arbitrary generated character signal is superposed onto the video signal by switches 3 and 4 and is taken out to a line output terminal 6. When the video signal is not obtained, a switch 10 is turned off to set the PLL circuit to the free driving state, and the synchronizing signal from the circuit 12 is superposed onto the character signal from the circuit 15 and is taken out to the terminal 6 by a switch 5. Thus, the character signal is outputted though there is not the video signal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to, for example, a consumer VTR.

[Summary of the invention]

The present invention relates to a VTR, in which an arbitrary character signal is superimposed on a video signal and outputted, a character signal is generated using a synchronization signal from a synchronization generation circuit, and a synchronization signal from the generation circuit is superimposed on the character signal. This allows character signals to be output even when there is no video signal.

[Conventional technology]

For example, in a consumer VTR, so-called character signals such as characters, symbols, and figures for displaying a tape counter, mode display, or various warnings are superimposed on the video signal and sent to a monitor receiver, etc. through a line output terminal. It is thought that it will be projected.

In this case, conventionally, the synchronization signal of the video signal is separated, the character generation circuit is driven by this synchronization signal, and the generated character signal is superimposed on the video signal.

[Problem to be solved by the invention]

However, in the advanced configuration, for example, when line input is selected and no signal is supplied to the terminal, or when reception is not performed in built-in tuner mode, or when the video signal is not recorded on a tape or only with an AFM signal, When a video signal is not obtained, such as when playing back a tape on which no information has been recorded, the above-mentioned character signal cannot be generated and no projection can be performed. However, even in such a case, the above information is required.

This application was filed in view of these points.

[Means to solve the problem]

In a VTR having a line output terminal (6), the present invention separates the synchronization signal of the video signal (terminal (1)) from the recording/playback system when outputting an arbitrary character signal to the line output terminal. +71)L, this separated synchronization signal is passed through the PLL circuit (phase comparison circuit (9) to v co (
11)) to a synchronization generation circuit (12), and supplying the generated synchronization signal to a character generation circuit (15);
This generated arbitrary character signal is superimposed on the video signal (switch (31 (41)) and taken out to the line output terminal, and when the video signal is not obtained (OR circuit (29)), the PLL circuit The free driving shape a (
This is a VTR in which a switch (10) is set, and a synchronization signal from the synchronization generation circuit is superimposed on a character signal from the character generation circuit (switch +51) and outputted to the line output terminal.

[For production]

According to this, when there is no video signal, the PLL circuit is freely driven to drive the synchronization generation circuit and the character generation circuit, and the generated synchronization signal and character signal are superimposed to display a good character signal. be able to.

〔Example〕

In FIG. 1, (1) is an input terminal to which a video signal is supplied from a recording/playback system (not shown), and the video signal from this terminal (1) is supplied to a clamp circuit (2). The DC level is fixed. This clamp circuit (2
) is taken out to the line output terminal (6) through a series circuit of switch +31 (41 (51).

Also, the signal from the clamp circuit (2) is transmitted to the synchronous separation circuit (7).
). The synchronization signal separated by this separation circuit (7) is further supplied to a horizontal synchronization separation circuit (8) to separate the horizontal synchronization signal HD. This horizontal synchronization signal HD is supplied to the phase comparison circuit (9), and the comparison output is sent to the switch (1
0) and is supplied to a variable oscillator (VCO) (11), and this oscillation output is supplied to a synchronization generation circuit (12).

The generated horizontal synchronizing signal HD is then transferred to the phase comparator circuit (9).
) to configure the PLL circuit, and the synchronization generation circuit (
The phase of the horizontal synchronization signal HD from 12) is matched to the input video signal.

Further, the synchronization signal separated by the separation circuit (7) is further supplied to the vertical synchronization separation circuit (13) to separate the vertical synchronization signal VD. This vertical synchronization signal VD is an OR circuit (14)
is supplied to the reset of the synchronization generation circuit (12) through. The phase of the vertical synchronization signal thus generated is matched with the input video signal.

The horizontal and vertical synchronization signals HD-VD generated by the synchronization generation circuit (12) are supplied to the character generation circuit (15). As a result, the character generating circuit (15) generates an arbitrary character signal and its background signal synchronized with the input video signal. The character signal and background signal are supplied to AND circuits (16) and (17), respectively. A terminal (18) is supplied with a control signal (data screen 0N10FF) for determining whether or not to superimpose a character signal on a line output video signal, and this control signal is supplied to AND circuits (16) and (17). As a result, when a character signal is superimposed on a line output video signal (data screen ON), a character signal and a background signal are outputted through AND circuits (16) and (17). The background signal from this AND circuit (17) is supplied to control the switch (3) through the OR circuit (19), and during this time the switch (3) is connected to the black level DC voltage source (
20).

Also, the character signal from the AND circuit (16) is sent to the switch (4).
), during which the switch (4) is switched to the white level DC voltage source (21).

In this manner, the character signal is superimposed on the video signal in the above circuit, and this superimposed signal is taken out to the line output terminal (6). Furthermore, when this circuit is applied to a camera-type VTR, the signal taken out to the line output terminal (6) is supplied to the base of the buffer transistor (23) through the resistor (22), From the emitter of this transistor (23) to the electronic viewfinder (
EVF) is supplied to the output terminal (24).

Furthermore, when the character signal is not superimposed on the line output video signal (data screen 0FF) using the above circuit,
The output signals from the AND circuits (16) and (17) are cut off. On the other hand, the character signal from the character generation circuit (15) is supplied to the AND circuit (25), and the control signal from the terminal (18) is passed through the inverter (26) to the AND circuit (25).
25). The signal from this AND circuit (25) passes through the resistor (27) to the transistor (23).
) is supplied to the base. As a result, a video signal on which no character signal is superimposed is taken out to the line output terminal (6), and the character signal from the AND circuit (25) is synthesized with this video signal by the resistors (22) and (27). The composite signal is taken out to the EVF output terminal (24) through the transistor (23).

A synchronization signal from a synchronization separation circuit (7) is supplied to this circuit to a detection circuit (28), and the presence or absence of a synchronization signal (video signal) is determined. This detection circuit (28)
When there is a video signal from , the high potential signal is inverted and supplied to the OR circuit (29). Further, a control signal for muting the video signal is supplied to the terminal (30), and this control signal is supplied to the OR circuit (29). The signal from this OR circuit (29) is supplied to the OR circuits (14) (19) and also to the control of the switch (10),
During this time, the switch (10) is turned off.

Further, a signal is supplied from the OR circuit (29) to control the switch (31), and during this time, a composite synchronization signal 5ync from the synchronization generation circuit (12) is supplied to the control of the switch (5) through the switch (31). The switch (5) is switched to a sink tip level DC voltage source (32).

Therefore, in this circuit, when the control signal from the terminal (18) has a high potential and the output signal of the OR circuit (29) has a high potential, the switch (10) is turned off and the OR circuit (1
4) is cut off, V CO (11) is driven freely (free run), and the synchronization generating circuit (12) is switched to C0 (11).
is driven by the oscillation output of The signal from this synchronization generation circuit (12) is then supplied to the character generation circuit (15), which generates a character signal synchronized with this, and the AND circuit (
The switch (4) is controlled through the switch (16), and the output of the OR circuit (19) is set to a high potential in the background, and the switch (3) is switched to the black level. Furthermore, the composite synchronization signal 5ync from the synchronization generation circuit (12) is applied to the switch (3).
1) to control the switch (5), a synchronization signal is added, a character signal is superimposed on this black level background, and the signal with the composite synchronization signal added is sent to the line output terminal (6) and the EVF output. Several companies are located at the terminal (24).

Furthermore, when the control signal from the terminal (18) is at a low potential, the AND circuit (16) is cut off, and a signal with a composite sync signal added to the black level background is output to the line output terminal (6). , This signal is combined with the character signal from the AND circuit (25) at the resistors (22) and (27), and the EV
It is taken out to the F output terminal (24).

In addition, when the above-mentioned circuit is applied to V'r R having a jog mode, the pseudo vertical synchronization signal (jog VD) supplied to the terminal (33) is controlled by the switch (5) through the switch (31). can be supplied to measure screen stability in jog mode. In addition, the control signals and jog VD supplied to the terminals (18) (30) (33) in the above circuit are controlled by a microcomputer (μmC) for control.
0M) etc.

According to the above-mentioned circuit, when there is no video signal, the PLL circuit is freely driven to drive the synchronization generation circuit and the character generation circuit, and the generated synchronization signal and character signal are superimposed to produce a good image of the character signal. You can make an exit.

That is, in the above-mentioned circuit, the operation is summarized as shown in FIG.

Furthermore, FIG. 3 shows a specific example of the main part of the PLL circuit applied to the above-mentioned circuit. In the figure, this example has a so-called charge pump type circuit configuration, and the phase comparison circuit (
The up (UP) or down (DN) control signals from 9) are supplied to control the tri-state buffers (41a) (41b) through OR circuits (10a) (10b) forming the switch/7ch (10), respectively. be done. And when controlling the amplifier, use the tri-state buffer (41a)
is turned on and the power supply V is supplied to the VCO (11) through resistors (42a) (43) and capacitors (44) (45), and when in down control, the tri-state buffer (41b) is turned on and grounded. The potential is the resistor (42b
) (43) , Vc through D 7 capacitors (44) (45).

(11). This allows V CO(11)
control is performed. In this case, the characteristics of the loop filter of the so-called PLL circuit are as follows:
2b) (43), capacitors (44) (45).

Koreni vs. Jiasuiachi (10) (, t TD road (
When IOa) (10b)) is switched, the high potential from the OR circuit (29) is applied to the tri-state buffer (4).
1a) (41b). As a result, the tri-state buffers (41a) and (41b) are both turned on, and the power supply is turned on. , and the ground potential is a resistor (42a)
(42b). Therefore this resistor (
42a) (42b) becomes a bias circuit for VCO (11). For example, by keeping these resistance values equal, a potential of 2 VDD is supplied to VCO (11), and VCO (11) is set to the desired frequency. is driven freely.

In other words, according to this circuit, when the conventional phase comparator circuit - loop filter -> analog switch -> bias circuit = ■C○ is connected, a buffer circuit is required between the loop filter and the bias circuit, or a buffer circuit is required between the loop filter and the bias circuit. If there is no circuit, it is possible to solve the problem that the gain of the loop filter decreases due to the influence of the bias circuit and the phase lock error increases.

〔Effect of the invention〕

According to this invention, when there is no video signal, the PLL circuit is freely driven to drive the synchronization generation circuit and the character generation circuit, and the generated synchronization signal and character signal are superimposed,
It is now possible to display good character signals.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. (1) is video input terminal, (2) is clamp circuit, +3
1 +41 (51 (10) (31) is a switch, (6
) is the line output terminal, (7) +81 (13) is the synchronous separation circuit, (9) is the phase comparison circuit, (11) is the variable oscillator,
(12) is a synchronization generation circuit, (14) (19) (29
) is an OR circuit, (15) is a character generation circuit, (16) (
17) (25) is an AND circuit, (18) (30)
(33) is a terminal, (20) (21) (32) is a voltage source, (22) (27) is a resistor, (23) is a transistor, (24) is an EVF output terminal, (26) is an inverter, ( 2) is the detection circuit.

Claims (1)

[Claims] In a VTR having a line output terminal, in order to output an arbitrary character signal to the line output terminal, the synchronization signal of the video signal from the recording/playback system is separated, and this separated synchronization signal is used. A synchronization signal is supplied to a synchronization generation circuit via a PLL circuit, the generated synchronization signal is supplied to a character generation circuit, and the generated arbitrary character signal is superimposed on the video signal and taken out to the line output terminal. . A VTR, wherein when the video signal is not obtained, the PLL circuit is put into a free drive state, and a synchronization signal from the synchronization generation circuit is superimposed on the character signal from the character generation circuit, and the superimposed signal is output to the line output terminal.